Lines Matching refs:ARM
93 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
94 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
95 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
96 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
97 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
98 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
99 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
100 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
103 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
104 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
105 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
106 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
107 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
108 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
109 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
110 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
114 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), in ARMBaseInstrInfo()
227 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
236 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
245 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
258 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
265 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
378 I->getOpcode() == ARM::t2DoLoopStartTP){ in analyzeBranch()
404 } else if (I->getOpcode() == ARM::t2LoopEnd && in analyzeBranch()
478 !isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd) in removeBranch()
488 if (!isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd) in removeBranch()
505 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
507 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); in insertBranch()
622 MI.getOperand(1).getReg() != ARM::CPSR) && in PredicateInstruction()
624 MI.getOperand(1).setReg(ARM::NoRegister); in PredicateInstruction()
663 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR); in ClobbersPredicate()
664 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR; in ClobbersPredicate()
684 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
692 case ARM::tADC: // ADC (register) T1 in isEligibleForITBlock()
693 case ARM::tADDi3: // ADD (immediate) T1 in isEligibleForITBlock()
694 case ARM::tADDi8: // ADD (immediate) T2 in isEligibleForITBlock()
695 case ARM::tADDrr: // ADD (register) T1 in isEligibleForITBlock()
696 case ARM::tAND: // AND (register) T1 in isEligibleForITBlock()
697 case ARM::tASRri: // ASR (immediate) T1 in isEligibleForITBlock()
698 case ARM::tASRrr: // ASR (register) T1 in isEligibleForITBlock()
699 case ARM::tBIC: // BIC (register) T1 in isEligibleForITBlock()
700 case ARM::tEOR: // EOR (register) T1 in isEligibleForITBlock()
701 case ARM::tLSLri: // LSL (immediate) T1 in isEligibleForITBlock()
702 case ARM::tLSLrr: // LSL (register) T1 in isEligibleForITBlock()
703 case ARM::tLSRri: // LSR (immediate) T1 in isEligibleForITBlock()
704 case ARM::tLSRrr: // LSR (register) T1 in isEligibleForITBlock()
705 case ARM::tMUL: // MUL T1 in isEligibleForITBlock()
706 case ARM::tMVN: // MVN (register) T1 in isEligibleForITBlock()
707 case ARM::tORR: // ORR (register) T1 in isEligibleForITBlock()
708 case ARM::tROR: // ROR (register) T1 in isEligibleForITBlock()
709 case ARM::tRSB: // RSB (immediate) T1 in isEligibleForITBlock()
710 case ARM::tSBC: // SBC (register) T1 in isEligibleForITBlock()
711 case ARM::tSUBi3: // SUB (immediate) T1 in isEligibleForITBlock()
712 case ARM::tSUBi8: // SUB (immediate) T2 in isEligibleForITBlock()
713 case ARM::tSUBrr: // SUB (register) T1 in isEligibleForITBlock()
762 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
792 case ARM::CONSTPOOL_ENTRY: in getInstSizeInBytes()
793 case ARM::JUMPTABLE_INSTS: in getInstSizeInBytes()
794 case ARM::JUMPTABLE_ADDRS: in getInstSizeInBytes()
795 case ARM::JUMPTABLE_TBB: in getInstSizeInBytes()
796 case ARM::JUMPTABLE_TBH: in getInstSizeInBytes()
800 case ARM::SPACE: in getInstSizeInBytes()
802 case ARM::INLINEASM: in getInstSizeInBytes()
803 case ARM::INLINEASM_BR: { in getInstSizeInBytes()
829 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
830 : ARM::MRS; in copyFromCPSR()
841 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
849 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
850 : ARM::MSR; in copyToCPSR()
861 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
878 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
892 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
893 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
896 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
903 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
904 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
908 Opc = ARM::VMOVS; in copyPhysReg()
910 Opc = ARM::VMOVRS; in copyPhysReg()
912 Opc = ARM::VMOVSR; in copyPhysReg()
913 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64()) in copyPhysReg()
914 Opc = ARM::VMOVD; in copyPhysReg()
915 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
916 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MQPRCopy; in copyPhysReg()
921 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) in copyPhysReg()
923 if (Opc == ARM::MVE_VORR) in copyPhysReg()
925 else if (Opc != ARM::MQPRCopy) in copyPhysReg()
936 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
937 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
938 BeginIdx = ARM::qsub_0; in copyPhysReg()
940 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
941 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
942 BeginIdx = ARM::qsub_0; in copyPhysReg()
945 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
946 Opc = ARM::VMOVD; in copyPhysReg()
947 BeginIdx = ARM::dsub_0; in copyPhysReg()
949 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
950 Opc = ARM::VMOVD; in copyPhysReg()
951 BeginIdx = ARM::dsub_0; in copyPhysReg()
953 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
954 Opc = ARM::VMOVD; in copyPhysReg()
955 BeginIdx = ARM::dsub_0; in copyPhysReg()
957 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
958 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; in copyPhysReg()
959 BeginIdx = ARM::gsub_0; in copyPhysReg()
961 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
962 Opc = ARM::VMOVD; in copyPhysReg()
963 BeginIdx = ARM::dsub_0; in copyPhysReg()
966 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
967 Opc = ARM::VMOVD; in copyPhysReg()
968 BeginIdx = ARM::dsub_0; in copyPhysReg()
971 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
972 Opc = ARM::VMOVD; in copyPhysReg()
973 BeginIdx = ARM::dsub_0; in copyPhysReg()
976 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
978 Opc = ARM::VMOVS; in copyPhysReg()
979 BeginIdx = ARM::ssub_0; in copyPhysReg()
981 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
984 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
987 } else if (DestReg == ARM::VPR) { in copyPhysReg()
988 assert(ARM::GPRRegClass.contains(SrcReg)); in copyPhysReg()
989 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg) in copyPhysReg()
993 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
994 assert(ARM::GPRRegClass.contains(DestReg)); in copyPhysReg()
995 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg) in copyPhysReg()
999 } else if (DestReg == ARM::FPSCR_NZCV) { in copyPhysReg()
1000 assert(ARM::GPRRegClass.contains(SrcReg)); in copyPhysReg()
1001 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg) in copyPhysReg()
1005 } else if (SrcReg == ARM::FPSCR_NZCV) { in copyPhysReg()
1006 assert(ARM::GPRRegClass.contains(DestReg)); in copyPhysReg()
1007 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg) in copyPhysReg()
1036 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) { in copyPhysReg()
1040 if (Opc == ARM::MVE_VORR) in copyPhysReg()
1045 if (Opc == ARM::MOVr) in copyPhysReg()
1064 (MI.getOpcode() == ARM::VORRq && in isCopyInstrImpl()
1127 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1128 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH)) in storeRegToStackSlot()
1138 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1139 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12)) in storeRegToStackSlot()
1145 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1146 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS)) in storeRegToStackSlot()
1152 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1153 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off)) in storeRegToStackSlot()
1163 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1164 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD)) in storeRegToStackSlot()
1170 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1172 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); in storeRegToStackSlot()
1173 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1174 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1180 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA)) in storeRegToStackSlot()
1184 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1185 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1191 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1194 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64)) in storeRegToStackSlot()
1201 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA)) in storeRegToStackSlot()
1207 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1209 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32)); in storeRegToStackSlot()
1219 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1223 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo)) in storeRegToStackSlot()
1231 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1235 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1236 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1237 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1243 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
1244 ARM::MQQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
1245 ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1250 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo)) in storeRegToStackSlot()
1257 BuildMI(MBB, I, DebugLoc(), get(ARM::MQQPRStore)) in storeRegToStackSlot()
1263 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1267 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1268 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1269 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1270 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1276 if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1278 BuildMI(MBB, I, DebugLoc(), get(ARM::MQQQQPRStore)) in storeRegToStackSlot()
1282 } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1283 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) in storeRegToStackSlot()
1287 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1288 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1289 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1290 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1291 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
1292 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
1293 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
1294 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
1307 case ARM::STRrs: in isStoreToStackSlot()
1308 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. in isStoreToStackSlot()
1316 case ARM::STRi12: in isStoreToStackSlot()
1317 case ARM::t2STRi12: in isStoreToStackSlot()
1318 case ARM::tSTRspi: in isStoreToStackSlot()
1319 case ARM::VSTRD: in isStoreToStackSlot()
1320 case ARM::VSTRS: in isStoreToStackSlot()
1321 case ARM::VSTR_P0_off: in isStoreToStackSlot()
1322 case ARM::MVE_VSTRWU32: in isStoreToStackSlot()
1329 case ARM::VST1q64: in isStoreToStackSlot()
1330 case ARM::VST1d64TPseudo: in isStoreToStackSlot()
1331 case ARM::VST1d64QPseudo: in isStoreToStackSlot()
1337 case ARM::VSTMQIA: in isStoreToStackSlot()
1343 case ARM::MQQPRStore: in isStoreToStackSlot()
1344 case ARM::MQQQQPRStore: in isStoreToStackSlot()
1384 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1385 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg) in loadRegFromStackSlot()
1394 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1395 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1400 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1401 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1406 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1407 BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg) in loadRegFromStackSlot()
1416 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1417 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1422 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1426 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1427 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1428 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1434 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
1438 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1439 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1448 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in loadRegFromStackSlot()
1450 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1456 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1461 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
1463 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg); in loadRegFromStackSlot()
1472 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1475 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1481 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1485 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1486 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1487 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1495 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in loadRegFromStackSlot()
1496 ARM::MQQPRRegClass.hasSubClassEq(RC) || in loadRegFromStackSlot()
1497 ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1500 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1506 BuildMI(MBB, I, DL, get(ARM::MQQPRLoad), DestReg) in loadRegFromStackSlot()
1510 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1514 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1515 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1516 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1517 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1525 if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
1527 BuildMI(MBB, I, DL, get(ARM::MQQQQPRLoad), DestReg) in loadRegFromStackSlot()
1530 } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1531 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1535 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1536 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1537 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1538 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1539 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1540 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1541 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1542 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1557 case ARM::LDRrs: in isLoadFromStackSlot()
1558 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. in isLoadFromStackSlot()
1566 case ARM::LDRi12: in isLoadFromStackSlot()
1567 case ARM::t2LDRi12: in isLoadFromStackSlot()
1568 case ARM::tLDRspi: in isLoadFromStackSlot()
1569 case ARM::VLDRD: in isLoadFromStackSlot()
1570 case ARM::VLDRS: in isLoadFromStackSlot()
1571 case ARM::VLDR_P0_off: in isLoadFromStackSlot()
1572 case ARM::MVE_VLDRWU32: in isLoadFromStackSlot()
1579 case ARM::VLD1q64: in isLoadFromStackSlot()
1580 case ARM::VLD1d8TPseudo: in isLoadFromStackSlot()
1581 case ARM::VLD1d16TPseudo: in isLoadFromStackSlot()
1582 case ARM::VLD1d32TPseudo: in isLoadFromStackSlot()
1583 case ARM::VLD1d64TPseudo: in isLoadFromStackSlot()
1584 case ARM::VLD1d8QPseudo: in isLoadFromStackSlot()
1585 case ARM::VLD1d16QPseudo: in isLoadFromStackSlot()
1586 case ARM::VLD1d32QPseudo: in isLoadFromStackSlot()
1587 case ARM::VLD1d64QPseudo: in isLoadFromStackSlot()
1593 case ARM::VLDMQIA: in isLoadFromStackSlot()
1599 case ARM::MQQPRLoad: in isLoadFromStackSlot()
1600 case ARM::MQQQQPRLoad: in isLoadFromStackSlot()
1637 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1638 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()
1639 : ARM::LDMIA_UPD)) in expandMEMCPY()
1642 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1647 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1648 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
1649 : ARM::STMIA_UPD)) in expandMEMCPY()
1652 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1687 if (MI.getOpcode() == ARM::MEMCPY) { in expandPostRAPseudo()
1703 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) in expandPostRAPseudo()
1707 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1708 &ARM::DPRRegClass); in expandPostRAPseudo()
1709 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
1710 &ARM::DPRRegClass); in expandPostRAPseudo()
1735 MI.setDesc(get(ARM::VMOVD)); in expandPostRAPseudo()
1816 case ARM::tLDRpci_pic: in reMaterialize()
1817 case ARM::t2LDRpci_pic: { in reMaterialize()
1838 case ARM::tLDRpci_pic: in duplicate()
1839 case ARM::t2LDRpci_pic: { in duplicate()
1859 if (Opcode == ARM::t2LDRpci || Opcode == ARM::t2LDRpci_pic || in produceSameValue()
1860 Opcode == ARM::tLDRpci || Opcode == ARM::tLDRpci_pic || in produceSameValue()
1861 Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1862 Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel || in produceSameValue()
1863 Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1864 Opcode == ARM::t2MOV_ga_pcrel) { in produceSameValue()
1875 if (Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1876 Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel || in produceSameValue()
1877 Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1878 Opcode == ARM::t2MOV_ga_pcrel) in produceSameValue()
1900 } else if (Opcode == ARM::PICLDR) { in produceSameValue()
1955 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1956 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1957 case ARM::LDRD: in areLoadsFromSameBasePtr()
1958 case ARM::LDRH: in areLoadsFromSameBasePtr()
1959 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1960 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1961 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1962 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1963 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1964 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1965 case ARM::t2LDRDi8: in areLoadsFromSameBasePtr()
1966 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1967 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1968 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1969 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1976 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1977 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1978 case ARM::LDRD: in areLoadsFromSameBasePtr()
1979 case ARM::LDRH: in areLoadsFromSameBasePtr()
1980 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1981 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1982 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1983 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1984 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1985 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1986 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1987 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1988 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1989 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
2041 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
2042 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
2043 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && in shouldScheduleLoadsNear()
2044 Load2->getMachineOpcode() == ARM::t2LDRBi8))) in shouldScheduleLoadsNear()
2087 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) in isSchedulingBoundary()
2098 if (!MI.isCall() && MI.definesRegister(ARM::SP)) in isSchedulingBoundary()
2118 if (LastMI->getOpcode() == ARM::t2Bcc) { in isProfitableToIfCvt()
2213 if (MI.getOpcode() == ARM::t2Bcc && in predictBranchSizeForIfCvt()
2255 if (Opc == ARM::B) in getMatchingCondBranchOpcode()
2256 return ARM::Bcc; in getMatchingCondBranchOpcode()
2257 if (Opc == ARM::tB) in getMatchingCondBranchOpcode()
2258 return ARM::tBcc; in getMatchingCondBranchOpcode()
2259 if (Opc == ARM::t2B) in getMatchingCondBranchOpcode()
2260 return ARM::t2Bcc; in getMatchingCondBranchOpcode()
2270 case ARM::MOVCCr: in commuteInstructionImpl()
2271 case ARM::t2MOVCCr: { in commuteInstructionImpl()
2276 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2332 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in analyzeSelect()
2353 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in optimizeSelect()
2432 {ARM::ADDSri, ARM::ADDri},
2433 {ARM::ADDSrr, ARM::ADDrr},
2434 {ARM::ADDSrsi, ARM::ADDrsi},
2435 {ARM::ADDSrsr, ARM::ADDrsr},
2437 {ARM::SUBSri, ARM::SUBri},
2438 {ARM::SUBSrr, ARM::SUBrr},
2439 {ARM::SUBSrsi, ARM::SUBrsi},
2440 {ARM::SUBSrsr, ARM::SUBrsr},
2442 {ARM::RSBSri, ARM::RSBri},
2443 {ARM::RSBSrsi, ARM::RSBrsi},
2444 {ARM::RSBSrsr, ARM::RSBrsr},
2446 {ARM::tADDSi3, ARM::tADDi3},
2447 {ARM::tADDSi8, ARM::tADDi8},
2448 {ARM::tADDSrr, ARM::tADDrr},
2449 {ARM::tADCS, ARM::tADC},
2451 {ARM::tSUBSi3, ARM::tSUBi3},
2452 {ARM::tSUBSi8, ARM::tSUBi8},
2453 {ARM::tSUBSrr, ARM::tSUBrr},
2454 {ARM::tSBCS, ARM::tSBC},
2455 {ARM::tRSBS, ARM::tRSB},
2456 {ARM::tLSLSri, ARM::tLSLri},
2458 {ARM::t2ADDSri, ARM::t2ADDri},
2459 {ARM::t2ADDSrr, ARM::t2ADDrr},
2460 {ARM::t2ADDSrs, ARM::t2ADDrs},
2462 {ARM::t2SUBSri, ARM::t2SUBri},
2463 {ARM::t2SUBSrr, ARM::t2SUBrr},
2464 {ARM::t2SUBSrs, ARM::t2SUBrs},
2466 {ARM::t2RSBSri, ARM::t2RSBri},
2467 {ARM::t2RSBSrs, ARM::t2RSBrs},
2485 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2507 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2534 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || in tryFoldSPUpdateIntoPushPop()
2535 MI->getOpcode() == ARM::VLDMDIA_UPD; in tryFoldSPUpdateIntoPushPop()
2536 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || in tryFoldSPUpdateIntoPushPop()
2537 MI->getOpcode() == ARM::tPOP || in tryFoldSPUpdateIntoPushPop()
2538 MI->getOpcode() == ARM::tPOP_RET; in tryFoldSPUpdateIntoPushPop()
2540 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && in tryFoldSPUpdateIntoPushPop()
2541 MI->getOperand(1).getReg() == ARM::SP)) && in tryFoldSPUpdateIntoPushPop()
2559 RegClass = &ARM::DPRRegClass; in tryFoldSPUpdateIntoPushPop()
2562 RegClass = &ARM::GPRRegClass; in tryFoldSPUpdateIntoPushPop()
2590 if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7)) in tryFoldSPUpdateIntoPushPop()
2649 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR) in rewriteARMFrameIndex()
2652 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2656 MI.setDesc(TII.get(ARM::MOVr)); in rewriteARMFrameIndex()
2664 MI.setDesc(TII.get(ARM::SUBri)); in rewriteARMFrameIndex()
2802 case ARM::CMPri: in analyzeCompare()
2803 case ARM::t2CMPri: in analyzeCompare()
2804 case ARM::tCMPi8: in analyzeCompare()
2810 case ARM::CMPrr: in analyzeCompare()
2811 case ARM::t2CMPrr: in analyzeCompare()
2812 case ARM::tCMPr: in analyzeCompare()
2818 case ARM::TSTri: in analyzeCompare()
2819 case ARM::t2TSTri: in analyzeCompare()
2837 case ARM::ANDri: in isSuitableForMask()
2838 case ARM::t2ANDri: in isSuitableForMask()
2873 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2874 (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) && in isRedundantFlagInstr()
2883 if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr && in isRedundantFlagInstr()
2892 if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
2893 (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) && in isRedundantFlagInstr()
2900 if (CmpI->getOpcode() == ARM::tCMPi8 && in isRedundantFlagInstr()
2901 (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) && in isRedundantFlagInstr()
2908 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2909 (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr || in isRedundantFlagInstr()
2910 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr()
2918 if (CmpI->getOpcode() == ARM::tCMPr && in isRedundantFlagInstr()
2919 (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 || in isRedundantFlagInstr()
2920 OI->getOpcode() == ARM::tADDrr) && in isRedundantFlagInstr()
2933 case ARM::tLSLri: in isOptimizeCompareCandidate()
2934 case ARM::tLSRri: in isOptimizeCompareCandidate()
2935 case ARM::tLSLrr: in isOptimizeCompareCandidate()
2936 case ARM::tLSRrr: in isOptimizeCompareCandidate()
2937 case ARM::tSUBrr: in isOptimizeCompareCandidate()
2938 case ARM::tADDrr: in isOptimizeCompareCandidate()
2939 case ARM::tADDi3: in isOptimizeCompareCandidate()
2940 case ARM::tADDi8: in isOptimizeCompareCandidate()
2941 case ARM::tSUBi3: in isOptimizeCompareCandidate()
2942 case ARM::tSUBi8: in isOptimizeCompareCandidate()
2943 case ARM::tMUL: in isOptimizeCompareCandidate()
2944 case ARM::tADC: in isOptimizeCompareCandidate()
2945 case ARM::tSBC: in isOptimizeCompareCandidate()
2946 case ARM::tRSB: in isOptimizeCompareCandidate()
2947 case ARM::tAND: in isOptimizeCompareCandidate()
2948 case ARM::tORR: in isOptimizeCompareCandidate()
2949 case ARM::tEOR: in isOptimizeCompareCandidate()
2950 case ARM::tBIC: in isOptimizeCompareCandidate()
2951 case ARM::tMVN: in isOptimizeCompareCandidate()
2952 case ARM::tASRri: in isOptimizeCompareCandidate()
2953 case ARM::tASRrr: in isOptimizeCompareCandidate()
2954 case ARM::tROR: in isOptimizeCompareCandidate()
2957 case ARM::RSBrr: in isOptimizeCompareCandidate()
2958 case ARM::RSBri: in isOptimizeCompareCandidate()
2959 case ARM::RSCrr: in isOptimizeCompareCandidate()
2960 case ARM::RSCri: in isOptimizeCompareCandidate()
2961 case ARM::ADDrr: in isOptimizeCompareCandidate()
2962 case ARM::ADDri: in isOptimizeCompareCandidate()
2963 case ARM::ADCrr: in isOptimizeCompareCandidate()
2964 case ARM::ADCri: in isOptimizeCompareCandidate()
2965 case ARM::SUBrr: in isOptimizeCompareCandidate()
2966 case ARM::SUBri: in isOptimizeCompareCandidate()
2967 case ARM::SBCrr: in isOptimizeCompareCandidate()
2968 case ARM::SBCri: in isOptimizeCompareCandidate()
2969 case ARM::t2RSBri: in isOptimizeCompareCandidate()
2970 case ARM::t2ADDrr: in isOptimizeCompareCandidate()
2971 case ARM::t2ADDri: in isOptimizeCompareCandidate()
2972 case ARM::t2ADCrr: in isOptimizeCompareCandidate()
2973 case ARM::t2ADCri: in isOptimizeCompareCandidate()
2974 case ARM::t2SUBrr: in isOptimizeCompareCandidate()
2975 case ARM::t2SUBri: in isOptimizeCompareCandidate()
2976 case ARM::t2SBCrr: in isOptimizeCompareCandidate()
2977 case ARM::t2SBCri: in isOptimizeCompareCandidate()
2978 case ARM::ANDrr: in isOptimizeCompareCandidate()
2979 case ARM::ANDri: in isOptimizeCompareCandidate()
2980 case ARM::t2ANDrr: in isOptimizeCompareCandidate()
2981 case ARM::t2ANDri: in isOptimizeCompareCandidate()
2982 case ARM::ORRrr: in isOptimizeCompareCandidate()
2983 case ARM::ORRri: in isOptimizeCompareCandidate()
2984 case ARM::t2ORRrr: in isOptimizeCompareCandidate()
2985 case ARM::t2ORRri: in isOptimizeCompareCandidate()
2986 case ARM::EORrr: in isOptimizeCompareCandidate()
2987 case ARM::EORri: in isOptimizeCompareCandidate()
2988 case ARM::t2EORrr: in isOptimizeCompareCandidate()
2989 case ARM::t2EORri: in isOptimizeCompareCandidate()
2990 case ARM::t2LSRri: in isOptimizeCompareCandidate()
2991 case ARM::t2LSRrr: in isOptimizeCompareCandidate()
2992 case ARM::t2LSLri: in isOptimizeCompareCandidate()
2993 case ARM::t2LSLrr: in isOptimizeCompareCandidate()
3053 if (CmpInstr.getOpcode() == ARM::CMPri || in optimizeCompareInstr()
3054 CmpInstr.getOpcode() == ARM::t2CMPri || in optimizeCompareInstr()
3055 CmpInstr.getOpcode() == ARM::tCMPi8) in optimizeCompareInstr()
3080 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) { in optimizeCompareInstr()
3083 if (I->getOpcode() != ARM::tMOVi8) { in optimizeCompareInstr()
3115 if (Instr.modifiesRegister(ARM::CPSR, TRI) || in optimizeCompareInstr()
3116 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
3161 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()
3165 if (!MO.isReg() || MO.getReg() != ARM::CPSR) in optimizeCompareInstr()
3179 case ARM::VSELEQD: in optimizeCompareInstr()
3180 case ARM::VSELEQS: in optimizeCompareInstr()
3181 case ARM::VSELEQH: in optimizeCompareInstr()
3184 case ARM::VSELGTD: in optimizeCompareInstr()
3185 case ARM::VSELGTS: in optimizeCompareInstr()
3186 case ARM::VSELGTH: in optimizeCompareInstr()
3189 case ARM::VSELGED: in optimizeCompareInstr()
3190 case ARM::VSELGES: in optimizeCompareInstr()
3191 case ARM::VSELGEH: in optimizeCompareInstr()
3194 case ARM::VSELVSD: in optimizeCompareInstr()
3195 case ARM::VSELVSS: in optimizeCompareInstr()
3196 case ARM::VSELVSH: in optimizeCompareInstr()
3210 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr || in optimizeCompareInstr()
3211 Opc == ARM::SUBri || Opc == ARM::t2SUBri || in optimizeCompareInstr()
3212 Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 || in optimizeCompareInstr()
3213 Opc == ARM::tSUBi8; in optimizeCompareInstr()
3214 unsigned OpI = Opc != ARM::tSUBrr ? 1 : 2; in optimizeCompareInstr()
3260 if (Succ->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
3267 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
3279 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
3307 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) in FoldImmediate()
3320 if (MO.getReg() == ARM::CPSR && !MO.isDead()) in FoldImmediate()
3329 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR) in FoldImmediate()
3342 case ARM::SUBrr: in FoldImmediate()
3343 case ARM::ADDrr: in FoldImmediate()
3344 case ARM::ORRrr: in FoldImmediate()
3345 case ARM::EORrr: in FoldImmediate()
3346 case ARM::t2SUBrr: in FoldImmediate()
3347 case ARM::t2ADDrr: in FoldImmediate()
3348 case ARM::t2ORRrr: in FoldImmediate()
3349 case ARM::t2EORrr: { in FoldImmediate()
3353 case ARM::ADDrr: in FoldImmediate()
3354 case ARM::SUBrr: in FoldImmediate()
3355 if (UseOpc == ARM::SUBrr && Commute) in FoldImmediate()
3361 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate()
3364 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
3370 case ARM::ORRrr: in FoldImmediate()
3371 case ARM::EORrr: in FoldImmediate()
3378 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; in FoldImmediate()
3379 case ARM::EORrr: NewUseOpc = ARM::EORri; break; in FoldImmediate()
3382 case ARM::t2ADDrr: in FoldImmediate()
3383 case ARM::t2SUBrr: { in FoldImmediate()
3384 if (UseOpc == ARM::t2SUBrr && Commute) in FoldImmediate()
3389 const bool ToSP = DefMI.getOperand(0).getReg() == ARM::SP; in FoldImmediate()
3390 const unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri; in FoldImmediate()
3391 const unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri; in FoldImmediate()
3393 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB; in FoldImmediate()
3396 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD; in FoldImmediate()
3403 case ARM::t2ORRrr: in FoldImmediate()
3404 case ARM::t2EORrr: in FoldImmediate()
3411 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; in FoldImmediate()
3412 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; in FoldImmediate()
3441 case ARM::t2ADDspImm: in FoldImmediate()
3442 case ARM::t2SUBspImm: in FoldImmediate()
3443 case ARM::t2ADDri: in FoldImmediate()
3444 case ARM::t2SUBri: in FoldImmediate()
3460 case ARM::LDRrs: in getNumMicroOpsSwiftLdSt()
3461 case ARM::LDRBrs: in getNumMicroOpsSwiftLdSt()
3462 case ARM::STRrs: in getNumMicroOpsSwiftLdSt()
3463 case ARM::STRBrs: { in getNumMicroOpsSwiftLdSt()
3475 case ARM::LDRH: in getNumMicroOpsSwiftLdSt()
3476 case ARM::STRH: { in getNumMicroOpsSwiftLdSt()
3491 case ARM::LDRSB: in getNumMicroOpsSwiftLdSt()
3492 case ARM::LDRSH: in getNumMicroOpsSwiftLdSt()
3495 case ARM::LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3496 case ARM::LDRSH_POST: { in getNumMicroOpsSwiftLdSt()
3502 case ARM::LDR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3503 case ARM::LDRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3519 case ARM::STR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3520 case ARM::STRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3532 case ARM::LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3533 case ARM::STRH_PRE: { in getNumMicroOpsSwiftLdSt()
3543 case ARM::LDR_POST_REG: in getNumMicroOpsSwiftLdSt()
3544 case ARM::LDRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3545 case ARM::LDRH_POST: { in getNumMicroOpsSwiftLdSt()
3551 case ARM::LDR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3552 case ARM::LDRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3553 case ARM::LDR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3554 case ARM::LDRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3555 case ARM::STRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3556 case ARM::STRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3557 case ARM::STRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3558 case ARM::STRH_POST: in getNumMicroOpsSwiftLdSt()
3559 case ARM::STR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3560 case ARM::STR_POST_REG: in getNumMicroOpsSwiftLdSt()
3561 case ARM::STR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3564 case ARM::LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3565 case ARM::LDRSH_PRE: { in getNumMicroOpsSwiftLdSt()
3583 case ARM::LDRD: { in getNumMicroOpsSwiftLdSt()
3593 case ARM::STRD: { in getNumMicroOpsSwiftLdSt()
3601 case ARM::LDRD_POST: in getNumMicroOpsSwiftLdSt()
3602 case ARM::t2LDRD_POST: in getNumMicroOpsSwiftLdSt()
3605 case ARM::STRD_POST: in getNumMicroOpsSwiftLdSt()
3606 case ARM::t2STRD_POST: in getNumMicroOpsSwiftLdSt()
3609 case ARM::LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3619 case ARM::t2LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3625 case ARM::STRD_PRE: { in getNumMicroOpsSwiftLdSt()
3633 case ARM::t2STRD_PRE: in getNumMicroOpsSwiftLdSt()
3636 case ARM::t2LDR_POST: in getNumMicroOpsSwiftLdSt()
3637 case ARM::t2LDRB_POST: in getNumMicroOpsSwiftLdSt()
3638 case ARM::t2LDRB_PRE: in getNumMicroOpsSwiftLdSt()
3639 case ARM::t2LDRSBi12: in getNumMicroOpsSwiftLdSt()
3640 case ARM::t2LDRSBi8: in getNumMicroOpsSwiftLdSt()
3641 case ARM::t2LDRSBpci: in getNumMicroOpsSwiftLdSt()
3642 case ARM::t2LDRSBs: in getNumMicroOpsSwiftLdSt()
3643 case ARM::t2LDRH_POST: in getNumMicroOpsSwiftLdSt()
3644 case ARM::t2LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3645 case ARM::t2LDRSBT: in getNumMicroOpsSwiftLdSt()
3646 case ARM::t2LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3647 case ARM::t2LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3648 case ARM::t2LDRSH_POST: in getNumMicroOpsSwiftLdSt()
3649 case ARM::t2LDRSH_PRE: in getNumMicroOpsSwiftLdSt()
3650 case ARM::t2LDRSHi12: in getNumMicroOpsSwiftLdSt()
3651 case ARM::t2LDRSHi8: in getNumMicroOpsSwiftLdSt()
3652 case ARM::t2LDRSHpci: in getNumMicroOpsSwiftLdSt()
3653 case ARM::t2LDRSHs: in getNumMicroOpsSwiftLdSt()
3656 case ARM::t2LDRDi8: { in getNumMicroOpsSwiftLdSt()
3662 case ARM::t2STRB_POST: in getNumMicroOpsSwiftLdSt()
3663 case ARM::t2STRB_PRE: in getNumMicroOpsSwiftLdSt()
3664 case ARM::t2STRBs: in getNumMicroOpsSwiftLdSt()
3665 case ARM::t2STRDi8: in getNumMicroOpsSwiftLdSt()
3666 case ARM::t2STRH_POST: in getNumMicroOpsSwiftLdSt()
3667 case ARM::t2STRH_PRE: in getNumMicroOpsSwiftLdSt()
3668 case ARM::t2STRHs: in getNumMicroOpsSwiftLdSt()
3669 case ARM::t2STR_POST: in getNumMicroOpsSwiftLdSt()
3670 case ARM::t2STR_PRE: in getNumMicroOpsSwiftLdSt()
3671 case ARM::t2STRs: in getNumMicroOpsSwiftLdSt()
3719 case ARM::VLDMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3720 case ARM::VLDMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3721 case ARM::VLDMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3722 case ARM::VLDMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3723 case ARM::VSTMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3724 case ARM::VSTMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3725 case ARM::VSTMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3726 case ARM::VSTMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3727 case ARM::LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3728 case ARM::LDMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3729 case ARM::LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3730 case ARM::LDMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3731 case ARM::STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3732 case ARM::STMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3733 case ARM::STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3734 case ARM::STMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3735 case ARM::tLDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3736 case ARM::tSTMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3737 case ARM::t2LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3738 case ARM::t2LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3739 case ARM::t2STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3740 case ARM::t2STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3743 case ARM::LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3744 case ARM::tPOP_RET: in getNumMicroOpsSingleIssuePlusExtras()
3745 case ARM::t2LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3771 case ARM::VLDMQIA: in getNumMicroOps()
3772 case ARM::VSTMQIA: in getNumMicroOps()
3785 case ARM::VLDMDIA: in getNumMicroOps()
3786 case ARM::VLDMDIA_UPD: in getNumMicroOps()
3787 case ARM::VLDMDDB_UPD: in getNumMicroOps()
3788 case ARM::VLDMSIA: in getNumMicroOps()
3789 case ARM::VLDMSIA_UPD: in getNumMicroOps()
3790 case ARM::VLDMSDB_UPD: in getNumMicroOps()
3791 case ARM::VSTMDIA: in getNumMicroOps()
3792 case ARM::VSTMDIA_UPD: in getNumMicroOps()
3793 case ARM::VSTMDDB_UPD: in getNumMicroOps()
3794 case ARM::VSTMSIA: in getNumMicroOps()
3795 case ARM::VSTMSIA_UPD: in getNumMicroOps()
3796 case ARM::VSTMSDB_UPD: { in getNumMicroOps()
3801 case ARM::LDMIA_RET: in getNumMicroOps()
3802 case ARM::LDMIA: in getNumMicroOps()
3803 case ARM::LDMDA: in getNumMicroOps()
3804 case ARM::LDMDB: in getNumMicroOps()
3805 case ARM::LDMIB: in getNumMicroOps()
3806 case ARM::LDMIA_UPD: in getNumMicroOps()
3807 case ARM::LDMDA_UPD: in getNumMicroOps()
3808 case ARM::LDMDB_UPD: in getNumMicroOps()
3809 case ARM::LDMIB_UPD: in getNumMicroOps()
3810 case ARM::STMIA: in getNumMicroOps()
3811 case ARM::STMDA: in getNumMicroOps()
3812 case ARM::STMDB: in getNumMicroOps()
3813 case ARM::STMIB: in getNumMicroOps()
3814 case ARM::STMIA_UPD: in getNumMicroOps()
3815 case ARM::STMDA_UPD: in getNumMicroOps()
3816 case ARM::STMDB_UPD: in getNumMicroOps()
3817 case ARM::STMIB_UPD: in getNumMicroOps()
3818 case ARM::tLDMIA: in getNumMicroOps()
3819 case ARM::tLDMIA_UPD: in getNumMicroOps()
3820 case ARM::tSTMIA_UPD: in getNumMicroOps()
3821 case ARM::tPOP_RET: in getNumMicroOps()
3822 case ARM::tPOP: in getNumMicroOps()
3823 case ARM::tPUSH: in getNumMicroOps()
3824 case ARM::t2LDMIA_RET: in getNumMicroOps()
3825 case ARM::t2LDMIA: in getNumMicroOps()
3826 case ARM::t2LDMDB: in getNumMicroOps()
3827 case ARM::t2LDMIA_UPD: in getNumMicroOps()
3828 case ARM::t2LDMDB_UPD: in getNumMicroOps()
3829 case ARM::t2STMIA: in getNumMicroOps()
3830 case ARM::t2STMDB: in getNumMicroOps()
3831 case ARM::t2STMIA_UPD: in getNumMicroOps()
3832 case ARM::t2STMDB_UPD: { in getNumMicroOps()
3887 case ARM::VLDMSIA: in getVLDMDefCycle()
3888 case ARM::VLDMSIA_UPD: in getVLDMDefCycle()
3889 case ARM::VLDMSDB_UPD: in getVLDMDefCycle()
3962 case ARM::VSTMSIA: in getVSTMUseCycle()
3963 case ARM::VSTMSIA_UPD: in getVSTMUseCycle()
3964 case ARM::VSTMSDB_UPD: in getVSTMUseCycle()
4032 case ARM::VLDMDIA: in getOperandLatency()
4033 case ARM::VLDMDIA_UPD: in getOperandLatency()
4034 case ARM::VLDMDDB_UPD: in getOperandLatency()
4035 case ARM::VLDMSIA: in getOperandLatency()
4036 case ARM::VLDMSIA_UPD: in getOperandLatency()
4037 case ARM::VLDMSDB_UPD: in getOperandLatency()
4041 case ARM::LDMIA_RET: in getOperandLatency()
4042 case ARM::LDMIA: in getOperandLatency()
4043 case ARM::LDMDA: in getOperandLatency()
4044 case ARM::LDMDB: in getOperandLatency()
4045 case ARM::LDMIB: in getOperandLatency()
4046 case ARM::LDMIA_UPD: in getOperandLatency()
4047 case ARM::LDMDA_UPD: in getOperandLatency()
4048 case ARM::LDMDB_UPD: in getOperandLatency()
4049 case ARM::LDMIB_UPD: in getOperandLatency()
4050 case ARM::tLDMIA: in getOperandLatency()
4051 case ARM::tLDMIA_UPD: in getOperandLatency()
4052 case ARM::tPUSH: in getOperandLatency()
4053 case ARM::t2LDMIA_RET: in getOperandLatency()
4054 case ARM::t2LDMIA: in getOperandLatency()
4055 case ARM::t2LDMDB: in getOperandLatency()
4056 case ARM::t2LDMIA_UPD: in getOperandLatency()
4057 case ARM::t2LDMDB_UPD: in getOperandLatency()
4073 case ARM::VSTMDIA: in getOperandLatency()
4074 case ARM::VSTMDIA_UPD: in getOperandLatency()
4075 case ARM::VSTMDDB_UPD: in getOperandLatency()
4076 case ARM::VSTMSIA: in getOperandLatency()
4077 case ARM::VSTMSIA_UPD: in getOperandLatency()
4078 case ARM::VSTMSDB_UPD: in getOperandLatency()
4082 case ARM::STMIA: in getOperandLatency()
4083 case ARM::STMDA: in getOperandLatency()
4084 case ARM::STMDB: in getOperandLatency()
4085 case ARM::STMIB: in getOperandLatency()
4086 case ARM::STMIA_UPD: in getOperandLatency()
4087 case ARM::STMDA_UPD: in getOperandLatency()
4088 case ARM::STMDB_UPD: in getOperandLatency()
4089 case ARM::STMIB_UPD: in getOperandLatency()
4090 case ARM::tSTMIA_UPD: in getOperandLatency()
4091 case ARM::tPOP_RET: in getOperandLatency()
4092 case ARM::tPOP: in getOperandLatency()
4093 case ARM::t2STMIA: in getOperandLatency()
4094 case ARM::t2STMDB: in getOperandLatency()
4095 case ARM::t2STMIA_UPD: in getOperandLatency()
4096 case ARM::t2STMDB_UPD: in getOperandLatency()
4160 if (II->getOpcode() != ARM::t2IT) in getBundledUseMI()
4186 case ARM::LDRrs: in adjustDefLatency()
4187 case ARM::LDRBrs: { in adjustDefLatency()
4195 case ARM::t2LDRs: in adjustDefLatency()
4196 case ARM::t2LDRBs: in adjustDefLatency()
4197 case ARM::t2LDRHs: in adjustDefLatency()
4198 case ARM::t2LDRSHs: { in adjustDefLatency()
4211 case ARM::LDRrs: in adjustDefLatency()
4212 case ARM::LDRBrs: { in adjustDefLatency()
4226 case ARM::t2LDRs: in adjustDefLatency()
4227 case ARM::t2LDRBs: in adjustDefLatency()
4228 case ARM::t2LDRHs: in adjustDefLatency()
4229 case ARM::t2LDRSHs: { in adjustDefLatency()
4242 case ARM::VLD1q8: in adjustDefLatency()
4243 case ARM::VLD1q16: in adjustDefLatency()
4244 case ARM::VLD1q32: in adjustDefLatency()
4245 case ARM::VLD1q64: in adjustDefLatency()
4246 case ARM::VLD1q8wb_fixed: in adjustDefLatency()
4247 case ARM::VLD1q16wb_fixed: in adjustDefLatency()
4248 case ARM::VLD1q32wb_fixed: in adjustDefLatency()
4249 case ARM::VLD1q64wb_fixed: in adjustDefLatency()
4250 case ARM::VLD1q8wb_register: in adjustDefLatency()
4251 case ARM::VLD1q16wb_register: in adjustDefLatency()
4252 case ARM::VLD1q32wb_register: in adjustDefLatency()
4253 case ARM::VLD1q64wb_register: in adjustDefLatency()
4254 case ARM::VLD2d8: in adjustDefLatency()
4255 case ARM::VLD2d16: in adjustDefLatency()
4256 case ARM::VLD2d32: in adjustDefLatency()
4257 case ARM::VLD2q8: in adjustDefLatency()
4258 case ARM::VLD2q16: in adjustDefLatency()
4259 case ARM::VLD2q32: in adjustDefLatency()
4260 case ARM::VLD2d8wb_fixed: in adjustDefLatency()
4261 case ARM::VLD2d16wb_fixed: in adjustDefLatency()
4262 case ARM::VLD2d32wb_fixed: in adjustDefLatency()
4263 case ARM::VLD2q8wb_fixed: in adjustDefLatency()
4264 case ARM::VLD2q16wb_fixed: in adjustDefLatency()
4265 case ARM::VLD2q32wb_fixed: in adjustDefLatency()
4266 case ARM::VLD2d8wb_register: in adjustDefLatency()
4267 case ARM::VLD2d16wb_register: in adjustDefLatency()
4268 case ARM::VLD2d32wb_register: in adjustDefLatency()
4269 case ARM::VLD2q8wb_register: in adjustDefLatency()
4270 case ARM::VLD2q16wb_register: in adjustDefLatency()
4271 case ARM::VLD2q32wb_register: in adjustDefLatency()
4272 case ARM::VLD3d8: in adjustDefLatency()
4273 case ARM::VLD3d16: in adjustDefLatency()
4274 case ARM::VLD3d32: in adjustDefLatency()
4275 case ARM::VLD1d64T: in adjustDefLatency()
4276 case ARM::VLD3d8_UPD: in adjustDefLatency()
4277 case ARM::VLD3d16_UPD: in adjustDefLatency()
4278 case ARM::VLD3d32_UPD: in adjustDefLatency()
4279 case ARM::VLD1d64Twb_fixed: in adjustDefLatency()
4280 case ARM::VLD1d64Twb_register: in adjustDefLatency()
4281 case ARM::VLD3q8_UPD: in adjustDefLatency()
4282 case ARM::VLD3q16_UPD: in adjustDefLatency()
4283 case ARM::VLD3q32_UPD: in adjustDefLatency()
4284 case ARM::VLD4d8: in adjustDefLatency()
4285 case ARM::VLD4d16: in adjustDefLatency()
4286 case ARM::VLD4d32: in adjustDefLatency()
4287 case ARM::VLD1d64Q: in adjustDefLatency()
4288 case ARM::VLD4d8_UPD: in adjustDefLatency()
4289 case ARM::VLD4d16_UPD: in adjustDefLatency()
4290 case ARM::VLD4d32_UPD: in adjustDefLatency()
4291 case ARM::VLD1d64Qwb_fixed: in adjustDefLatency()
4292 case ARM::VLD1d64Qwb_register: in adjustDefLatency()
4293 case ARM::VLD4q8_UPD: in adjustDefLatency()
4294 case ARM::VLD4q16_UPD: in adjustDefLatency()
4295 case ARM::VLD4q32_UPD: in adjustDefLatency()
4296 case ARM::VLD1DUPq8: in adjustDefLatency()
4297 case ARM::VLD1DUPq16: in adjustDefLatency()
4298 case ARM::VLD1DUPq32: in adjustDefLatency()
4299 case ARM::VLD1DUPq8wb_fixed: in adjustDefLatency()
4300 case ARM::VLD1DUPq16wb_fixed: in adjustDefLatency()
4301 case ARM::VLD1DUPq32wb_fixed: in adjustDefLatency()
4302 case ARM::VLD1DUPq8wb_register: in adjustDefLatency()
4303 case ARM::VLD1DUPq16wb_register: in adjustDefLatency()
4304 case ARM::VLD1DUPq32wb_register: in adjustDefLatency()
4305 case ARM::VLD2DUPd8: in adjustDefLatency()
4306 case ARM::VLD2DUPd16: in adjustDefLatency()
4307 case ARM::VLD2DUPd32: in adjustDefLatency()
4308 case ARM::VLD2DUPd8wb_fixed: in adjustDefLatency()
4309 case ARM::VLD2DUPd16wb_fixed: in adjustDefLatency()
4310 case ARM::VLD2DUPd32wb_fixed: in adjustDefLatency()
4311 case ARM::VLD2DUPd8wb_register: in adjustDefLatency()
4312 case ARM::VLD2DUPd16wb_register: in adjustDefLatency()
4313 case ARM::VLD2DUPd32wb_register: in adjustDefLatency()
4314 case ARM::VLD4DUPd8: in adjustDefLatency()
4315 case ARM::VLD4DUPd16: in adjustDefLatency()
4316 case ARM::VLD4DUPd32: in adjustDefLatency()
4317 case ARM::VLD4DUPd8_UPD: in adjustDefLatency()
4318 case ARM::VLD4DUPd16_UPD: in adjustDefLatency()
4319 case ARM::VLD4DUPd32_UPD: in adjustDefLatency()
4320 case ARM::VLD1LNd8: in adjustDefLatency()
4321 case ARM::VLD1LNd16: in adjustDefLatency()
4322 case ARM::VLD1LNd32: in adjustDefLatency()
4323 case ARM::VLD1LNd8_UPD: in adjustDefLatency()
4324 case ARM::VLD1LNd16_UPD: in adjustDefLatency()
4325 case ARM::VLD1LNd32_UPD: in adjustDefLatency()
4326 case ARM::VLD2LNd8: in adjustDefLatency()
4327 case ARM::VLD2LNd16: in adjustDefLatency()
4328 case ARM::VLD2LNd32: in adjustDefLatency()
4329 case ARM::VLD2LNq16: in adjustDefLatency()
4330 case ARM::VLD2LNq32: in adjustDefLatency()
4331 case ARM::VLD2LNd8_UPD: in adjustDefLatency()
4332 case ARM::VLD2LNd16_UPD: in adjustDefLatency()
4333 case ARM::VLD2LNd32_UPD: in adjustDefLatency()
4334 case ARM::VLD2LNq16_UPD: in adjustDefLatency()
4335 case ARM::VLD2LNq32_UPD: in adjustDefLatency()
4336 case ARM::VLD4LNd8: in adjustDefLatency()
4337 case ARM::VLD4LNd16: in adjustDefLatency()
4338 case ARM::VLD4LNd32: in adjustDefLatency()
4339 case ARM::VLD4LNq16: in adjustDefLatency()
4340 case ARM::VLD4LNq32: in adjustDefLatency()
4341 case ARM::VLD4LNd8_UPD: in adjustDefLatency()
4342 case ARM::VLD4LNd16_UPD: in adjustDefLatency()
4343 case ARM::VLD4LNd32_UPD: in adjustDefLatency()
4344 case ARM::VLD4LNq16_UPD: in adjustDefLatency()
4345 case ARM::VLD4LNq32_UPD: in adjustDefLatency()
4396 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
4397 if (DefMI.getOpcode() == ARM::FMSTAT) { in getOperandLatencyImpl()
4492 case ARM::LDRrs: in getOperandLatency()
4493 case ARM::LDRBrs: { in getOperandLatency()
4502 case ARM::t2LDRs: in getOperandLatency()
4503 case ARM::t2LDRBs: in getOperandLatency()
4504 case ARM::t2LDRHs: in getOperandLatency()
4505 case ARM::t2LDRSHs: { in getOperandLatency()
4519 case ARM::LDRrs: in getOperandLatency()
4520 case ARM::LDRBrs: { in getOperandLatency()
4532 case ARM::t2LDRs: in getOperandLatency()
4533 case ARM::t2LDRBs: in getOperandLatency()
4534 case ARM::t2LDRHs: in getOperandLatency()
4535 case ARM::t2LDRSHs: in getOperandLatency()
4545 case ARM::VLD1q8: in getOperandLatency()
4546 case ARM::VLD1q16: in getOperandLatency()
4547 case ARM::VLD1q32: in getOperandLatency()
4548 case ARM::VLD1q64: in getOperandLatency()
4549 case ARM::VLD1q8wb_register: in getOperandLatency()
4550 case ARM::VLD1q16wb_register: in getOperandLatency()
4551 case ARM::VLD1q32wb_register: in getOperandLatency()
4552 case ARM::VLD1q64wb_register: in getOperandLatency()
4553 case ARM::VLD1q8wb_fixed: in getOperandLatency()
4554 case ARM::VLD1q16wb_fixed: in getOperandLatency()
4555 case ARM::VLD1q32wb_fixed: in getOperandLatency()
4556 case ARM::VLD1q64wb_fixed: in getOperandLatency()
4557 case ARM::VLD2d8: in getOperandLatency()
4558 case ARM::VLD2d16: in getOperandLatency()
4559 case ARM::VLD2d32: in getOperandLatency()
4560 case ARM::VLD2q8Pseudo: in getOperandLatency()
4561 case ARM::VLD2q16Pseudo: in getOperandLatency()
4562 case ARM::VLD2q32Pseudo: in getOperandLatency()
4563 case ARM::VLD2d8wb_fixed: in getOperandLatency()
4564 case ARM::VLD2d16wb_fixed: in getOperandLatency()
4565 case ARM::VLD2d32wb_fixed: in getOperandLatency()
4566 case ARM::VLD2q8PseudoWB_fixed: in getOperandLatency()
4567 case ARM::VLD2q16PseudoWB_fixed: in getOperandLatency()
4568 case ARM::VLD2q32PseudoWB_fixed: in getOperandLatency()
4569 case ARM::VLD2d8wb_register: in getOperandLatency()
4570 case ARM::VLD2d16wb_register: in getOperandLatency()
4571 case ARM::VLD2d32wb_register: in getOperandLatency()
4572 case ARM::VLD2q8PseudoWB_register: in getOperandLatency()
4573 case ARM::VLD2q16PseudoWB_register: in getOperandLatency()
4574 case ARM::VLD2q32PseudoWB_register: in getOperandLatency()
4575 case ARM::VLD3d8Pseudo: in getOperandLatency()
4576 case ARM::VLD3d16Pseudo: in getOperandLatency()
4577 case ARM::VLD3d32Pseudo: in getOperandLatency()
4578 case ARM::VLD1d8TPseudo: in getOperandLatency()
4579 case ARM::VLD1d16TPseudo: in getOperandLatency()
4580 case ARM::VLD1d32TPseudo: in getOperandLatency()
4581 case ARM::VLD1d64TPseudo: in getOperandLatency()
4582 case ARM::VLD1d64TPseudoWB_fixed: in getOperandLatency()
4583 case ARM::VLD1d64TPseudoWB_register: in getOperandLatency()
4584 case ARM::VLD3d8Pseudo_UPD: in getOperandLatency()
4585 case ARM::VLD3d16Pseudo_UPD: in getOperandLatency()
4586 case ARM::VLD3d32Pseudo_UPD: in getOperandLatency()
4587 case ARM::VLD3q8Pseudo_UPD: in getOperandLatency()
4588 case ARM::VLD3q16Pseudo_UPD: in getOperandLatency()
4589 case ARM::VLD3q32Pseudo_UPD: in getOperandLatency()
4590 case ARM::VLD3q8oddPseudo: in getOperandLatency()
4591 case ARM::VLD3q16oddPseudo: in getOperandLatency()
4592 case ARM::VLD3q32oddPseudo: in getOperandLatency()
4593 case ARM::VLD3q8oddPseudo_UPD: in getOperandLatency()
4594 case ARM::VLD3q16oddPseudo_UPD: in getOperandLatency()
4595 case ARM::VLD3q32oddPseudo_UPD: in getOperandLatency()
4596 case ARM::VLD4d8Pseudo: in getOperandLatency()
4597 case ARM::VLD4d16Pseudo: in getOperandLatency()
4598 case ARM::VLD4d32Pseudo: in getOperandLatency()
4599 case ARM::VLD1d8QPseudo: in getOperandLatency()
4600 case ARM::VLD1d16QPseudo: in getOperandLatency()
4601 case ARM::VLD1d32QPseudo: in getOperandLatency()
4602 case ARM::VLD1d64QPseudo: in getOperandLatency()
4603 case ARM::VLD1d64QPseudoWB_fixed: in getOperandLatency()
4604 case ARM::VLD1d64QPseudoWB_register: in getOperandLatency()
4605 case ARM::VLD1q8HighQPseudo: in getOperandLatency()
4606 case ARM::VLD1q8LowQPseudo_UPD: in getOperandLatency()
4607 case ARM::VLD1q8HighTPseudo: in getOperandLatency()
4608 case ARM::VLD1q8LowTPseudo_UPD: in getOperandLatency()
4609 case ARM::VLD1q16HighQPseudo: in getOperandLatency()
4610 case ARM::VLD1q16LowQPseudo_UPD: in getOperandLatency()
4611 case ARM::VLD1q16HighTPseudo: in getOperandLatency()
4612 case ARM::VLD1q16LowTPseudo_UPD: in getOperandLatency()
4613 case ARM::VLD1q32HighQPseudo: in getOperandLatency()
4614 case ARM::VLD1q32LowQPseudo_UPD: in getOperandLatency()
4615 case ARM::VLD1q32HighTPseudo: in getOperandLatency()
4616 case ARM::VLD1q32LowTPseudo_UPD: in getOperandLatency()
4617 case ARM::VLD1q64HighQPseudo: in getOperandLatency()
4618 case ARM::VLD1q64LowQPseudo_UPD: in getOperandLatency()
4619 case ARM::VLD1q64HighTPseudo: in getOperandLatency()
4620 case ARM::VLD1q64LowTPseudo_UPD: in getOperandLatency()
4621 case ARM::VLD4d8Pseudo_UPD: in getOperandLatency()
4622 case ARM::VLD4d16Pseudo_UPD: in getOperandLatency()
4623 case ARM::VLD4d32Pseudo_UPD: in getOperandLatency()
4624 case ARM::VLD4q8Pseudo_UPD: in getOperandLatency()
4625 case ARM::VLD4q16Pseudo_UPD: in getOperandLatency()
4626 case ARM::VLD4q32Pseudo_UPD: in getOperandLatency()
4627 case ARM::VLD4q8oddPseudo: in getOperandLatency()
4628 case ARM::VLD4q16oddPseudo: in getOperandLatency()
4629 case ARM::VLD4q32oddPseudo: in getOperandLatency()
4630 case ARM::VLD4q8oddPseudo_UPD: in getOperandLatency()
4631 case ARM::VLD4q16oddPseudo_UPD: in getOperandLatency()
4632 case ARM::VLD4q32oddPseudo_UPD: in getOperandLatency()
4633 case ARM::VLD1DUPq8: in getOperandLatency()
4634 case ARM::VLD1DUPq16: in getOperandLatency()
4635 case ARM::VLD1DUPq32: in getOperandLatency()
4636 case ARM::VLD1DUPq8wb_fixed: in getOperandLatency()
4637 case ARM::VLD1DUPq16wb_fixed: in getOperandLatency()
4638 case ARM::VLD1DUPq32wb_fixed: in getOperandLatency()
4639 case ARM::VLD1DUPq8wb_register: in getOperandLatency()
4640 case ARM::VLD1DUPq16wb_register: in getOperandLatency()
4641 case ARM::VLD1DUPq32wb_register: in getOperandLatency()
4642 case ARM::VLD2DUPd8: in getOperandLatency()
4643 case ARM::VLD2DUPd16: in getOperandLatency()
4644 case ARM::VLD2DUPd32: in getOperandLatency()
4645 case ARM::VLD2DUPd8wb_fixed: in getOperandLatency()
4646 case ARM::VLD2DUPd16wb_fixed: in getOperandLatency()
4647 case ARM::VLD2DUPd32wb_fixed: in getOperandLatency()
4648 case ARM::VLD2DUPd8wb_register: in getOperandLatency()
4649 case ARM::VLD2DUPd16wb_register: in getOperandLatency()
4650 case ARM::VLD2DUPd32wb_register: in getOperandLatency()
4651 case ARM::VLD2DUPq8EvenPseudo: in getOperandLatency()
4652 case ARM::VLD2DUPq8OddPseudo: in getOperandLatency()
4653 case ARM::VLD2DUPq16EvenPseudo: in getOperandLatency()
4654 case ARM::VLD2DUPq16OddPseudo: in getOperandLatency()
4655 case ARM::VLD2DUPq32EvenPseudo: in getOperandLatency()
4656 case ARM::VLD2DUPq32OddPseudo: in getOperandLatency()
4657 case ARM::VLD3DUPq8EvenPseudo: in getOperandLatency()
4658 case ARM::VLD3DUPq8OddPseudo: in getOperandLatency()
4659 case ARM::VLD3DUPq16EvenPseudo: in getOperandLatency()
4660 case ARM::VLD3DUPq16OddPseudo: in getOperandLatency()
4661 case ARM::VLD3DUPq32EvenPseudo: in getOperandLatency()
4662 case ARM::VLD3DUPq32OddPseudo: in getOperandLatency()
4663 case ARM::VLD4DUPd8Pseudo: in getOperandLatency()
4664 case ARM::VLD4DUPd16Pseudo: in getOperandLatency()
4665 case ARM::VLD4DUPd32Pseudo: in getOperandLatency()
4666 case ARM::VLD4DUPd8Pseudo_UPD: in getOperandLatency()
4667 case ARM::VLD4DUPd16Pseudo_UPD: in getOperandLatency()
4668 case ARM::VLD4DUPd32Pseudo_UPD: in getOperandLatency()
4669 case ARM::VLD4DUPq8EvenPseudo: in getOperandLatency()
4670 case ARM::VLD4DUPq8OddPseudo: in getOperandLatency()
4671 case ARM::VLD4DUPq16EvenPseudo: in getOperandLatency()
4672 case ARM::VLD4DUPq16OddPseudo: in getOperandLatency()
4673 case ARM::VLD4DUPq32EvenPseudo: in getOperandLatency()
4674 case ARM::VLD4DUPq32OddPseudo: in getOperandLatency()
4675 case ARM::VLD1LNq8Pseudo: in getOperandLatency()
4676 case ARM::VLD1LNq16Pseudo: in getOperandLatency()
4677 case ARM::VLD1LNq32Pseudo: in getOperandLatency()
4678 case ARM::VLD1LNq8Pseudo_UPD: in getOperandLatency()
4679 case ARM::VLD1LNq16Pseudo_UPD: in getOperandLatency()
4680 case ARM::VLD1LNq32Pseudo_UPD: in getOperandLatency()
4681 case ARM::VLD2LNd8Pseudo: in getOperandLatency()
4682 case ARM::VLD2LNd16Pseudo: in getOperandLatency()
4683 case ARM::VLD2LNd32Pseudo: in getOperandLatency()
4684 case ARM::VLD2LNq16Pseudo: in getOperandLatency()
4685 case ARM::VLD2LNq32Pseudo: in getOperandLatency()
4686 case ARM::VLD2LNd8Pseudo_UPD: in getOperandLatency()
4687 case ARM::VLD2LNd16Pseudo_UPD: in getOperandLatency()
4688 case ARM::VLD2LNd32Pseudo_UPD: in getOperandLatency()
4689 case ARM::VLD2LNq16Pseudo_UPD: in getOperandLatency()
4690 case ARM::VLD2LNq32Pseudo_UPD: in getOperandLatency()
4691 case ARM::VLD4LNd8Pseudo: in getOperandLatency()
4692 case ARM::VLD4LNd16Pseudo: in getOperandLatency()
4693 case ARM::VLD4LNd32Pseudo: in getOperandLatency()
4694 case ARM::VLD4LNq16Pseudo: in getOperandLatency()
4695 case ARM::VLD4LNq32Pseudo: in getOperandLatency()
4696 case ARM::VLD4LNd8Pseudo_UPD: in getOperandLatency()
4697 case ARM::VLD4LNd16Pseudo_UPD: in getOperandLatency()
4698 case ARM::VLD4LNd32Pseudo_UPD: in getOperandLatency()
4699 case ARM::VLD4LNq16Pseudo_UPD: in getOperandLatency()
4700 case ARM::VLD4LNq32Pseudo_UPD: in getOperandLatency()
4720 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getPredicationCost()
4743 if (I->getOpcode() != ARM::t2IT) in getInstrLatency()
4750 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getInstrLatency()
4792 case ARM::VLDMQIA: in getInstrLatency()
4793 case ARM::VSTMQIA: in getInstrLatency()
4841 if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) { in verifyInstruction()
4843 if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) && in verifyInstruction()
4844 !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) { in verifyInstruction()
4849 if (MI.getOpcode() == ARM::tPUSH || in verifyInstruction()
4850 MI.getOpcode() == ARM::tPOP || in verifyInstruction()
4851 MI.getOpcode() == ARM::tPOP_RET) { in verifyInstruction()
4856 if (Reg < ARM::R0 || Reg > ARM::R7) { in verifyInstruction()
4857 if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) && in verifyInstruction()
4858 !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) { in verifyInstruction()
4865 if (MI.getOpcode() == ARM::MVE_VMOV_q_rr) { in verifyInstruction()
4918 if (LoadImmOpc == ARM::MRC || LoadImmOpc == ARM::t2MRC) { in expandLoadStackGuardBase()
4936 unsigned AddOpc = (LoadImmOpc == ARM::MRC) ? ARM::ADDri : ARM::t2ADDri; in expandLoadStackGuardBase()
5026 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
5032 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR || in getExecutionDomain()
5033 MI.getOpcode() == ARM::VMOVS)) in getExecutionDomain()
5055 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5058 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
5062 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5095 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
5120 case ARM::VMOVD: in setExecutionDomain()
5138 MI.setDesc(get(ARM::VORRd)); in setExecutionDomain()
5144 case ARM::VMOVRS: in setExecutionDomain()
5161 MI.setDesc(get(ARM::VGETLNi32)); in setExecutionDomain()
5171 case ARM::VMOVSR: { in setExecutionDomain()
5191 MI.setDesc(get(ARM::VSETLNi32)); in setExecutionDomain()
5205 case ARM::VMOVS: { in setExecutionDomain()
5227 MI.setDesc(get(ARM::VDUPLN32d)); in setExecutionDomain()
5255 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32), in setExecutionDomain()
5274 MI.setDesc(get(ARM::VEXTd32)); in setExecutionDomain()
5335 case ARM::VLDRS: in getPartialRegUpdateClearance()
5336 case ARM::FCONSTS: in getPartialRegUpdateClearance()
5337 case ARM::VMOVSR: in getPartialRegUpdateClearance()
5338 case ARM::VMOVv8i8: in getPartialRegUpdateClearance()
5339 case ARM::VMOVv4i16: in getPartialRegUpdateClearance()
5340 case ARM::VMOVv2i32: in getPartialRegUpdateClearance()
5341 case ARM::VMOVv2f32: in getPartialRegUpdateClearance()
5342 case ARM::VMOVv1i64: in getPartialRegUpdateClearance()
5347 case ARM::VLD1LNd32: in getPartialRegUpdateClearance()
5364 } else if (ARM::SPRRegClass.contains(Reg)) { in getPartialRegUpdateClearance()
5366 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
5367 &ARM::DPRRegClass); in getPartialRegUpdateClearance()
5391 if (ARM::SPRRegClass.contains(Reg)) { in breakPartialRegDependency()
5392 DReg = ARM::D0 + (Reg - ARM::S0) / 2; in breakPartialRegDependency()
5396 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); in breakPartialRegDependency()
5407 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg) in breakPartialRegDependency()
5414 return Subtarget.getFeatureBits()[ARM::HasV6KOps]; in hasNOP()
5438 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
5447 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5452 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
5465 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
5475 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
5488 case ARM::VSETLNi32: in getInsertSubregLikeInputs()
5489 case ARM::MVE_VMOV_to_lane_32: in getInsertSubregLikeInputs()
5502 InsertedReg.SubIdx = ARM::ssub_0 + MOIndex.getImm(); in getInsertSubregLikeInputs()
5550 if (Opcode == ARM::SUBri) in isAddImmediate()
5552 else if (Opcode != ARM::ADDri) in isAddImmediate()
5583 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5585 if (CmpMI->readsRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5591 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri) in findCMPToFoldIntoCBZ()
5808 for (Register Reg : ARM::rGPRRegClass) { in findRegisterToSaveLRTo()
5810 Reg != ARM::LR && // LR is not reserved, but don't use it. in findRegisterToSaveLRTo()
5811 Reg != ARM::R12 && // R12 is not guaranteed to be preserved. in findRegisterToSaveLRTo()
5831 if (MI.modifiesRegister(ARM::LR, &TRI)) in isLRAvailable()
5836 if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR || in isLRAvailable()
5837 Opcode == ARM::SUBS_PC_LR || Opcode == ARM::tBX_RET || in isLRAvailable()
5838 Opcode == ARM::tBXNS_RET) { in isLRAvailable()
5844 if (MI.readsRegister(ARM::LR, &TRI)) in isLRAvailable()
5884 return C.isAnyUnavailableAcrossOrOutOfSeq({ARM::R12, ARM::CPSR}, TRI); in getOutliningCandidateInfo()
5981 } else if (LastInstrOpcode == ARM::BL || LastInstrOpcode == ARM::BLX || in getOutliningCandidateInfo()
5982 LastInstrOpcode == ARM::BLX_noip || LastInstrOpcode == ARM::tBL || in getOutliningCandidateInfo()
5983 LastInstrOpcode == ARM::tBLXr || in getOutliningCandidateInfo()
5984 LastInstrOpcode == ARM::tBLXr_noip || in getOutliningCandidateInfo()
5985 LastInstrOpcode == ARM::tBLXi) { in getOutliningCandidateInfo()
6004 : C.isAvailableAcrossAndOutOfSeq(ARM::LR, TRI); in getOutliningCandidateInfo()
6023 else if (C.isAvailableInsideSeq(ARM::SP, TRI)) { in getOutliningCandidateInfo()
6072 int SPIdx = MI->findRegisterUseOperandIdx(ARM::SP); in checkAndUpdateStackOffset()
6220 bool R12AvailableInBlock = LRU.available(ARM::R12); in isMBBSafeToOutlineFrom()
6221 bool CPSRAvailableInBlock = LRU.available(ARM::CPSR); in isMBBSafeToOutlineFrom()
6233 if (R12AvailableInBlock && !LRU.available(ARM::R12)) in isMBBSafeToOutlineFrom()
6235 if (CPSRAvailableInBlock && !LRU.available(ARM::CPSR)) in isMBBSafeToOutlineFrom()
6248 : LRU.available(ARM::LR); in isMBBSafeToOutlineFrom()
6277 if (Opc == ARM::tPICADD || Opc == ARM::PICADD || Opc == ARM::PICSTR || in getOutliningType()
6278 Opc == ARM::PICSTRB || Opc == ARM::PICSTRH || Opc == ARM::PICLDR || in getOutliningType()
6279 Opc == ARM::PICLDRB || Opc == ARM::PICLDRH || Opc == ARM::PICLDRSB || in getOutliningType()
6280 Opc == ARM::PICLDRSH || Opc == ARM::t2LDRpci_pic || in getOutliningType()
6281 Opc == ARM::t2MOVi16_ga_pcrel || Opc == ARM::t2MOVTi16_ga_pcrel || in getOutliningType()
6282 Opc == ARM::t2MOV_ga_pcrel) in getOutliningType()
6286 if (Opc == ARM::t2BF_LabelPseudo || Opc == ARM::t2DoLoopStart || in getOutliningType()
6287 Opc == ARM::t2DoLoopStartTP || Opc == ARM::t2WhileLoopStart || in getOutliningType()
6288 Opc == ARM::t2WhileLoopStartLR || Opc == ARM::t2WhileLoopStartTP || in getOutliningType()
6289 Opc == ARM::t2LoopDec || Opc == ARM::t2LoopEnd || in getOutliningType()
6290 Opc == ARM::t2LoopEndDec) in getOutliningType()
6320 if (MI.readsRegister(ARM::LR, TRI) || MI.readsRegister(ARM::PC, TRI)) in getOutliningType()
6346 if (Opc == ARM::BL || Opc == ARM::tBL || Opc == ARM::BLX || in getOutliningType()
6347 Opc == ARM::BLX_noip || Opc == ARM::tBLXr || Opc == ARM::tBLXr_noip || in getOutliningType()
6348 Opc == ARM::tBLXi) in getOutliningType()
6377 if (MI.modifiesRegister(ARM::LR, TRI) || MI.modifiesRegister(ARM::PC, TRI)) in getOutliningType()
6381 if (MI.modifiesRegister(ARM::SP, TRI) || MI.readsRegister(ARM::SP, TRI)) { in getOutliningType()
6404 if (MI.modifiesRegister(ARM::SP, TRI)) in getOutliningType()
6418 if (MI.readsRegister(ARM::ITSTATE, TRI) || in getOutliningType()
6419 MI.modifiesRegister(ARM::ITSTATE, TRI)) in getOutliningType()
6444 BuildMI(MBB, It, DebugLoc(), get(ARM::t2PAC)) in saveLROnStack()
6446 BuildMI(MBB, It, DebugLoc(), get(ARM::t2STRD_PRE), ARM::SP) in saveLROnStack()
6447 .addReg(ARM::R12, RegState::Kill) in saveLROnStack()
6448 .addReg(ARM::LR, RegState::Kill) in saveLROnStack()
6449 .addReg(ARM::SP) in saveLROnStack()
6454 unsigned Opc = Subtarget.isThumb() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM; in saveLROnStack()
6455 BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::SP) in saveLROnStack()
6456 .addReg(ARM::LR, RegState::Kill) in saveLROnStack()
6457 .addReg(ARM::SP) in saveLROnStack()
6471 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in saveLROnStack()
6479 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in saveLROnStack()
6482 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in saveLROnStack()
6487 unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); in saveLROnStack()
6490 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in saveLROnStack()
6501 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRSaveToReg()
6506 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRSaveToReg()
6518 BuildMI(MBB, It, DebugLoc(), get(ARM::t2LDRD_POST)) in restoreLRFromStack()
6519 .addReg(ARM::R12, RegState::Define) in restoreLRFromStack()
6520 .addReg(ARM::LR, RegState::Define) in restoreLRFromStack()
6521 .addReg(ARM::SP, RegState::Define) in restoreLRFromStack()
6522 .addReg(ARM::SP) in restoreLRFromStack()
6528 unsigned Opc = Subtarget.isThumb() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM; in restoreLRFromStack()
6529 MachineInstrBuilder MIB = BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::LR) in restoreLRFromStack()
6530 .addReg(ARM::SP, RegState::Define) in restoreLRFromStack()
6531 .addReg(ARM::SP); in restoreLRFromStack()
6543 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in restoreLRFromStack()
6546 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in restoreLRFromStack()
6553 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in restoreLRFromStack()
6558 unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); in restoreLRFromStack()
6561 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in restoreLRFromStack()
6568 BuildMI(MBB, It, DebugLoc(), get(ARM::t2AUT)); in restoreLRFromStack()
6575 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRRestoreFromReg()
6579 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRRestoreFromReg()
6594 ? isThumb ? ARM::tTAILJMPr : ARM::TAILJMPr in buildOutlinedFrame()
6595 : isThumb ? Subtarget.isTargetMachO() ? ARM::tTAILJMPd in buildOutlinedFrame()
6596 : ARM::tTAILJMPdND in buildOutlinedFrame()
6597 : ARM::TAILJMPd; in buildOutlinedFrame()
6620 if (!MBB.isLiveIn(ARM::LR)) in buildOutlinedFrame()
6621 MBB.addLiveIn(ARM::LR); in buildOutlinedFrame()
6672 ? Subtarget.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND in insertOutlinedCall()
6673 : ARM::TAILJMPd; in insertOutlinedCall()
6683 Opc = isThumb ? ARM::tBL : ARM::BL; in insertOutlinedCall()
6703 copyPhysReg(MBB, It, DebugLoc(), Reg, ARM::LR, true); in insertOutlinedCall()
6707 copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true); in insertOutlinedCall()
6714 if (!MBB.isLiveIn(ARM::LR)) in insertOutlinedCall()
6715 MBB.addLiveIn(ARM::LR); in insertOutlinedCall()
6739 return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::BLX_noip in getBLXOpcode()
6740 : ARM::BLX; in getBLXOpcode()
6744 return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::tBLXr_noip in gettBLXrOpcode()
6745 : ARM::tBLXr; in gettBLXrOpcode()
6749 return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::BLX_pred_noip in getBLXpredOpcode()
6750 : ARM::BLX_pred; in getBLXpredOpcode()
6788 } else if (EndLoop->getOpcode() == ARM::t2LoopEnd) { in createTripCountGreaterCondition()
6793 if (I.getOpcode() == ARM::t2LoopDec) in createTripCountGreaterCondition()
6797 BuildMI(&MBB, LoopDec->getDebugLoc(), TII->get(ARM::t2CMPri)) in createTripCountGreaterCondition()
6801 .addReg(ARM::NoRegister); in createTripCountGreaterCondition()
6803 Cond.push_back(MachineOperand::CreateReg(ARM::CPSR, false)); in createTripCountGreaterCondition()
6824 if (I != LoopBB->end() && I->getOpcode() == ARM::t2Bcc) { in analyzeLoopForPipelining()
6851 if (I != LoopBB->end() && I->getOpcode() == ARM::t2LoopEnd) { in analyzeLoopForPipelining()
6860 if (!LoopDec || LoopDec->getOpcode() != ARM::t2LoopDec) in analyzeLoopForPipelining()
6864 if (J.getOpcode() == ARM::t2DoLoopStart) in analyzeLoopForPipelining()