1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling, if-conversion, and other late
11 // optimizations. This pass should be run after register allocation but before
12 // the post-regalloc scheduling pass.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "ARM.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBaseRegisterInfo.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/Support/Debug.h"
28
29 using namespace llvm;
30
31 #define DEBUG_TYPE "arm-pseudo"
32
33 static cl::opt<bool>
34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
35 cl::desc("Verify machine code after expanding ARM pseudos"));
36
37 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
38
39 namespace {
40 class ARMExpandPseudo : public MachineFunctionPass {
41 public:
42 static char ID;
ARMExpandPseudo()43 ARMExpandPseudo() : MachineFunctionPass(ID) {}
44
45 const ARMBaseInstrInfo *TII;
46 const TargetRegisterInfo *TRI;
47 const ARMSubtarget *STI;
48 ARMFunctionInfo *AFI;
49
50 bool runOnMachineFunction(MachineFunction &Fn) override;
51
getRequiredProperties() const52 MachineFunctionProperties getRequiredProperties() const override {
53 return MachineFunctionProperties().set(
54 MachineFunctionProperties::Property::NoVRegs);
55 }
56
getPassName() const57 StringRef getPassName() const override {
58 return ARM_EXPAND_PSEUDO_NAME;
59 }
60
61 private:
62 void TransferImpOps(MachineInstr &OldMI,
63 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
64 bool ExpandMI(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MBBI,
66 MachineBasicBlock::iterator &NextMBBI);
67 bool ExpandMBB(MachineBasicBlock &MBB);
68 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
69 void ExpandVST(MachineBasicBlock::iterator &MBBI);
70 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
71 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
72 unsigned Opc, bool IsExt);
73 void ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI);
74 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator &MBBI);
76 void CMSEClearGPRegs(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
78 const SmallVectorImpl<unsigned> &ClearRegs,
79 unsigned ClobberReg);
80 MachineBasicBlock &CMSEClearFPRegs(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MBBI);
82 MachineBasicBlock &CMSEClearFPRegsV8(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MBBI,
84 const BitVector &ClearRegs);
85 MachineBasicBlock &CMSEClearFPRegsV81(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI,
87 const BitVector &ClearRegs);
88 void CMSESaveClearFPRegs(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
90 const LivePhysRegs &LiveRegs,
91 SmallVectorImpl<unsigned> &AvailableRegs);
92 void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
94 const LivePhysRegs &LiveRegs,
95 SmallVectorImpl<unsigned> &ScratchRegs);
96 void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
98 const LivePhysRegs &LiveRegs);
99 void CMSERestoreFPRegs(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
101 SmallVectorImpl<unsigned> &AvailableRegs);
102 void CMSERestoreFPRegsV8(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
104 SmallVectorImpl<unsigned> &AvailableRegs);
105 void CMSERestoreFPRegsV81(MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
107 SmallVectorImpl<unsigned> &AvailableRegs);
108 bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
110 unsigned StrexOp, unsigned UxtOp,
111 MachineBasicBlock::iterator &NextMBBI);
112
113 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator MBBI,
115 MachineBasicBlock::iterator &NextMBBI);
116 };
117 char ARMExpandPseudo::ID = 0;
118 }
119
INITIALIZE_PASS(ARMExpandPseudo,DEBUG_TYPE,ARM_EXPAND_PSEUDO_NAME,false,false)120 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false,
121 false)
122
123 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
124 /// the instructions created from the expansion.
125 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
126 MachineInstrBuilder &UseMI,
127 MachineInstrBuilder &DefMI) {
128 const MCInstrDesc &Desc = OldMI.getDesc();
129 for (const MachineOperand &MO :
130 llvm::drop_begin(OldMI.operands(), Desc.getNumOperands())) {
131 assert(MO.isReg() && MO.getReg());
132 if (MO.isUse())
133 UseMI.add(MO);
134 else
135 DefMI.add(MO);
136 }
137 }
138
139 namespace {
140 // Constants for register spacing in NEON load/store instructions.
141 // For quad-register load-lane and store-lane pseudo instructors, the
142 // spacing is initially assumed to be EvenDblSpc, and that is changed to
143 // OddDblSpc depending on the lane number operand.
144 enum NEONRegSpacing {
145 SingleSpc,
146 SingleLowSpc , // Single spacing, low registers, three and four vectors.
147 SingleHighQSpc, // Single spacing, high registers, four vectors.
148 SingleHighTSpc, // Single spacing, high registers, three vectors.
149 EvenDblSpc,
150 OddDblSpc
151 };
152
153 // Entries for NEON load/store information table. The table is sorted by
154 // PseudoOpc for fast binary-search lookups.
155 struct NEONLdStTableEntry {
156 uint16_t PseudoOpc;
157 uint16_t RealOpc;
158 bool IsLoad;
159 bool isUpdating;
160 bool hasWritebackOperand;
161 uint8_t RegSpacing; // One of type NEONRegSpacing
162 uint8_t NumRegs; // D registers loaded or stored
163 uint8_t RegElts; // elements per D register; used for lane ops
164 // FIXME: Temporary flag to denote whether the real instruction takes
165 // a single register (like the encoding) or all of the registers in
166 // the list (like the asm syntax and the isel DAG). When all definitions
167 // are converted to take only the single encoded register, this will
168 // go away.
169 bool copyAllListRegs;
170
171 // Comparison methods for binary search of the table.
operator <__anonc17b80660211::NEONLdStTableEntry172 bool operator<(const NEONLdStTableEntry &TE) const {
173 return PseudoOpc < TE.PseudoOpc;
174 }
operator <(const NEONLdStTableEntry & TE,unsigned PseudoOpc)175 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
176 return TE.PseudoOpc < PseudoOpc;
177 }
operator <(unsigned PseudoOpc,const NEONLdStTableEntry & TE)178 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
179 const NEONLdStTableEntry &TE) {
180 return PseudoOpc < TE.PseudoOpc;
181 }
182 };
183 }
184
185 static const NEONLdStTableEntry NEONLdStTable[] = {
186 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
188 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
190 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
191 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
192
193 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
194 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
195 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,false},
196 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
197 { ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed, true, true, false, SingleSpc, 3, 4 ,false},
198 { ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register, true, true, true, SingleSpc, 3, 4 ,false},
199
200 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
201 { ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
202 { ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register, true, true, true, SingleSpc, 4, 2 ,false},
203 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
204 { ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed, true, true, false, SingleSpc, 3, 2 ,false},
205 { ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register, true, true, true, SingleSpc, 3, 2 ,false},
206
207 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
208 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
209 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false},
210 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
211 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
212 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false},
213
214 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
215 { ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
216 { ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register, true, true, true, SingleSpc, 4, 8 ,false},
217 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
218 { ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed, true, true, false, SingleSpc, 3, 8 ,false},
219 { ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register, true, true, true, SingleSpc, 3, 8 ,false},
220
221 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
222 { ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleHighQSpc, 4, 4 ,false},
223 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
224 { ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleHighTSpc, 3, 4 ,false},
225 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false},
226 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false},
227
228 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
229 { ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleHighQSpc, 4, 2 ,false},
230 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
231 { ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleHighTSpc, 3, 2 ,false},
232 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false},
233 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false},
234
235 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
236 { ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleHighQSpc, 4, 1 ,false},
237 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
238 { ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleHighTSpc, 3, 1 ,false},
239 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false},
240 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false},
241
242 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
243 { ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleHighQSpc, 4, 8 ,false},
244 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
245 { ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleHighTSpc, 3, 8 ,false},
246 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false},
247 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false},
248
249 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
250 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
251 { ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed, true, true, false, OddDblSpc, 2, 4 ,false},
252 { ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register, true, true, true, OddDblSpc, 2, 4 ,false},
253 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
254 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
255 { ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed, true, true, false, OddDblSpc, 2, 2 ,false},
256 { ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register, true, true, true, OddDblSpc, 2, 2 ,false},
257 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
258 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
259 { ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed, true, true, false, OddDblSpc, 2, 8 ,false},
260 { ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register, true, true, true, OddDblSpc, 2, 8 ,false},
261
262 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
263 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
264 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
265 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
266 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
267 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
268 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
269 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
270 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
271 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
272
273 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
274 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
275 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
276 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
277 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
278 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
279 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
280 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
281 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
282
283 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
284 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
285 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
286 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
287 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
288 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
289 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
290 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
291 { ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
292 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
293 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
294 { ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
295 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
296 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
297 { ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
298
299 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
300 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
301 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
302 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
303 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
304 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
305 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
306 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
307 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
308 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
309
310 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
311 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
312 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
313 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
314 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
315 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
316
317 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
318 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
319 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
320 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
321 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
322 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
323 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
324 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
325 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
326
327 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
328 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
329 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
330 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
331 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
332 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
333 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
334 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
335 { ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
336 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
337 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
338 { ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
339 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
340 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
341 { ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
342
343 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
344 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
345 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
346 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
347 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
348 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
349 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
350 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
351 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
352 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
353
354 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
355 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
356 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
357 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
358 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
359 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
360
361 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
362 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
363 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
364 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
365 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
366 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
367 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
368 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
369 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
370
371 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
372 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
373 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
374 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
375 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
376 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
377
378 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
379 { ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
380 { ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register, false, true, true, SingleSpc, 4, 4 ,false},
381 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
382 { ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed, false, true, false, SingleSpc, 3, 4 ,false},
383 { ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register, false, true, true, SingleSpc, 3, 4 ,false},
384
385 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
386 { ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
387 { ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register, false, true, true, SingleSpc, 4, 2 ,false},
388 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
389 { ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed, false, true, false, SingleSpc, 3, 2 ,false},
390 { ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register, false, true, true, SingleSpc, 3, 2 ,false},
391
392 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
393 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
394 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
395 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
396 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
397 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
398
399 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
400 { ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
401 { ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register, false, true, true, SingleSpc, 4, 8 ,false},
402 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
403 { ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed, false, true, false, SingleSpc, 3, 8 ,false},
404 { ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register, false, true, true, SingleSpc, 3, 8 ,false},
405
406 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
407 { ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
408 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
409 { ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleHighTSpc, 3, 4 ,false},
410 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false},
411 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false},
412
413 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
414 { ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
415 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
416 { ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleHighTSpc, 3, 2 ,false},
417 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false},
418 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false},
419
420 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
421 { ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
422 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
423 { ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleHighTSpc, 3, 1 ,false},
424 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false},
425 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false},
426
427 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
428 { ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
429 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
430 { ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleHighTSpc, 3, 8 ,false},
431 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false},
432 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false},
433
434 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
435 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
436 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
437 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
438 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
439 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
440 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
441 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
442 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
443 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
444
445 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
446 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
447 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
448 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
449 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
450 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
451 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
452 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
453 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
454
455 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
456 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
457 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
458 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
459 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
460 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
461 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
462 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
463 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
464 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
465
466 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
467 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
468 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
469 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
470 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
471 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
472
473 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
474 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
475 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
476 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
477 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
478 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
479 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
480 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
481 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
482
483 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
484 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
485 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
486 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
487 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
488 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
489 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
490 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
491 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
492 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
493
494 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
495 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
496 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
497 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
498 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
499 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
500
501 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
502 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
503 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
504 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
505 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
506 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
507 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
508 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
509 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
510 };
511
512 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
513 /// load or store pseudo instruction.
LookupNEONLdSt(unsigned Opcode)514 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
515 #ifndef NDEBUG
516 // Make sure the table is sorted.
517 static std::atomic<bool> TableChecked(false);
518 if (!TableChecked.load(std::memory_order_relaxed)) {
519 assert(llvm::is_sorted(NEONLdStTable) && "NEONLdStTable is not sorted!");
520 TableChecked.store(true, std::memory_order_relaxed);
521 }
522 #endif
523
524 auto I = llvm::lower_bound(NEONLdStTable, Opcode);
525 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
526 return I;
527 return nullptr;
528 }
529
530 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
531 /// corresponding to the specified register spacing. Not all of the results
532 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
GetDSubRegs(unsigned Reg,NEONRegSpacing RegSpc,const TargetRegisterInfo * TRI,unsigned & D0,unsigned & D1,unsigned & D2,unsigned & D3)533 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
534 const TargetRegisterInfo *TRI, unsigned &D0,
535 unsigned &D1, unsigned &D2, unsigned &D3) {
536 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
537 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
538 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
539 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
540 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
541 } else if (RegSpc == SingleHighQSpc) {
542 D0 = TRI->getSubReg(Reg, ARM::dsub_4);
543 D1 = TRI->getSubReg(Reg, ARM::dsub_5);
544 D2 = TRI->getSubReg(Reg, ARM::dsub_6);
545 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
546 } else if (RegSpc == SingleHighTSpc) {
547 D0 = TRI->getSubReg(Reg, ARM::dsub_3);
548 D1 = TRI->getSubReg(Reg, ARM::dsub_4);
549 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
550 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
551 } else if (RegSpc == EvenDblSpc) {
552 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
553 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
554 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
555 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
556 } else {
557 assert(RegSpc == OddDblSpc && "unknown register spacing");
558 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
559 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
560 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
561 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
562 }
563 }
564
565 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
566 /// operands to real VLD instructions with D register operands.
ExpandVLD(MachineBasicBlock::iterator & MBBI)567 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
568 MachineInstr &MI = *MBBI;
569 MachineBasicBlock &MBB = *MI.getParent();
570 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
571
572 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
573 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
574 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
575 unsigned NumRegs = TableEntry->NumRegs;
576
577 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
578 TII->get(TableEntry->RealOpc));
579 unsigned OpIdx = 0;
580
581 bool DstIsDead = MI.getOperand(OpIdx).isDead();
582 Register DstReg = MI.getOperand(OpIdx++).getReg();
583
584 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
585 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
586 TableEntry->RealOpc == ARM::VLD2DUPd32x2 ||
587 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
588 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
589 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed ||
590 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register ||
591 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register ||
592 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register;
593
594 if (IsVLD2DUP) {
595 unsigned SubRegIndex;
596 if (RegSpc == EvenDblSpc) {
597 SubRegIndex = ARM::dsub_0;
598 } else {
599 assert(RegSpc == OddDblSpc && "Unexpected spacing!");
600 SubRegIndex = ARM::dsub_1;
601 }
602 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex);
603 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
604 &ARM::DPairSpcRegClass);
605 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
606 } else {
607 unsigned D0, D1, D2, D3;
608 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
609 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
610 if (NumRegs > 1 && TableEntry->copyAllListRegs)
611 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
612 if (NumRegs > 2 && TableEntry->copyAllListRegs)
613 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
614 if (NumRegs > 3 && TableEntry->copyAllListRegs)
615 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
616 }
617
618 if (TableEntry->isUpdating)
619 MIB.add(MI.getOperand(OpIdx++));
620
621 // Copy the addrmode6 operands.
622 MIB.add(MI.getOperand(OpIdx++));
623 MIB.add(MI.getOperand(OpIdx++));
624
625 // Copy the am6offset operand.
626 if (TableEntry->hasWritebackOperand) {
627 // TODO: The writing-back pseudo instructions we translate here are all
628 // defined to take am6offset nodes that are capable to represent both fixed
629 // and register forms. Some real instructions, however, do not rely on
630 // am6offset and have separate definitions for such forms. When this is the
631 // case, fixed forms do not take any offset nodes, so here we skip them for
632 // such instructions. Once all real and pseudo writing-back instructions are
633 // rewritten without use of am6offset nodes, this code will go away.
634 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
635 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
636 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
637 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
638 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
639 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
640 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
641 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
642 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed ||
643 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
644 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
645 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) {
646 assert(AM6Offset.getReg() == 0 &&
647 "A fixed writing-back pseudo instruction provides an offset "
648 "register!");
649 } else {
650 MIB.add(AM6Offset);
651 }
652 }
653
654 // For an instruction writing double-spaced subregs, the pseudo instruction
655 // has an extra operand that is a use of the super-register. Record the
656 // operand index and skip over it.
657 unsigned SrcOpIdx = 0;
658 if (!IsVLD2DUP) {
659 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc ||
660 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc ||
661 RegSpc == SingleHighTSpc)
662 SrcOpIdx = OpIdx++;
663 }
664
665 // Copy the predicate operands.
666 MIB.add(MI.getOperand(OpIdx++));
667 MIB.add(MI.getOperand(OpIdx++));
668
669 // Copy the super-register source operand used for double-spaced subregs over
670 // to the new instruction as an implicit operand.
671 if (SrcOpIdx != 0) {
672 MachineOperand MO = MI.getOperand(SrcOpIdx);
673 MO.setImplicit(true);
674 MIB.add(MO);
675 }
676 // Add an implicit def for the super-register.
677 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
678 TransferImpOps(MI, MIB, MIB);
679
680 // Transfer memoperands.
681 MIB.cloneMemRefs(MI);
682 MI.eraseFromParent();
683 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
684 }
685
686 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
687 /// operands to real VST instructions with D register operands.
ExpandVST(MachineBasicBlock::iterator & MBBI)688 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
689 MachineInstr &MI = *MBBI;
690 MachineBasicBlock &MBB = *MI.getParent();
691 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
692
693 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
694 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
695 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
696 unsigned NumRegs = TableEntry->NumRegs;
697
698 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
699 TII->get(TableEntry->RealOpc));
700 unsigned OpIdx = 0;
701 if (TableEntry->isUpdating)
702 MIB.add(MI.getOperand(OpIdx++));
703
704 // Copy the addrmode6 operands.
705 MIB.add(MI.getOperand(OpIdx++));
706 MIB.add(MI.getOperand(OpIdx++));
707
708 if (TableEntry->hasWritebackOperand) {
709 // TODO: The writing-back pseudo instructions we translate here are all
710 // defined to take am6offset nodes that are capable to represent both fixed
711 // and register forms. Some real instructions, however, do not rely on
712 // am6offset and have separate definitions for such forms. When this is the
713 // case, fixed forms do not take any offset nodes, so here we skip them for
714 // such instructions. Once all real and pseudo writing-back instructions are
715 // rewritten without use of am6offset nodes, this code will go away.
716 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
717 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
718 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
719 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
720 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
721 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
722 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
723 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
724 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
725 assert(AM6Offset.getReg() == 0 &&
726 "A fixed writing-back pseudo instruction provides an offset "
727 "register!");
728 } else {
729 MIB.add(AM6Offset);
730 }
731 }
732
733 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
734 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
735 Register SrcReg = MI.getOperand(OpIdx++).getReg();
736 unsigned D0, D1, D2, D3;
737 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
738 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
739 if (NumRegs > 1 && TableEntry->copyAllListRegs)
740 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
741 if (NumRegs > 2 && TableEntry->copyAllListRegs)
742 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
743 if (NumRegs > 3 && TableEntry->copyAllListRegs)
744 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
745
746 // Copy the predicate operands.
747 MIB.add(MI.getOperand(OpIdx++));
748 MIB.add(MI.getOperand(OpIdx++));
749
750 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
751 MIB->addRegisterKilled(SrcReg, TRI, true);
752 else if (!SrcIsUndef)
753 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
754 TransferImpOps(MI, MIB, MIB);
755
756 // Transfer memoperands.
757 MIB.cloneMemRefs(MI);
758 MI.eraseFromParent();
759 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
760 }
761
762 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
763 /// register operands to real instructions with D register operands.
ExpandLaneOp(MachineBasicBlock::iterator & MBBI)764 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
765 MachineInstr &MI = *MBBI;
766 MachineBasicBlock &MBB = *MI.getParent();
767 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
768
769 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
770 assert(TableEntry && "NEONLdStTable lookup failed");
771 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
772 unsigned NumRegs = TableEntry->NumRegs;
773 unsigned RegElts = TableEntry->RegElts;
774
775 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
776 TII->get(TableEntry->RealOpc));
777 unsigned OpIdx = 0;
778 // The lane operand is always the 3rd from last operand, before the 2
779 // predicate operands.
780 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
781
782 // Adjust the lane and spacing as needed for Q registers.
783 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
784 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
785 RegSpc = OddDblSpc;
786 Lane -= RegElts;
787 }
788 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
789
790 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
791 unsigned DstReg = 0;
792 bool DstIsDead = false;
793 if (TableEntry->IsLoad) {
794 DstIsDead = MI.getOperand(OpIdx).isDead();
795 DstReg = MI.getOperand(OpIdx++).getReg();
796 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
797 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
798 if (NumRegs > 1)
799 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
800 if (NumRegs > 2)
801 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
802 if (NumRegs > 3)
803 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
804 }
805
806 if (TableEntry->isUpdating)
807 MIB.add(MI.getOperand(OpIdx++));
808
809 // Copy the addrmode6 operands.
810 MIB.add(MI.getOperand(OpIdx++));
811 MIB.add(MI.getOperand(OpIdx++));
812 // Copy the am6offset operand.
813 if (TableEntry->hasWritebackOperand)
814 MIB.add(MI.getOperand(OpIdx++));
815
816 // Grab the super-register source.
817 MachineOperand MO = MI.getOperand(OpIdx++);
818 if (!TableEntry->IsLoad)
819 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
820
821 // Add the subregs as sources of the new instruction.
822 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
823 getKillRegState(MO.isKill()));
824 MIB.addReg(D0, SrcFlags);
825 if (NumRegs > 1)
826 MIB.addReg(D1, SrcFlags);
827 if (NumRegs > 2)
828 MIB.addReg(D2, SrcFlags);
829 if (NumRegs > 3)
830 MIB.addReg(D3, SrcFlags);
831
832 // Add the lane number operand.
833 MIB.addImm(Lane);
834 OpIdx += 1;
835
836 // Copy the predicate operands.
837 MIB.add(MI.getOperand(OpIdx++));
838 MIB.add(MI.getOperand(OpIdx++));
839
840 // Copy the super-register source to be an implicit source.
841 MO.setImplicit(true);
842 MIB.add(MO);
843 if (TableEntry->IsLoad)
844 // Add an implicit def for the super-register.
845 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
846 TransferImpOps(MI, MIB, MIB);
847 // Transfer memoperands.
848 MIB.cloneMemRefs(MI);
849 MI.eraseFromParent();
850 }
851
852 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
853 /// register operands to real instructions with D register operands.
ExpandVTBL(MachineBasicBlock::iterator & MBBI,unsigned Opc,bool IsExt)854 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
855 unsigned Opc, bool IsExt) {
856 MachineInstr &MI = *MBBI;
857 MachineBasicBlock &MBB = *MI.getParent();
858 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
859
860 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
861 unsigned OpIdx = 0;
862
863 // Transfer the destination register operand.
864 MIB.add(MI.getOperand(OpIdx++));
865 if (IsExt) {
866 MachineOperand VdSrc(MI.getOperand(OpIdx++));
867 MIB.add(VdSrc);
868 }
869
870 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
871 Register SrcReg = MI.getOperand(OpIdx++).getReg();
872 unsigned D0, D1, D2, D3;
873 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
874 MIB.addReg(D0);
875
876 // Copy the other source register operand.
877 MachineOperand VmSrc(MI.getOperand(OpIdx++));
878 MIB.add(VmSrc);
879
880 // Copy the predicate operands.
881 MIB.add(MI.getOperand(OpIdx++));
882 MIB.add(MI.getOperand(OpIdx++));
883
884 // Add an implicit kill and use for the super-reg.
885 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
886 TransferImpOps(MI, MIB, MIB);
887 MI.eraseFromParent();
888 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
889 }
890
ExpandMQQPRLoadStore(MachineBasicBlock::iterator & MBBI)891 void ARMExpandPseudo::ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI) {
892 MachineInstr &MI = *MBBI;
893 MachineBasicBlock &MBB = *MI.getParent();
894 unsigned NewOpc =
895 MI.getOpcode() == ARM::MQQPRStore || MI.getOpcode() == ARM::MQQQQPRStore
896 ? ARM::VSTMDIA
897 : ARM::VLDMDIA;
898 MachineInstrBuilder MIB =
899 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
900
901 unsigned Flags = getKillRegState(MI.getOperand(0).isKill()) |
902 getDefRegState(MI.getOperand(0).isDef());
903 Register SrcReg = MI.getOperand(0).getReg();
904
905 // Copy the destination register.
906 MIB.add(MI.getOperand(1));
907 MIB.add(predOps(ARMCC::AL));
908 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags);
909 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags);
910 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags);
911 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags);
912 if (MI.getOpcode() == ARM::MQQQQPRStore ||
913 MI.getOpcode() == ARM::MQQQQPRLoad) {
914 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags);
915 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags);
916 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags);
917 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags);
918 }
919
920 if (NewOpc == ARM::VSTMDIA)
921 MIB.addReg(SrcReg, RegState::Implicit);
922
923 TransferImpOps(MI, MIB, MIB);
924 MIB.cloneMemRefs(MI);
925 MI.eraseFromParent();
926 }
927
IsAnAddressOperand(const MachineOperand & MO)928 static bool IsAnAddressOperand(const MachineOperand &MO) {
929 // This check is overly conservative. Unless we are certain that the machine
930 // operand is not a symbol reference, we return that it is a symbol reference.
931 // This is important as the load pair may not be split up Windows.
932 switch (MO.getType()) {
933 case MachineOperand::MO_Register:
934 case MachineOperand::MO_Immediate:
935 case MachineOperand::MO_CImmediate:
936 case MachineOperand::MO_FPImmediate:
937 case MachineOperand::MO_ShuffleMask:
938 return false;
939 case MachineOperand::MO_MachineBasicBlock:
940 return true;
941 case MachineOperand::MO_FrameIndex:
942 return false;
943 case MachineOperand::MO_ConstantPoolIndex:
944 case MachineOperand::MO_TargetIndex:
945 case MachineOperand::MO_JumpTableIndex:
946 case MachineOperand::MO_ExternalSymbol:
947 case MachineOperand::MO_GlobalAddress:
948 case MachineOperand::MO_BlockAddress:
949 return true;
950 case MachineOperand::MO_RegisterMask:
951 case MachineOperand::MO_RegisterLiveOut:
952 return false;
953 case MachineOperand::MO_Metadata:
954 case MachineOperand::MO_MCSymbol:
955 return true;
956 case MachineOperand::MO_CFIIndex:
957 return false;
958 case MachineOperand::MO_IntrinsicID:
959 case MachineOperand::MO_Predicate:
960 llvm_unreachable("should not exist post-isel");
961 }
962 llvm_unreachable("unhandled machine operand type");
963 }
964
makeImplicit(const MachineOperand & MO)965 static MachineOperand makeImplicit(const MachineOperand &MO) {
966 MachineOperand NewMO = MO;
967 NewMO.setImplicit();
968 return NewMO;
969 }
970
ExpandMOV32BitImm(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI)971 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
972 MachineBasicBlock::iterator &MBBI) {
973 MachineInstr &MI = *MBBI;
974 unsigned Opcode = MI.getOpcode();
975 Register PredReg;
976 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
977 Register DstReg = MI.getOperand(0).getReg();
978 bool DstIsDead = MI.getOperand(0).isDead();
979 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
980 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
981 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
982 MachineInstrBuilder LO16, HI16;
983 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
984
985 if (!STI->hasV6T2Ops() &&
986 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
987 // FIXME Windows CE supports older ARM CPUs
988 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
989
990 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
991 unsigned ImmVal = (unsigned)MO.getImm();
992 unsigned SOImmValV1 = 0, SOImmValV2 = 0;
993
994 if (ARM_AM::isSOImmTwoPartVal(ImmVal)) { // Expand into a movi + orr.
995 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
996 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
997 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
998 .addReg(DstReg);
999 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1000 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1001 } else { // Expand into a mvn + sub.
1002 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg);
1003 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri))
1004 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1005 .addReg(DstReg);
1006 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(-ImmVal);
1007 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(-ImmVal);
1008 SOImmValV1 = ~(-SOImmValV1);
1009 }
1010
1011 unsigned MIFlags = MI.getFlags();
1012 LO16 = LO16.addImm(SOImmValV1);
1013 HI16 = HI16.addImm(SOImmValV2);
1014 LO16.cloneMemRefs(MI);
1015 HI16.cloneMemRefs(MI);
1016 LO16.setMIFlags(MIFlags);
1017 HI16.setMIFlags(MIFlags);
1018 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
1019 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
1020 if (isCC)
1021 LO16.add(makeImplicit(MI.getOperand(1)));
1022 TransferImpOps(MI, LO16, HI16);
1023 MI.eraseFromParent();
1024 return;
1025 }
1026
1027 unsigned LO16Opc = 0;
1028 unsigned HI16Opc = 0;
1029 unsigned MIFlags = MI.getFlags();
1030 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
1031 LO16Opc = ARM::t2MOVi16;
1032 HI16Opc = ARM::t2MOVTi16;
1033 } else {
1034 LO16Opc = ARM::MOVi16;
1035 HI16Opc = ARM::MOVTi16;
1036 }
1037
1038 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
1039 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
1040 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1041 .addReg(DstReg);
1042
1043 LO16.setMIFlags(MIFlags);
1044 HI16.setMIFlags(MIFlags);
1045
1046 switch (MO.getType()) {
1047 case MachineOperand::MO_Immediate: {
1048 unsigned Imm = MO.getImm();
1049 unsigned Lo16 = Imm & 0xffff;
1050 unsigned Hi16 = (Imm >> 16) & 0xffff;
1051 LO16 = LO16.addImm(Lo16);
1052 HI16 = HI16.addImm(Hi16);
1053 break;
1054 }
1055 case MachineOperand::MO_ExternalSymbol: {
1056 const char *ES = MO.getSymbolName();
1057 unsigned TF = MO.getTargetFlags();
1058 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
1059 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
1060 break;
1061 }
1062 default: {
1063 const GlobalValue *GV = MO.getGlobal();
1064 unsigned TF = MO.getTargetFlags();
1065 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
1066 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
1067 break;
1068 }
1069 }
1070
1071 LO16.cloneMemRefs(MI);
1072 HI16.cloneMemRefs(MI);
1073 LO16.addImm(Pred).addReg(PredReg);
1074 HI16.addImm(Pred).addReg(PredReg);
1075
1076 if (RequiresBundling)
1077 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
1078
1079 if (isCC)
1080 LO16.add(makeImplicit(MI.getOperand(1)));
1081 TransferImpOps(MI, LO16, HI16);
1082 MI.eraseFromParent();
1083 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump(););
1084 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump(););
1085 }
1086
1087 // The size of the area, accessed by that VLSTM/VLLDM
1088 // S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad)
1089 static const int CMSE_FP_SAVE_SIZE = 136;
1090
determineGPRegsToClear(const MachineInstr & MI,const std::initializer_list<unsigned> & Regs,SmallVectorImpl<unsigned> & ClearRegs)1091 static void determineGPRegsToClear(const MachineInstr &MI,
1092 const std::initializer_list<unsigned> &Regs,
1093 SmallVectorImpl<unsigned> &ClearRegs) {
1094 SmallVector<unsigned, 4> OpRegs;
1095 for (const MachineOperand &Op : MI.operands()) {
1096 if (!Op.isReg() || !Op.isUse())
1097 continue;
1098 OpRegs.push_back(Op.getReg());
1099 }
1100 llvm::sort(OpRegs);
1101
1102 std::set_difference(Regs.begin(), Regs.end(), OpRegs.begin(), OpRegs.end(),
1103 std::back_inserter(ClearRegs));
1104 }
1105
CMSEClearGPRegs(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,const SmallVectorImpl<unsigned> & ClearRegs,unsigned ClobberReg)1106 void ARMExpandPseudo::CMSEClearGPRegs(
1107 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
1108 const DebugLoc &DL, const SmallVectorImpl<unsigned> &ClearRegs,
1109 unsigned ClobberReg) {
1110
1111 if (STI->hasV8_1MMainlineOps()) {
1112 // Clear the registers using the CLRM instruction.
1113 MachineInstrBuilder CLRM =
1114 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL));
1115 for (unsigned R : ClearRegs)
1116 CLRM.addReg(R, RegState::Define);
1117 CLRM.addReg(ARM::APSR, RegState::Define);
1118 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1119 } else {
1120 // Clear the registers and flags by copying ClobberReg into them.
1121 // (Baseline can't do a high register clear in one instruction).
1122 for (unsigned Reg : ClearRegs) {
1123 if (Reg == ClobberReg)
1124 continue;
1125 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg)
1126 .addReg(ClobberReg)
1127 .add(predOps(ARMCC::AL));
1128 }
1129
1130 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M))
1131 .addImm(STI->hasDSP() ? 0xc00 : 0x800)
1132 .addReg(ClobberReg)
1133 .add(predOps(ARMCC::AL));
1134 }
1135 }
1136
1137 // Find which FP registers need to be cleared. The parameter `ClearRegs` is
1138 // initialised with all elements set to true, and this function resets all the
1139 // bits, which correspond to register uses. Returns true if any floating point
1140 // register is defined, false otherwise.
determineFPRegsToClear(const MachineInstr & MI,BitVector & ClearRegs)1141 static bool determineFPRegsToClear(const MachineInstr &MI,
1142 BitVector &ClearRegs) {
1143 bool DefFP = false;
1144 for (const MachineOperand &Op : MI.operands()) {
1145 if (!Op.isReg())
1146 continue;
1147
1148 Register Reg = Op.getReg();
1149 if (Op.isDef()) {
1150 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1151 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1152 (Reg >= ARM::S0 && Reg <= ARM::S31))
1153 DefFP = true;
1154 continue;
1155 }
1156
1157 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) {
1158 int R = Reg - ARM::Q0;
1159 ClearRegs.reset(R * 4, (R + 1) * 4);
1160 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) {
1161 int R = Reg - ARM::D0;
1162 ClearRegs.reset(R * 2, (R + 1) * 2);
1163 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) {
1164 ClearRegs[Reg - ARM::S0] = false;
1165 }
1166 }
1167 return DefFP;
1168 }
1169
1170 MachineBasicBlock &
CMSEClearFPRegs(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI)1171 ARMExpandPseudo::CMSEClearFPRegs(MachineBasicBlock &MBB,
1172 MachineBasicBlock::iterator MBBI) {
1173 BitVector ClearRegs(16, true);
1174 (void)determineFPRegsToClear(*MBBI, ClearRegs);
1175
1176 if (STI->hasV8_1MMainlineOps())
1177 return CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1178 else
1179 return CMSEClearFPRegsV8(MBB, MBBI, ClearRegs);
1180 }
1181
1182 // Clear the FP registers for v8.0-M, by copying over the content
1183 // of LR. Uses R12 as a scratch register.
1184 MachineBasicBlock &
CMSEClearFPRegsV8(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const BitVector & ClearRegs)1185 ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB,
1186 MachineBasicBlock::iterator MBBI,
1187 const BitVector &ClearRegs) {
1188 if (!STI->hasFPRegs())
1189 return MBB;
1190
1191 auto &RetI = *MBBI;
1192 const DebugLoc &DL = RetI.getDebugLoc();
1193
1194 // If optimising for minimum size, clear FP registers unconditionally.
1195 // Otherwise, check the CONTROL.SFPA (Secure Floating-Point Active) bit and
1196 // don't clear them if they belong to the non-secure state.
1197 MachineBasicBlock *ClearBB, *DoneBB;
1198 if (STI->hasMinSize()) {
1199 ClearBB = DoneBB = &MBB;
1200 } else {
1201 MachineFunction *MF = MBB.getParent();
1202 ClearBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1203 DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1204
1205 MF->insert(++MBB.getIterator(), ClearBB);
1206 MF->insert(++ClearBB->getIterator(), DoneBB);
1207
1208 DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end());
1209 DoneBB->transferSuccessors(&MBB);
1210 MBB.addSuccessor(ClearBB);
1211 MBB.addSuccessor(DoneBB);
1212 ClearBB->addSuccessor(DoneBB);
1213
1214 // At the new basic blocks we need to have live-in the registers, used
1215 // for the return value as well as LR, used to clear registers.
1216 for (const MachineOperand &Op : RetI.operands()) {
1217 if (!Op.isReg())
1218 continue;
1219 Register Reg = Op.getReg();
1220 if (Reg == ARM::NoRegister || Reg == ARM::LR)
1221 continue;
1222 assert(Register::isPhysicalRegister(Reg) && "Unallocated register");
1223 ClearBB->addLiveIn(Reg);
1224 DoneBB->addLiveIn(Reg);
1225 }
1226 ClearBB->addLiveIn(ARM::LR);
1227 DoneBB->addLiveIn(ARM::LR);
1228
1229 // Read the CONTROL register.
1230 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12)
1231 .addImm(20)
1232 .add(predOps(ARMCC::AL));
1233 // Check bit 3 (SFPA).
1234 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri))
1235 .addReg(ARM::R12)
1236 .addImm(8)
1237 .add(predOps(ARMCC::AL));
1238 // If SFPA is clear, jump over ClearBB to DoneBB.
1239 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc))
1240 .addMBB(DoneBB)
1241 .addImm(ARMCC::EQ)
1242 .addReg(ARM::CPSR, RegState::Kill);
1243 }
1244
1245 // Emit the clearing sequence
1246 for (unsigned D = 0; D < 8; D++) {
1247 // Attempt to clear as double
1248 if (ClearRegs[D * 2 + 0] && ClearRegs[D * 2 + 1]) {
1249 unsigned Reg = ARM::D0 + D;
1250 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg)
1251 .addReg(ARM::LR)
1252 .addReg(ARM::LR)
1253 .add(predOps(ARMCC::AL));
1254 } else {
1255 // Clear first part as single
1256 if (ClearRegs[D * 2 + 0]) {
1257 unsigned Reg = ARM::S0 + D * 2;
1258 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg)
1259 .addReg(ARM::LR)
1260 .add(predOps(ARMCC::AL));
1261 }
1262 // Clear second part as single
1263 if (ClearRegs[D * 2 + 1]) {
1264 unsigned Reg = ARM::S0 + D * 2 + 1;
1265 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg)
1266 .addReg(ARM::LR)
1267 .add(predOps(ARMCC::AL));
1268 }
1269 }
1270 }
1271
1272 // Clear FPSCR bits 0-4, 7, 28-31
1273 // The other bits are program global according to the AAPCS
1274 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12)
1275 .add(predOps(ARMCC::AL));
1276 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12)
1277 .addReg(ARM::R12)
1278 .addImm(0x0000009F)
1279 .add(predOps(ARMCC::AL))
1280 .add(condCodeOp());
1281 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12)
1282 .addReg(ARM::R12)
1283 .addImm(0xF0000000)
1284 .add(predOps(ARMCC::AL))
1285 .add(condCodeOp());
1286 BuildMI(ClearBB, DL, TII->get(ARM::VMSR))
1287 .addReg(ARM::R12)
1288 .add(predOps(ARMCC::AL));
1289
1290 return *DoneBB;
1291 }
1292
1293 MachineBasicBlock &
CMSEClearFPRegsV81(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const BitVector & ClearRegs)1294 ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB,
1295 MachineBasicBlock::iterator MBBI,
1296 const BitVector &ClearRegs) {
1297 auto &RetI = *MBBI;
1298
1299 // Emit a sequence of VSCCLRM <sreglist> instructions, one instruction for
1300 // each contiguous sequence of S-registers.
1301 int Start = -1, End = -1;
1302 for (int S = 0, E = ClearRegs.size(); S != E; ++S) {
1303 if (ClearRegs[S] && S == End + 1) {
1304 End = S; // extend range
1305 continue;
1306 }
1307 // Emit current range.
1308 if (Start < End) {
1309 MachineInstrBuilder VSCCLRM =
1310 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1311 .add(predOps(ARMCC::AL));
1312 while (++Start <= End)
1313 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define);
1314 VSCCLRM.addReg(ARM::VPR, RegState::Define);
1315 }
1316 Start = End = S;
1317 }
1318 // Emit last range.
1319 if (Start < End) {
1320 MachineInstrBuilder VSCCLRM =
1321 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1322 .add(predOps(ARMCC::AL));
1323 while (++Start <= End)
1324 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define);
1325 VSCCLRM.addReg(ARM::VPR, RegState::Define);
1326 }
1327
1328 return MBB;
1329 }
1330
CMSESaveClearFPRegs(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc & DL,const LivePhysRegs & LiveRegs,SmallVectorImpl<unsigned> & ScratchRegs)1331 void ARMExpandPseudo::CMSESaveClearFPRegs(
1332 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1333 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
1334 if (STI->hasV8_1MMainlineOps())
1335 CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
1336 else if (STI->hasV8MMainlineOps())
1337 CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs);
1338 }
1339
1340 // Save and clear FP registers if present
CMSESaveClearFPRegsV8(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc & DL,const LivePhysRegs & LiveRegs,SmallVectorImpl<unsigned> & ScratchRegs)1341 void ARMExpandPseudo::CMSESaveClearFPRegsV8(
1342 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1343 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
1344
1345 // Store an available register for FPSCR clearing
1346 assert(!ScratchRegs.empty());
1347 unsigned SpareReg = ScratchRegs.front();
1348
1349 // save space on stack for VLSTM
1350 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1351 .addReg(ARM::SP)
1352 .addImm(CMSE_FP_SAVE_SIZE >> 2)
1353 .add(predOps(ARMCC::AL));
1354
1355 // Use ScratchRegs to store the fp regs
1356 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1357 std::vector<unsigned> NonclearedFPRegs;
1358 for (const MachineOperand &Op : MBBI->operands()) {
1359 if (Op.isReg() && Op.isUse()) {
1360 Register Reg = Op.getReg();
1361 assert(!ARM::DPRRegClass.contains(Reg) ||
1362 ARM::DPR_VFP2RegClass.contains(Reg));
1363 assert(!ARM::QPRRegClass.contains(Reg));
1364 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1365 if (ScratchRegs.size() >= 2) {
1366 unsigned SaveReg2 = ScratchRegs.pop_back_val();
1367 unsigned SaveReg1 = ScratchRegs.pop_back_val();
1368 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
1369
1370 // Save the fp register to the normal registers
1371 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1372 .addReg(SaveReg1, RegState::Define)
1373 .addReg(SaveReg2, RegState::Define)
1374 .addReg(Reg)
1375 .add(predOps(ARMCC::AL));
1376 } else {
1377 NonclearedFPRegs.push_back(Reg);
1378 }
1379 } else if (ARM::SPRRegClass.contains(Reg)) {
1380 if (ScratchRegs.size() >= 1) {
1381 unsigned SaveReg = ScratchRegs.pop_back_val();
1382 ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
1383
1384 // Save the fp register to the normal registers
1385 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1386 .addReg(Reg)
1387 .add(predOps(ARMCC::AL));
1388 } else {
1389 NonclearedFPRegs.push_back(Reg);
1390 }
1391 }
1392 }
1393 }
1394
1395 bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1396
1397 if (passesFPReg)
1398 assert(STI->hasFPRegs() && "Subtarget needs fpregs");
1399
1400 // Lazy store all fp registers to the stack.
1401 // This executes as NOP in the absence of floating-point support.
1402 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1403 .addReg(ARM::SP)
1404 .add(predOps(ARMCC::AL));
1405 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
1406 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1407 VLSTM.addReg(R, RegState::Implicit |
1408 (LiveRegs.contains(R) ? 0 : RegState::Undef));
1409
1410 // Restore all arguments
1411 for (const auto &Regs : ClearedFPRegs) {
1412 unsigned Reg, SaveReg1, SaveReg2;
1413 std::tie(Reg, SaveReg1, SaveReg2) = Regs;
1414 if (ARM::DPR_VFP2RegClass.contains(Reg))
1415 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1416 .addReg(SaveReg1)
1417 .addReg(SaveReg2)
1418 .add(predOps(ARMCC::AL));
1419 else if (ARM::SPRRegClass.contains(Reg))
1420 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1421 .addReg(SaveReg1)
1422 .add(predOps(ARMCC::AL));
1423 }
1424
1425 for (unsigned Reg : NonclearedFPRegs) {
1426 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1427 if (STI->isLittle()) {
1428 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg)
1429 .addReg(ARM::SP)
1430 .addImm((Reg - ARM::D0) * 2)
1431 .add(predOps(ARMCC::AL));
1432 } else {
1433 // For big-endian targets we need to load the two subregisters of Reg
1434 // manually because VLDRD would load them in wrong order
1435 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0);
1436 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0)
1437 .addReg(ARM::SP)
1438 .addImm((Reg - ARM::D0) * 2)
1439 .add(predOps(ARMCC::AL));
1440 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1)
1441 .addReg(ARM::SP)
1442 .addImm((Reg - ARM::D0) * 2 + 1)
1443 .add(predOps(ARMCC::AL));
1444 }
1445 } else if (ARM::SPRRegClass.contains(Reg)) {
1446 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg)
1447 .addReg(ARM::SP)
1448 .addImm(Reg - ARM::S0)
1449 .add(predOps(ARMCC::AL));
1450 }
1451 }
1452 // restore FPSCR from stack and clear bits 0-4, 7, 28-31
1453 // The other bits are program global according to the AAPCS
1454 if (passesFPReg) {
1455 BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg)
1456 .addReg(ARM::SP)
1457 .addImm(0x10)
1458 .add(predOps(ARMCC::AL));
1459 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1460 .addReg(SpareReg)
1461 .addImm(0x0000009F)
1462 .add(predOps(ARMCC::AL))
1463 .add(condCodeOp());
1464 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1465 .addReg(SpareReg)
1466 .addImm(0xF0000000)
1467 .add(predOps(ARMCC::AL))
1468 .add(condCodeOp());
1469 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR))
1470 .addReg(SpareReg)
1471 .add(predOps(ARMCC::AL));
1472 // The ldr must happen after a floating point instruction. To prevent the
1473 // post-ra scheduler to mess with the order, we create a bundle.
1474 finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator());
1475 }
1476 }
1477
CMSESaveClearFPRegsV81(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc & DL,const LivePhysRegs & LiveRegs)1478 void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
1479 MachineBasicBlock::iterator MBBI,
1480 DebugLoc &DL,
1481 const LivePhysRegs &LiveRegs) {
1482 BitVector ClearRegs(32, true);
1483 bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs);
1484
1485 // If the instruction does not write to a FP register and no elements were
1486 // removed from the set, then no FP registers were used to pass
1487 // arguments/returns.
1488 if (!DefFP && ClearRegs.count() == ClearRegs.size()) {
1489 // save space on stack for VLSTM
1490 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1491 .addReg(ARM::SP)
1492 .addImm(CMSE_FP_SAVE_SIZE >> 2)
1493 .add(predOps(ARMCC::AL));
1494
1495 // Lazy store all FP registers to the stack
1496 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1497 .addReg(ARM::SP)
1498 .add(predOps(ARMCC::AL));
1499 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
1500 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1501 VLSTM.addReg(R, RegState::Implicit |
1502 (LiveRegs.contains(R) ? 0 : RegState::Undef));
1503 } else {
1504 // Push all the callee-saved registers (s16-s31).
1505 MachineInstrBuilder VPUSH =
1506 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP)
1507 .addReg(ARM::SP)
1508 .add(predOps(ARMCC::AL));
1509 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
1510 VPUSH.addReg(Reg);
1511
1512 // Clear FP registers with a VSCCLRM.
1513 (void)CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1514
1515 // Save floating-point context.
1516 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP)
1517 .addReg(ARM::SP)
1518 .addImm(-8)
1519 .add(predOps(ARMCC::AL));
1520 }
1521 }
1522
1523 // Restore FP registers if present
CMSERestoreFPRegs(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc & DL,SmallVectorImpl<unsigned> & AvailableRegs)1524 void ARMExpandPseudo::CMSERestoreFPRegs(
1525 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1526 SmallVectorImpl<unsigned> &AvailableRegs) {
1527 if (STI->hasV8_1MMainlineOps())
1528 CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs);
1529 else if (STI->hasV8MMainlineOps())
1530 CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs);
1531 }
1532
CMSERestoreFPRegsV8(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc & DL,SmallVectorImpl<unsigned> & AvailableRegs)1533 void ARMExpandPseudo::CMSERestoreFPRegsV8(
1534 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1535 SmallVectorImpl<unsigned> &AvailableRegs) {
1536
1537 // Keep a scratch register for the mitigation sequence.
1538 unsigned ScratchReg = ARM::NoRegister;
1539 if (STI->fixCMSE_CVE_2021_35465())
1540 ScratchReg = AvailableRegs.pop_back_val();
1541
1542 // Use AvailableRegs to store the fp regs
1543 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1544 std::vector<unsigned> NonclearedFPRegs;
1545 for (const MachineOperand &Op : MBBI->operands()) {
1546 if (Op.isReg() && Op.isDef()) {
1547 Register Reg = Op.getReg();
1548 assert(!ARM::DPRRegClass.contains(Reg) ||
1549 ARM::DPR_VFP2RegClass.contains(Reg));
1550 assert(!ARM::QPRRegClass.contains(Reg));
1551 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1552 if (AvailableRegs.size() >= 2) {
1553 unsigned SaveReg2 = AvailableRegs.pop_back_val();
1554 unsigned SaveReg1 = AvailableRegs.pop_back_val();
1555 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
1556
1557 // Save the fp register to the normal registers
1558 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1559 .addReg(SaveReg1, RegState::Define)
1560 .addReg(SaveReg2, RegState::Define)
1561 .addReg(Reg)
1562 .add(predOps(ARMCC::AL));
1563 } else {
1564 NonclearedFPRegs.push_back(Reg);
1565 }
1566 } else if (ARM::SPRRegClass.contains(Reg)) {
1567 if (AvailableRegs.size() >= 1) {
1568 unsigned SaveReg = AvailableRegs.pop_back_val();
1569 ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
1570
1571 // Save the fp register to the normal registers
1572 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1573 .addReg(Reg)
1574 .add(predOps(ARMCC::AL));
1575 } else {
1576 NonclearedFPRegs.push_back(Reg);
1577 }
1578 }
1579 }
1580 }
1581
1582 bool returnsFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1583
1584 if (returnsFPReg)
1585 assert(STI->hasFPRegs() && "Subtarget needs fpregs");
1586
1587 // Push FP regs that cannot be restored via normal registers on the stack
1588 for (unsigned Reg : NonclearedFPRegs) {
1589 if (ARM::DPR_VFP2RegClass.contains(Reg))
1590 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD))
1591 .addReg(Reg)
1592 .addReg(ARM::SP)
1593 .addImm((Reg - ARM::D0) * 2)
1594 .add(predOps(ARMCC::AL));
1595 else if (ARM::SPRRegClass.contains(Reg))
1596 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS))
1597 .addReg(Reg)
1598 .addReg(ARM::SP)
1599 .addImm(Reg - ARM::S0)
1600 .add(predOps(ARMCC::AL));
1601 }
1602
1603 // Lazy load fp regs from stack.
1604 // This executes as NOP in the absence of floating-point support.
1605 MachineInstrBuilder VLLDM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1606 .addReg(ARM::SP)
1607 .add(predOps(ARMCC::AL));
1608
1609 if (STI->fixCMSE_CVE_2021_35465()) {
1610 auto Bundler = MIBundleBuilder(MBB, VLLDM);
1611 // Read the CONTROL register.
1612 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2MRS_M))
1613 .addReg(ScratchReg, RegState::Define)
1614 .addImm(20)
1615 .add(predOps(ARMCC::AL)));
1616 // Check bit 3 (SFPA).
1617 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2TSTri))
1618 .addReg(ScratchReg)
1619 .addImm(8)
1620 .add(predOps(ARMCC::AL)));
1621 // Emit the IT block.
1622 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2IT))
1623 .addImm(ARMCC::NE)
1624 .addImm(8));
1625 // If SFPA is clear jump over to VLLDM, otherwise execute an instruction
1626 // which has no functional effect apart from causing context creation:
1627 // vmovne s0, s0. In the absence of FPU we emit .inst.w 0xeeb00a40,
1628 // which is defined as NOP if not executed.
1629 if (STI->hasFPRegs())
1630 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::VMOVS))
1631 .addReg(ARM::S0, RegState::Define)
1632 .addReg(ARM::S0, RegState::Undef)
1633 .add(predOps(ARMCC::NE)));
1634 else
1635 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::INLINEASM))
1636 .addExternalSymbol(".inst.w 0xeeb00a40")
1637 .addImm(InlineAsm::Extra_HasSideEffects));
1638 finalizeBundle(MBB, Bundler.begin(), Bundler.end());
1639 }
1640
1641 // Restore all FP registers via normal registers
1642 for (const auto &Regs : ClearedFPRegs) {
1643 unsigned Reg, SaveReg1, SaveReg2;
1644 std::tie(Reg, SaveReg1, SaveReg2) = Regs;
1645 if (ARM::DPR_VFP2RegClass.contains(Reg))
1646 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1647 .addReg(SaveReg1)
1648 .addReg(SaveReg2)
1649 .add(predOps(ARMCC::AL));
1650 else if (ARM::SPRRegClass.contains(Reg))
1651 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1652 .addReg(SaveReg1)
1653 .add(predOps(ARMCC::AL));
1654 }
1655
1656 // Pop the stack space
1657 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1658 .addReg(ARM::SP)
1659 .addImm(CMSE_FP_SAVE_SIZE >> 2)
1660 .add(predOps(ARMCC::AL));
1661 }
1662
definesOrUsesFPReg(const MachineInstr & MI)1663 static bool definesOrUsesFPReg(const MachineInstr &MI) {
1664 for (const MachineOperand &Op : MI.operands()) {
1665 if (!Op.isReg())
1666 continue;
1667 Register Reg = Op.getReg();
1668 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1669 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1670 (Reg >= ARM::S0 && Reg <= ARM::S31))
1671 return true;
1672 }
1673 return false;
1674 }
1675
CMSERestoreFPRegsV81(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc & DL,SmallVectorImpl<unsigned> & AvailableRegs)1676 void ARMExpandPseudo::CMSERestoreFPRegsV81(
1677 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1678 SmallVectorImpl<unsigned> &AvailableRegs) {
1679 if (!definesOrUsesFPReg(*MBBI)) {
1680 if (STI->fixCMSE_CVE_2021_35465()) {
1681 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS))
1682 .add(predOps(ARMCC::AL))
1683 .addReg(ARM::VPR, RegState::Define);
1684 }
1685
1686 // Load FP registers from stack.
1687 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1688 .addReg(ARM::SP)
1689 .add(predOps(ARMCC::AL));
1690
1691 // Pop the stack space
1692 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1693 .addReg(ARM::SP)
1694 .addImm(CMSE_FP_SAVE_SIZE >> 2)
1695 .add(predOps(ARMCC::AL));
1696 } else {
1697 // Restore the floating point context.
1698 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post),
1699 ARM::SP)
1700 .addReg(ARM::SP)
1701 .addImm(8)
1702 .add(predOps(ARMCC::AL));
1703
1704 // Pop all the callee-saved registers (s16-s31).
1705 MachineInstrBuilder VPOP =
1706 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP)
1707 .addReg(ARM::SP)
1708 .add(predOps(ARMCC::AL));
1709 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
1710 VPOP.addReg(Reg, RegState::Define);
1711 }
1712 }
1713
1714 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
1715 /// possible. This only gets used at -O0 so we don't care about efficiency of
1716 /// the generated code.
ExpandCMP_SWAP(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,unsigned LdrexOp,unsigned StrexOp,unsigned UxtOp,MachineBasicBlock::iterator & NextMBBI)1717 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
1718 MachineBasicBlock::iterator MBBI,
1719 unsigned LdrexOp, unsigned StrexOp,
1720 unsigned UxtOp,
1721 MachineBasicBlock::iterator &NextMBBI) {
1722 bool IsThumb = STI->isThumb();
1723 bool IsThumb1Only = STI->isThumb1Only();
1724 MachineInstr &MI = *MBBI;
1725 DebugLoc DL = MI.getDebugLoc();
1726 const MachineOperand &Dest = MI.getOperand(0);
1727 Register TempReg = MI.getOperand(1).getReg();
1728 // Duplicating undef operands into 2 instructions does not guarantee the same
1729 // value on both; However undef should be replaced by xzr anyway.
1730 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1731 Register AddrReg = MI.getOperand(2).getReg();
1732 Register DesiredReg = MI.getOperand(3).getReg();
1733 Register NewReg = MI.getOperand(4).getReg();
1734
1735 if (IsThumb) {
1736 assert(STI->hasV8MBaselineOps() &&
1737 "CMP_SWAP not expected to be custom expanded for Thumb1");
1738 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
1739 "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
1740 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) &&
1741 "DesiredReg used for UXT op must be tGPR");
1742 }
1743
1744 MachineFunction *MF = MBB.getParent();
1745 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1746 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1747 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1748
1749 MF->insert(++MBB.getIterator(), LoadCmpBB);
1750 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
1751 MF->insert(++StoreBB->getIterator(), DoneBB);
1752
1753 if (UxtOp) {
1754 MachineInstrBuilder MIB =
1755 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
1756 .addReg(DesiredReg, RegState::Kill);
1757 if (!IsThumb)
1758 MIB.addImm(0);
1759 MIB.add(predOps(ARMCC::AL));
1760 }
1761
1762 // .Lloadcmp:
1763 // ldrex rDest, [rAddr]
1764 // cmp rDest, rDesired
1765 // bne .Ldone
1766
1767 MachineInstrBuilder MIB;
1768 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
1769 MIB.addReg(AddrReg);
1770 if (LdrexOp == ARM::t2LDREX)
1771 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
1772 MIB.add(predOps(ARMCC::AL));
1773
1774 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1775 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1776 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
1777 .addReg(DesiredReg)
1778 .add(predOps(ARMCC::AL));
1779 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1780 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1781 .addMBB(DoneBB)
1782 .addImm(ARMCC::NE)
1783 .addReg(ARM::CPSR, RegState::Kill);
1784 LoadCmpBB->addSuccessor(DoneBB);
1785 LoadCmpBB->addSuccessor(StoreBB);
1786
1787 // .Lstore:
1788 // strex rTempReg, rNew, [rAddr]
1789 // cmp rTempReg, #0
1790 // bne .Lloadcmp
1791 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
1792 .addReg(NewReg)
1793 .addReg(AddrReg);
1794 if (StrexOp == ARM::t2STREX)
1795 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
1796 MIB.add(predOps(ARMCC::AL));
1797
1798 unsigned CMPri =
1799 IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri;
1800 BuildMI(StoreBB, DL, TII->get(CMPri))
1801 .addReg(TempReg, RegState::Kill)
1802 .addImm(0)
1803 .add(predOps(ARMCC::AL));
1804 BuildMI(StoreBB, DL, TII->get(Bcc))
1805 .addMBB(LoadCmpBB)
1806 .addImm(ARMCC::NE)
1807 .addReg(ARM::CPSR, RegState::Kill);
1808 StoreBB->addSuccessor(LoadCmpBB);
1809 StoreBB->addSuccessor(DoneBB);
1810
1811 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1812 DoneBB->transferSuccessors(&MBB);
1813
1814 MBB.addSuccessor(LoadCmpBB);
1815
1816 NextMBBI = MBB.end();
1817 MI.eraseFromParent();
1818
1819 // Recompute livein lists.
1820 LivePhysRegs LiveRegs;
1821 computeAndAddLiveIns(LiveRegs, *DoneBB);
1822 computeAndAddLiveIns(LiveRegs, *StoreBB);
1823 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1824 // Do an extra pass around the loop to get loop carried registers right.
1825 StoreBB->clearLiveIns();
1826 computeAndAddLiveIns(LiveRegs, *StoreBB);
1827 LoadCmpBB->clearLiveIns();
1828 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1829
1830 return true;
1831 }
1832
1833 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1834 /// single GPRPair register), Thumb's take two separate registers so we need to
1835 /// extract the subregs from the pair.
addExclusiveRegPair(MachineInstrBuilder & MIB,MachineOperand & Reg,unsigned Flags,bool IsThumb,const TargetRegisterInfo * TRI)1836 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1837 unsigned Flags, bool IsThumb,
1838 const TargetRegisterInfo *TRI) {
1839 if (IsThumb) {
1840 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1841 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1842 MIB.addReg(RegLo, Flags);
1843 MIB.addReg(RegHi, Flags);
1844 } else
1845 MIB.addReg(Reg.getReg(), Flags);
1846 }
1847
1848 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
ExpandCMP_SWAP_64(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,MachineBasicBlock::iterator & NextMBBI)1849 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
1850 MachineBasicBlock::iterator MBBI,
1851 MachineBasicBlock::iterator &NextMBBI) {
1852 bool IsThumb = STI->isThumb();
1853 assert(!STI->isThumb1Only() && "CMP_SWAP_64 unsupported under Thumb1!");
1854 MachineInstr &MI = *MBBI;
1855 DebugLoc DL = MI.getDebugLoc();
1856 MachineOperand &Dest = MI.getOperand(0);
1857 Register TempReg = MI.getOperand(1).getReg();
1858 // Duplicating undef operands into 2 instructions does not guarantee the same
1859 // value on both; However undef should be replaced by xzr anyway.
1860 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1861 Register AddrReg = MI.getOperand(2).getReg();
1862 Register DesiredReg = MI.getOperand(3).getReg();
1863 MachineOperand New = MI.getOperand(4);
1864 New.setIsKill(false);
1865
1866 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1867 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1868 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1869 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1870
1871 MachineFunction *MF = MBB.getParent();
1872 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1873 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1874 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1875
1876 MF->insert(++MBB.getIterator(), LoadCmpBB);
1877 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
1878 MF->insert(++StoreBB->getIterator(), DoneBB);
1879
1880 // .Lloadcmp:
1881 // ldrexd rDestLo, rDestHi, [rAddr]
1882 // cmp rDestLo, rDesiredLo
1883 // sbcs dead rTempReg, rDestHi, rDesiredHi
1884 // bne .Ldone
1885 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1886 MachineInstrBuilder MIB;
1887 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
1888 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
1889 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1890
1891 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1892 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1893 .addReg(DestLo, getKillRegState(Dest.isDead()))
1894 .addReg(DesiredLo)
1895 .add(predOps(ARMCC::AL));
1896
1897 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1898 .addReg(DestHi, getKillRegState(Dest.isDead()))
1899 .addReg(DesiredHi)
1900 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1901
1902 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1903 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1904 .addMBB(DoneBB)
1905 .addImm(ARMCC::NE)
1906 .addReg(ARM::CPSR, RegState::Kill);
1907 LoadCmpBB->addSuccessor(DoneBB);
1908 LoadCmpBB->addSuccessor(StoreBB);
1909
1910 // .Lstore:
1911 // strexd rTempReg, rNewLo, rNewHi, [rAddr]
1912 // cmp rTempReg, #0
1913 // bne .Lloadcmp
1914 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
1915 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
1916 unsigned Flags = getKillRegState(New.isDead());
1917 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI);
1918 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1919
1920 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1921 BuildMI(StoreBB, DL, TII->get(CMPri))
1922 .addReg(TempReg, RegState::Kill)
1923 .addImm(0)
1924 .add(predOps(ARMCC::AL));
1925 BuildMI(StoreBB, DL, TII->get(Bcc))
1926 .addMBB(LoadCmpBB)
1927 .addImm(ARMCC::NE)
1928 .addReg(ARM::CPSR, RegState::Kill);
1929 StoreBB->addSuccessor(LoadCmpBB);
1930 StoreBB->addSuccessor(DoneBB);
1931
1932 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1933 DoneBB->transferSuccessors(&MBB);
1934
1935 MBB.addSuccessor(LoadCmpBB);
1936
1937 NextMBBI = MBB.end();
1938 MI.eraseFromParent();
1939
1940 // Recompute livein lists.
1941 LivePhysRegs LiveRegs;
1942 computeAndAddLiveIns(LiveRegs, *DoneBB);
1943 computeAndAddLiveIns(LiveRegs, *StoreBB);
1944 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1945 // Do an extra pass around the loop to get loop carried registers right.
1946 StoreBB->clearLiveIns();
1947 computeAndAddLiveIns(LiveRegs, *StoreBB);
1948 LoadCmpBB->clearLiveIns();
1949 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1950
1951 return true;
1952 }
1953
CMSEPushCalleeSaves(const TargetInstrInfo & TII,MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,int JumpReg,const LivePhysRegs & LiveRegs,bool Thumb1Only)1954 static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
1955 MachineBasicBlock &MBB,
1956 MachineBasicBlock::iterator MBBI, int JumpReg,
1957 const LivePhysRegs &LiveRegs, bool Thumb1Only) {
1958 const DebugLoc &DL = MBBI->getDebugLoc();
1959 if (Thumb1Only) { // push Lo and Hi regs separately
1960 MachineInstrBuilder PushMIB =
1961 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
1962 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
1963 PushMIB.addReg(
1964 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef);
1965 }
1966
1967 // Thumb1 can only tPUSH low regs, so we copy the high regs to the low
1968 // regs that we just saved and push the low regs again, taking care to
1969 // not clobber JumpReg. If JumpReg is one of the low registers, push first
1970 // the values of r9-r11, and then r8. That would leave them ordered in
1971 // memory, and allow us to later pop them with a single instructions.
1972 // FIXME: Could also use any of r0-r3 that are free (including in the
1973 // first PUSH above).
1974 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) {
1975 if (JumpReg == LoReg)
1976 continue;
1977 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
1978 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef)
1979 .add(predOps(ARMCC::AL));
1980 --HiReg;
1981 }
1982 MachineInstrBuilder PushMIB2 =
1983 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
1984 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
1985 if (Reg == JumpReg)
1986 continue;
1987 PushMIB2.addReg(Reg, RegState::Kill);
1988 }
1989
1990 // If we couldn't use a low register for temporary storage (because it was
1991 // the JumpReg), use r4 or r5, whichever is not JumpReg. It has already been
1992 // saved.
1993 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) {
1994 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4;
1995 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
1996 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef)
1997 .add(predOps(ARMCC::AL));
1998 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH))
1999 .add(predOps(ARMCC::AL))
2000 .addReg(LoReg, RegState::Kill);
2001 }
2002 } else { // push Lo and Hi registers with a single instruction
2003 MachineInstrBuilder PushMIB =
2004 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
2005 .addReg(ARM::SP)
2006 .add(predOps(ARMCC::AL));
2007 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
2008 PushMIB.addReg(
2009 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef);
2010 }
2011 }
2012 }
2013
CMSEPopCalleeSaves(const TargetInstrInfo & TII,MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,int JumpReg,bool Thumb1Only)2014 static void CMSEPopCalleeSaves(const TargetInstrInfo &TII,
2015 MachineBasicBlock &MBB,
2016 MachineBasicBlock::iterator MBBI, int JumpReg,
2017 bool Thumb1Only) {
2018 const DebugLoc &DL = MBBI->getDebugLoc();
2019 if (Thumb1Only) {
2020 MachineInstrBuilder PopMIB =
2021 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2022 for (int R = 0; R < 4; ++R) {
2023 PopMIB.addReg(ARM::R4 + R, RegState::Define);
2024 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R)
2025 .addReg(ARM::R4 + R, RegState::Kill)
2026 .add(predOps(ARMCC::AL));
2027 }
2028 MachineInstrBuilder PopMIB2 =
2029 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2030 for (int R = 0; R < 4; ++R)
2031 PopMIB2.addReg(ARM::R4 + R, RegState::Define);
2032 } else { // pop Lo and Hi registers with a single instruction
2033 MachineInstrBuilder PopMIB =
2034 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP)
2035 .addReg(ARM::SP)
2036 .add(predOps(ARMCC::AL));
2037 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg)
2038 PopMIB.addReg(Reg, RegState::Define);
2039 }
2040 }
2041
ExpandMI(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,MachineBasicBlock::iterator & NextMBBI)2042 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
2043 MachineBasicBlock::iterator MBBI,
2044 MachineBasicBlock::iterator &NextMBBI) {
2045 MachineInstr &MI = *MBBI;
2046 unsigned Opcode = MI.getOpcode();
2047 switch (Opcode) {
2048 default:
2049 return false;
2050
2051 case ARM::VBSPd:
2052 case ARM::VBSPq: {
2053 Register DstReg = MI.getOperand(0).getReg();
2054 if (DstReg == MI.getOperand(3).getReg()) {
2055 // Expand to VBIT
2056 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
2057 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2058 .add(MI.getOperand(0))
2059 .add(MI.getOperand(3))
2060 .add(MI.getOperand(2))
2061 .add(MI.getOperand(1))
2062 .addImm(MI.getOperand(4).getImm())
2063 .add(MI.getOperand(5));
2064 } else if (DstReg == MI.getOperand(2).getReg()) {
2065 // Expand to VBIF
2066 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
2067 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2068 .add(MI.getOperand(0))
2069 .add(MI.getOperand(2))
2070 .add(MI.getOperand(3))
2071 .add(MI.getOperand(1))
2072 .addImm(MI.getOperand(4).getImm())
2073 .add(MI.getOperand(5));
2074 } else {
2075 // Expand to VBSL
2076 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
2077 if (DstReg == MI.getOperand(1).getReg()) {
2078 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2079 .add(MI.getOperand(0))
2080 .add(MI.getOperand(1))
2081 .add(MI.getOperand(2))
2082 .add(MI.getOperand(3))
2083 .addImm(MI.getOperand(4).getImm())
2084 .add(MI.getOperand(5));
2085 } else {
2086 // Use move to satisfy constraints
2087 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
2088 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc))
2089 .addReg(DstReg,
2090 RegState::Define |
2091 getRenamableRegState(MI.getOperand(0).isRenamable()))
2092 .add(MI.getOperand(1))
2093 .add(MI.getOperand(1))
2094 .addImm(MI.getOperand(4).getImm())
2095 .add(MI.getOperand(5));
2096 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2097 .add(MI.getOperand(0))
2098 .addReg(DstReg,
2099 RegState::Kill |
2100 getRenamableRegState(MI.getOperand(0).isRenamable()))
2101 .add(MI.getOperand(2))
2102 .add(MI.getOperand(3))
2103 .addImm(MI.getOperand(4).getImm())
2104 .add(MI.getOperand(5));
2105 }
2106 }
2107 MI.eraseFromParent();
2108 return true;
2109 }
2110
2111 case ARM::TCRETURNdi:
2112 case ARM::TCRETURNri: {
2113 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
2114 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2115 MBBI--;
2116 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2117 MBBI--;
2118 assert(MBBI->isReturn() &&
2119 "Can only insert epilog into returning blocks");
2120 unsigned RetOpcode = MBBI->getOpcode();
2121 DebugLoc dl = MBBI->getDebugLoc();
2122 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
2123 MBB.getParent()->getSubtarget().getInstrInfo());
2124
2125 // Tail call return: adjust the stack pointer and jump to callee.
2126 MBBI = MBB.getLastNonDebugInstr();
2127 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2128 MBBI--;
2129 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2130 MBBI--;
2131 MachineOperand &JumpTarget = MBBI->getOperand(0);
2132
2133 // Jump to label or value in register.
2134 if (RetOpcode == ARM::TCRETURNdi) {
2135 MachineFunction *MF = MBB.getParent();
2136 bool NeedsWinCFI = MF->getTarget().getMCAsmInfo()->usesWindowsCFI() &&
2137 MF->getFunction().needsUnwindTableEntry();
2138 unsigned TCOpcode =
2139 STI->isThumb()
2140 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd
2141 : ARM::tTAILJMPdND)
2142 : ARM::TAILJMPd;
2143 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
2144 if (JumpTarget.isGlobal())
2145 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
2146 JumpTarget.getTargetFlags());
2147 else {
2148 assert(JumpTarget.isSymbol());
2149 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
2150 JumpTarget.getTargetFlags());
2151 }
2152
2153 // Add the default predicate in Thumb mode.
2154 if (STI->isThumb())
2155 MIB.add(predOps(ARMCC::AL));
2156 } else if (RetOpcode == ARM::TCRETURNri) {
2157 unsigned Opcode =
2158 STI->isThumb() ? ARM::tTAILJMPr
2159 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
2160 BuildMI(MBB, MBBI, dl,
2161 TII.get(Opcode))
2162 .addReg(JumpTarget.getReg(), RegState::Kill);
2163 }
2164
2165 auto NewMI = std::prev(MBBI);
2166 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
2167 NewMI->addOperand(MBBI->getOperand(i));
2168
2169
2170 // Update call site info and delete the pseudo instruction TCRETURN.
2171 if (MI.isCandidateForCallSiteEntry())
2172 MI.getMF()->moveCallSiteInfo(&MI, &*NewMI);
2173 MBB.erase(MBBI);
2174
2175 MBBI = NewMI;
2176 return true;
2177 }
2178 case ARM::tBXNS_RET: {
2179 // For v8.0-M.Main we need to authenticate LR before clearing FPRs, which
2180 // uses R12 as a scratch register.
2181 if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress())
2182 BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT));
2183
2184 MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI);
2185
2186 if (STI->hasV8_1MMainlineOps()) {
2187 // Restore the non-secure floating point context.
2188 BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
2189 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP)
2190 .addReg(ARM::SP)
2191 .addImm(4)
2192 .add(predOps(ARMCC::AL));
2193
2194 if (AFI->shouldSignReturnAddress())
2195 BuildMI(AfterBB, AfterBB.end(), DebugLoc(), TII->get(ARM::t2AUT));
2196 }
2197
2198 // Clear all GPR that are not a use of the return instruction.
2199 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) {
2200 return !Op.isReg() || Op.getReg() != ARM::R12;
2201 }));
2202 SmallVector<unsigned, 5> ClearRegs;
2203 determineGPRegsToClear(
2204 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2205 CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs,
2206 ARM::LR);
2207
2208 MachineInstrBuilder NewMI =
2209 BuildMI(AfterBB, AfterBB.end(), MBBI->getDebugLoc(),
2210 TII->get(ARM::tBXNS))
2211 .addReg(ARM::LR)
2212 .add(predOps(ARMCC::AL));
2213 for (const MachineOperand &Op : MI.operands())
2214 NewMI->addOperand(Op);
2215 MI.eraseFromParent();
2216 return true;
2217 }
2218 case ARM::tBLXNS_CALL: {
2219 DebugLoc DL = MBBI->getDebugLoc();
2220 Register JumpReg = MBBI->getOperand(0).getReg();
2221
2222 // Figure out which registers are live at the point immediately before the
2223 // call. When we indiscriminately push a set of registers, the live
2224 // registers are added as ordinary use operands, whereas dead registers
2225 // are "undef".
2226 LivePhysRegs LiveRegs(*TRI);
2227 LiveRegs.addLiveOuts(MBB);
2228 for (const MachineInstr &MI : make_range(MBB.rbegin(), MBBI.getReverse()))
2229 LiveRegs.stepBackward(MI);
2230 LiveRegs.stepBackward(*MBBI);
2231
2232 CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs,
2233 AFI->isThumb1OnlyFunction());
2234
2235 SmallVector<unsigned, 16> ClearRegs;
2236 determineGPRegsToClear(*MBBI,
2237 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
2238 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9,
2239 ARM::R10, ARM::R11, ARM::R12},
2240 ClearRegs);
2241 auto OriginalClearRegs = ClearRegs;
2242
2243 // Get the first cleared register as a scratch (to use later with tBIC).
2244 // We need to use the first so we can ensure it is a low register.
2245 unsigned ScratchReg = ClearRegs.front();
2246
2247 // Clear LSB of JumpReg
2248 if (AFI->isThumb2Function()) {
2249 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg)
2250 .addReg(JumpReg)
2251 .addImm(1)
2252 .add(predOps(ARMCC::AL))
2253 .add(condCodeOp());
2254 } else {
2255 // We need to use an extra register to cope with 8M Baseline,
2256 // since we have saved all of the registers we are ok to trash a non
2257 // argument register here.
2258 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg)
2259 .add(condCodeOp())
2260 .addImm(1)
2261 .add(predOps(ARMCC::AL));
2262 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg)
2263 .addReg(ARM::CPSR, RegState::Define)
2264 .addReg(JumpReg)
2265 .addReg(ScratchReg)
2266 .add(predOps(ARMCC::AL));
2267 }
2268
2269 CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs,
2270 ClearRegs); // save+clear FP regs with ClearRegs
2271 CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg);
2272
2273 const MachineInstrBuilder NewCall =
2274 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr))
2275 .add(predOps(ARMCC::AL))
2276 .addReg(JumpReg, RegState::Kill);
2277
2278 for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
2279 NewCall->addOperand(MO);
2280 if (MI.isCandidateForCallSiteEntry())
2281 MI.getMF()->moveCallSiteInfo(&MI, NewCall.getInstr());
2282
2283 CMSERestoreFPRegs(MBB, MBBI, DL, OriginalClearRegs); // restore FP registers
2284
2285 CMSEPopCalleeSaves(*TII, MBB, MBBI, JumpReg, AFI->isThumb1OnlyFunction());
2286
2287 MI.eraseFromParent();
2288 return true;
2289 }
2290 case ARM::VMOVHcc:
2291 case ARM::VMOVScc:
2292 case ARM::VMOVDcc: {
2293 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
2294 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
2295 MI.getOperand(1).getReg())
2296 .add(MI.getOperand(2))
2297 .addImm(MI.getOperand(3).getImm()) // 'pred'
2298 .add(MI.getOperand(4))
2299 .add(makeImplicit(MI.getOperand(1)));
2300
2301 MI.eraseFromParent();
2302 return true;
2303 }
2304 case ARM::t2MOVCCr:
2305 case ARM::MOVCCr: {
2306 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
2307 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2308 MI.getOperand(1).getReg())
2309 .add(MI.getOperand(2))
2310 .addImm(MI.getOperand(3).getImm()) // 'pred'
2311 .add(MI.getOperand(4))
2312 .add(condCodeOp()) // 's' bit
2313 .add(makeImplicit(MI.getOperand(1)));
2314
2315 MI.eraseFromParent();
2316 return true;
2317 }
2318 case ARM::MOVCCsi: {
2319 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2320 (MI.getOperand(1).getReg()))
2321 .add(MI.getOperand(2))
2322 .addImm(MI.getOperand(3).getImm())
2323 .addImm(MI.getOperand(4).getImm()) // 'pred'
2324 .add(MI.getOperand(5))
2325 .add(condCodeOp()) // 's' bit
2326 .add(makeImplicit(MI.getOperand(1)));
2327
2328 MI.eraseFromParent();
2329 return true;
2330 }
2331 case ARM::MOVCCsr: {
2332 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
2333 (MI.getOperand(1).getReg()))
2334 .add(MI.getOperand(2))
2335 .add(MI.getOperand(3))
2336 .addImm(MI.getOperand(4).getImm())
2337 .addImm(MI.getOperand(5).getImm()) // 'pred'
2338 .add(MI.getOperand(6))
2339 .add(condCodeOp()) // 's' bit
2340 .add(makeImplicit(MI.getOperand(1)));
2341
2342 MI.eraseFromParent();
2343 return true;
2344 }
2345 case ARM::t2MOVCCi16:
2346 case ARM::MOVCCi16: {
2347 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
2348 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
2349 MI.getOperand(1).getReg())
2350 .addImm(MI.getOperand(2).getImm())
2351 .addImm(MI.getOperand(3).getImm()) // 'pred'
2352 .add(MI.getOperand(4))
2353 .add(makeImplicit(MI.getOperand(1)));
2354 MI.eraseFromParent();
2355 return true;
2356 }
2357 case ARM::t2MOVCCi:
2358 case ARM::MOVCCi: {
2359 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
2360 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2361 MI.getOperand(1).getReg())
2362 .addImm(MI.getOperand(2).getImm())
2363 .addImm(MI.getOperand(3).getImm()) // 'pred'
2364 .add(MI.getOperand(4))
2365 .add(condCodeOp()) // 's' bit
2366 .add(makeImplicit(MI.getOperand(1)));
2367
2368 MI.eraseFromParent();
2369 return true;
2370 }
2371 case ARM::t2MVNCCi:
2372 case ARM::MVNCCi: {
2373 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
2374 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2375 MI.getOperand(1).getReg())
2376 .addImm(MI.getOperand(2).getImm())
2377 .addImm(MI.getOperand(3).getImm()) // 'pred'
2378 .add(MI.getOperand(4))
2379 .add(condCodeOp()) // 's' bit
2380 .add(makeImplicit(MI.getOperand(1)));
2381
2382 MI.eraseFromParent();
2383 return true;
2384 }
2385 case ARM::t2MOVCClsl:
2386 case ARM::t2MOVCClsr:
2387 case ARM::t2MOVCCasr:
2388 case ARM::t2MOVCCror: {
2389 unsigned NewOpc;
2390 switch (Opcode) {
2391 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
2392 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
2393 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
2394 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
2395 default: llvm_unreachable("unexpeced conditional move");
2396 }
2397 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
2398 MI.getOperand(1).getReg())
2399 .add(MI.getOperand(2))
2400 .addImm(MI.getOperand(3).getImm())
2401 .addImm(MI.getOperand(4).getImm()) // 'pred'
2402 .add(MI.getOperand(5))
2403 .add(condCodeOp()) // 's' bit
2404 .add(makeImplicit(MI.getOperand(1)));
2405 MI.eraseFromParent();
2406 return true;
2407 }
2408 case ARM::Int_eh_sjlj_dispatchsetup: {
2409 MachineFunction &MF = *MI.getParent()->getParent();
2410 const ARMBaseInstrInfo *AII =
2411 static_cast<const ARMBaseInstrInfo*>(TII);
2412 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
2413 // For functions using a base pointer, we rematerialize it (via the frame
2414 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
2415 // for us. Otherwise, expand to nothing.
2416 if (RI.hasBasePointer(MF)) {
2417 int32_t NumBytes = AFI->getFramePtrSpillOffset();
2418 Register FramePtr = RI.getFrameRegister(MF);
2419 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
2420 "base pointer without frame pointer?");
2421
2422 if (AFI->isThumb2Function()) {
2423 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2424 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
2425 } else if (AFI->isThumbFunction()) {
2426 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2427 FramePtr, -NumBytes, *TII, RI);
2428 } else {
2429 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2430 FramePtr, -NumBytes, ARMCC::AL, 0,
2431 *TII);
2432 }
2433 // If there's dynamic realignment, adjust for it.
2434 if (RI.hasStackRealignment(MF)) {
2435 MachineFrameInfo &MFI = MF.getFrameInfo();
2436 Align MaxAlign = MFI.getMaxAlign();
2437 assert (!AFI->isThumb1OnlyFunction());
2438 // Emit bic r6, r6, MaxAlign
2439 assert(MaxAlign <= Align(256) &&
2440 "The BIC instruction cannot encode "
2441 "immediates larger than 256 with all lower "
2442 "bits set.");
2443 unsigned bicOpc = AFI->isThumbFunction() ?
2444 ARM::t2BICri : ARM::BICri;
2445 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
2446 .addReg(ARM::R6, RegState::Kill)
2447 .addImm(MaxAlign.value() - 1)
2448 .add(predOps(ARMCC::AL))
2449 .add(condCodeOp());
2450 }
2451 }
2452 MI.eraseFromParent();
2453 return true;
2454 }
2455
2456 case ARM::MOVsrl_flag:
2457 case ARM::MOVsra_flag: {
2458 // These are just fancy MOVs instructions.
2459 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2460 MI.getOperand(0).getReg())
2461 .add(MI.getOperand(1))
2462 .addImm(ARM_AM::getSORegOpc(
2463 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
2464 .add(predOps(ARMCC::AL))
2465 .addReg(ARM::CPSR, RegState::Define);
2466 MI.eraseFromParent();
2467 return true;
2468 }
2469 case ARM::RRX: {
2470 // This encodes as "MOVs Rd, Rm, rrx
2471 MachineInstrBuilder MIB =
2472 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2473 MI.getOperand(0).getReg())
2474 .add(MI.getOperand(1))
2475 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
2476 .add(predOps(ARMCC::AL))
2477 .add(condCodeOp());
2478 TransferImpOps(MI, MIB, MIB);
2479 MI.eraseFromParent();
2480 return true;
2481 }
2482 case ARM::tTPsoft:
2483 case ARM::TPsoft: {
2484 const bool Thumb = Opcode == ARM::tTPsoft;
2485
2486 MachineInstrBuilder MIB;
2487 MachineFunction *MF = MBB.getParent();
2488 if (STI->genLongCalls()) {
2489 MachineConstantPool *MCP = MF->getConstantPool();
2490 unsigned PCLabelID = AFI->createPICLabelUId();
2491 MachineConstantPoolValue *CPV =
2492 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(),
2493 "__aeabi_read_tp", PCLabelID, 0);
2494 Register Reg = MI.getOperand(0).getReg();
2495 MIB =
2496 BuildMI(MBB, MBBI, MI.getDebugLoc(),
2497 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
2498 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4)));
2499 if (!Thumb)
2500 MIB.addImm(0);
2501 MIB.add(predOps(ARMCC::AL));
2502
2503 MIB =
2504 BuildMI(MBB, MBBI, MI.getDebugLoc(),
2505 TII->get(Thumb ? gettBLXrOpcode(*MF) : getBLXOpcode(*MF)));
2506 if (Thumb)
2507 MIB.add(predOps(ARMCC::AL));
2508 MIB.addReg(Reg, RegState::Kill);
2509 } else {
2510 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2511 TII->get(Thumb ? ARM::tBL : ARM::BL));
2512 if (Thumb)
2513 MIB.add(predOps(ARMCC::AL));
2514 MIB.addExternalSymbol("__aeabi_read_tp", 0);
2515 }
2516
2517 MIB.cloneMemRefs(MI);
2518 TransferImpOps(MI, MIB, MIB);
2519 // Update the call site info.
2520 if (MI.isCandidateForCallSiteEntry())
2521 MF->moveCallSiteInfo(&MI, &*MIB);
2522 MI.eraseFromParent();
2523 return true;
2524 }
2525 case ARM::tLDRpci_pic:
2526 case ARM::t2LDRpci_pic: {
2527 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
2528 ? ARM::tLDRpci : ARM::t2LDRpci;
2529 Register DstReg = MI.getOperand(0).getReg();
2530 bool DstIsDead = MI.getOperand(0).isDead();
2531 MachineInstrBuilder MIB1 =
2532 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
2533 .add(MI.getOperand(1))
2534 .add(predOps(ARMCC::AL));
2535 MIB1.cloneMemRefs(MI);
2536 MachineInstrBuilder MIB2 =
2537 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
2538 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2539 .addReg(DstReg)
2540 .add(MI.getOperand(2));
2541 TransferImpOps(MI, MIB1, MIB2);
2542 MI.eraseFromParent();
2543 return true;
2544 }
2545
2546 case ARM::LDRLIT_ga_abs:
2547 case ARM::LDRLIT_ga_pcrel:
2548 case ARM::LDRLIT_ga_pcrel_ldr:
2549 case ARM::tLDRLIT_ga_abs:
2550 case ARM::t2LDRLIT_ga_pcrel:
2551 case ARM::tLDRLIT_ga_pcrel: {
2552 Register DstReg = MI.getOperand(0).getReg();
2553 bool DstIsDead = MI.getOperand(0).isDead();
2554 const MachineOperand &MO1 = MI.getOperand(1);
2555 auto Flags = MO1.getTargetFlags();
2556 const GlobalValue *GV = MO1.getGlobal();
2557 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
2558 Opcode != ARM::tLDRLIT_ga_abs &&
2559 Opcode != ARM::t2LDRLIT_ga_pcrel;
2560 bool IsPIC =
2561 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
2562 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
2563 if (Opcode == ARM::t2LDRLIT_ga_pcrel)
2564 LDRLITOpc = ARM::t2LDRpci;
2565 unsigned PICAddOpc =
2566 IsARM
2567 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2568 : ARM::tPICADD;
2569
2570 // We need a new const-pool entry to load from.
2571 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
2572 unsigned ARMPCLabelIndex = 0;
2573 MachineConstantPoolValue *CPV;
2574
2575 if (IsPIC) {
2576 unsigned PCAdj = IsARM ? 8 : 4;
2577 auto Modifier = (Flags & ARMII::MO_GOT)
2578 ? ARMCP::GOT_PREL
2579 : ARMCP::no_modifier;
2580 ARMPCLabelIndex = AFI->createPICLabelUId();
2581 CPV = ARMConstantPoolConstant::Create(
2582 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier,
2583 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL);
2584 } else
2585 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
2586
2587 MachineInstrBuilder MIB =
2588 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
2589 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4)));
2590 if (IsARM)
2591 MIB.addImm(0);
2592 MIB.add(predOps(ARMCC::AL));
2593
2594 if (IsPIC) {
2595 MachineInstrBuilder MIB =
2596 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
2597 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2598 .addReg(DstReg)
2599 .addImm(ARMPCLabelIndex);
2600
2601 if (IsARM)
2602 MIB.add(predOps(ARMCC::AL));
2603 }
2604
2605 MI.eraseFromParent();
2606 return true;
2607 }
2608 case ARM::MOV_ga_pcrel:
2609 case ARM::MOV_ga_pcrel_ldr:
2610 case ARM::t2MOV_ga_pcrel: {
2611 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
2612 unsigned LabelId = AFI->createPICLabelUId();
2613 Register DstReg = MI.getOperand(0).getReg();
2614 bool DstIsDead = MI.getOperand(0).isDead();
2615 const MachineOperand &MO1 = MI.getOperand(1);
2616 const GlobalValue *GV = MO1.getGlobal();
2617 unsigned TF = MO1.getTargetFlags();
2618 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
2619 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
2620 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
2621 unsigned LO16TF = TF | ARMII::MO_LO16;
2622 unsigned HI16TF = TF | ARMII::MO_HI16;
2623 unsigned PICAddOpc = isARM
2624 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2625 : ARM::tPICADD;
2626 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2627 TII->get(LO16Opc), DstReg)
2628 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
2629 .addImm(LabelId);
2630
2631 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
2632 .addReg(DstReg)
2633 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
2634 .addImm(LabelId);
2635
2636 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2637 TII->get(PICAddOpc))
2638 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2639 .addReg(DstReg).addImm(LabelId);
2640 if (isARM) {
2641 MIB3.add(predOps(ARMCC::AL));
2642 if (Opcode == ARM::MOV_ga_pcrel_ldr)
2643 MIB3.cloneMemRefs(MI);
2644 }
2645 TransferImpOps(MI, MIB1, MIB3);
2646 MI.eraseFromParent();
2647 return true;
2648 }
2649
2650 case ARM::MOVi32imm:
2651 case ARM::MOVCCi32imm:
2652 case ARM::t2MOVi32imm:
2653 case ARM::t2MOVCCi32imm:
2654 ExpandMOV32BitImm(MBB, MBBI);
2655 return true;
2656
2657 case ARM::SUBS_PC_LR: {
2658 MachineInstrBuilder MIB =
2659 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
2660 .addReg(ARM::LR)
2661 .add(MI.getOperand(0))
2662 .add(MI.getOperand(1))
2663 .add(MI.getOperand(2))
2664 .addReg(ARM::CPSR, RegState::Undef);
2665 TransferImpOps(MI, MIB, MIB);
2666 MI.eraseFromParent();
2667 return true;
2668 }
2669 case ARM::VLDMQIA: {
2670 unsigned NewOpc = ARM::VLDMDIA;
2671 MachineInstrBuilder MIB =
2672 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
2673 unsigned OpIdx = 0;
2674
2675 // Grab the Q register destination.
2676 bool DstIsDead = MI.getOperand(OpIdx).isDead();
2677 Register DstReg = MI.getOperand(OpIdx++).getReg();
2678
2679 // Copy the source register.
2680 MIB.add(MI.getOperand(OpIdx++));
2681
2682 // Copy the predicate operands.
2683 MIB.add(MI.getOperand(OpIdx++));
2684 MIB.add(MI.getOperand(OpIdx++));
2685
2686 // Add the destination operands (D subregs).
2687 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
2688 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
2689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
2690 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
2691
2692 // Add an implicit def for the super-register.
2693 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
2694 TransferImpOps(MI, MIB, MIB);
2695 MIB.cloneMemRefs(MI);
2696 MI.eraseFromParent();
2697 return true;
2698 }
2699
2700 case ARM::VSTMQIA: {
2701 unsigned NewOpc = ARM::VSTMDIA;
2702 MachineInstrBuilder MIB =
2703 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
2704 unsigned OpIdx = 0;
2705
2706 // Grab the Q register source.
2707 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
2708 Register SrcReg = MI.getOperand(OpIdx++).getReg();
2709
2710 // Copy the destination register.
2711 MachineOperand Dst(MI.getOperand(OpIdx++));
2712 MIB.add(Dst);
2713
2714 // Copy the predicate operands.
2715 MIB.add(MI.getOperand(OpIdx++));
2716 MIB.add(MI.getOperand(OpIdx++));
2717
2718 // Add the source operands (D subregs).
2719 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
2720 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
2721 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
2722 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
2723
2724 if (SrcIsKill) // Add an implicit kill for the Q register.
2725 MIB->addRegisterKilled(SrcReg, TRI, true);
2726
2727 TransferImpOps(MI, MIB, MIB);
2728 MIB.cloneMemRefs(MI);
2729 MI.eraseFromParent();
2730 return true;
2731 }
2732
2733 case ARM::VLD2q8Pseudo:
2734 case ARM::VLD2q16Pseudo:
2735 case ARM::VLD2q32Pseudo:
2736 case ARM::VLD2q8PseudoWB_fixed:
2737 case ARM::VLD2q16PseudoWB_fixed:
2738 case ARM::VLD2q32PseudoWB_fixed:
2739 case ARM::VLD2q8PseudoWB_register:
2740 case ARM::VLD2q16PseudoWB_register:
2741 case ARM::VLD2q32PseudoWB_register:
2742 case ARM::VLD3d8Pseudo:
2743 case ARM::VLD3d16Pseudo:
2744 case ARM::VLD3d32Pseudo:
2745 case ARM::VLD1d8TPseudo:
2746 case ARM::VLD1d8TPseudoWB_fixed:
2747 case ARM::VLD1d8TPseudoWB_register:
2748 case ARM::VLD1d16TPseudo:
2749 case ARM::VLD1d16TPseudoWB_fixed:
2750 case ARM::VLD1d16TPseudoWB_register:
2751 case ARM::VLD1d32TPseudo:
2752 case ARM::VLD1d32TPseudoWB_fixed:
2753 case ARM::VLD1d32TPseudoWB_register:
2754 case ARM::VLD1d64TPseudo:
2755 case ARM::VLD1d64TPseudoWB_fixed:
2756 case ARM::VLD1d64TPseudoWB_register:
2757 case ARM::VLD3d8Pseudo_UPD:
2758 case ARM::VLD3d16Pseudo_UPD:
2759 case ARM::VLD3d32Pseudo_UPD:
2760 case ARM::VLD3q8Pseudo_UPD:
2761 case ARM::VLD3q16Pseudo_UPD:
2762 case ARM::VLD3q32Pseudo_UPD:
2763 case ARM::VLD3q8oddPseudo:
2764 case ARM::VLD3q16oddPseudo:
2765 case ARM::VLD3q32oddPseudo:
2766 case ARM::VLD3q8oddPseudo_UPD:
2767 case ARM::VLD3q16oddPseudo_UPD:
2768 case ARM::VLD3q32oddPseudo_UPD:
2769 case ARM::VLD4d8Pseudo:
2770 case ARM::VLD4d16Pseudo:
2771 case ARM::VLD4d32Pseudo:
2772 case ARM::VLD1d8QPseudo:
2773 case ARM::VLD1d8QPseudoWB_fixed:
2774 case ARM::VLD1d8QPseudoWB_register:
2775 case ARM::VLD1d16QPseudo:
2776 case ARM::VLD1d16QPseudoWB_fixed:
2777 case ARM::VLD1d16QPseudoWB_register:
2778 case ARM::VLD1d32QPseudo:
2779 case ARM::VLD1d32QPseudoWB_fixed:
2780 case ARM::VLD1d32QPseudoWB_register:
2781 case ARM::VLD1d64QPseudo:
2782 case ARM::VLD1d64QPseudoWB_fixed:
2783 case ARM::VLD1d64QPseudoWB_register:
2784 case ARM::VLD1q8HighQPseudo:
2785 case ARM::VLD1q8HighQPseudo_UPD:
2786 case ARM::VLD1q8LowQPseudo_UPD:
2787 case ARM::VLD1q8HighTPseudo:
2788 case ARM::VLD1q8HighTPseudo_UPD:
2789 case ARM::VLD1q8LowTPseudo_UPD:
2790 case ARM::VLD1q16HighQPseudo:
2791 case ARM::VLD1q16HighQPseudo_UPD:
2792 case ARM::VLD1q16LowQPseudo_UPD:
2793 case ARM::VLD1q16HighTPseudo:
2794 case ARM::VLD1q16HighTPseudo_UPD:
2795 case ARM::VLD1q16LowTPseudo_UPD:
2796 case ARM::VLD1q32HighQPseudo:
2797 case ARM::VLD1q32HighQPseudo_UPD:
2798 case ARM::VLD1q32LowQPseudo_UPD:
2799 case ARM::VLD1q32HighTPseudo:
2800 case ARM::VLD1q32HighTPseudo_UPD:
2801 case ARM::VLD1q32LowTPseudo_UPD:
2802 case ARM::VLD1q64HighQPseudo:
2803 case ARM::VLD1q64HighQPseudo_UPD:
2804 case ARM::VLD1q64LowQPseudo_UPD:
2805 case ARM::VLD1q64HighTPseudo:
2806 case ARM::VLD1q64HighTPseudo_UPD:
2807 case ARM::VLD1q64LowTPseudo_UPD:
2808 case ARM::VLD4d8Pseudo_UPD:
2809 case ARM::VLD4d16Pseudo_UPD:
2810 case ARM::VLD4d32Pseudo_UPD:
2811 case ARM::VLD4q8Pseudo_UPD:
2812 case ARM::VLD4q16Pseudo_UPD:
2813 case ARM::VLD4q32Pseudo_UPD:
2814 case ARM::VLD4q8oddPseudo:
2815 case ARM::VLD4q16oddPseudo:
2816 case ARM::VLD4q32oddPseudo:
2817 case ARM::VLD4q8oddPseudo_UPD:
2818 case ARM::VLD4q16oddPseudo_UPD:
2819 case ARM::VLD4q32oddPseudo_UPD:
2820 case ARM::VLD3DUPd8Pseudo:
2821 case ARM::VLD3DUPd16Pseudo:
2822 case ARM::VLD3DUPd32Pseudo:
2823 case ARM::VLD3DUPd8Pseudo_UPD:
2824 case ARM::VLD3DUPd16Pseudo_UPD:
2825 case ARM::VLD3DUPd32Pseudo_UPD:
2826 case ARM::VLD4DUPd8Pseudo:
2827 case ARM::VLD4DUPd16Pseudo:
2828 case ARM::VLD4DUPd32Pseudo:
2829 case ARM::VLD4DUPd8Pseudo_UPD:
2830 case ARM::VLD4DUPd16Pseudo_UPD:
2831 case ARM::VLD4DUPd32Pseudo_UPD:
2832 case ARM::VLD2DUPq8EvenPseudo:
2833 case ARM::VLD2DUPq8OddPseudo:
2834 case ARM::VLD2DUPq16EvenPseudo:
2835 case ARM::VLD2DUPq16OddPseudo:
2836 case ARM::VLD2DUPq32EvenPseudo:
2837 case ARM::VLD2DUPq32OddPseudo:
2838 case ARM::VLD2DUPq8OddPseudoWB_fixed:
2839 case ARM::VLD2DUPq8OddPseudoWB_register:
2840 case ARM::VLD2DUPq16OddPseudoWB_fixed:
2841 case ARM::VLD2DUPq16OddPseudoWB_register:
2842 case ARM::VLD2DUPq32OddPseudoWB_fixed:
2843 case ARM::VLD2DUPq32OddPseudoWB_register:
2844 case ARM::VLD3DUPq8EvenPseudo:
2845 case ARM::VLD3DUPq8OddPseudo:
2846 case ARM::VLD3DUPq16EvenPseudo:
2847 case ARM::VLD3DUPq16OddPseudo:
2848 case ARM::VLD3DUPq32EvenPseudo:
2849 case ARM::VLD3DUPq32OddPseudo:
2850 case ARM::VLD3DUPq8OddPseudo_UPD:
2851 case ARM::VLD3DUPq16OddPseudo_UPD:
2852 case ARM::VLD3DUPq32OddPseudo_UPD:
2853 case ARM::VLD4DUPq8EvenPseudo:
2854 case ARM::VLD4DUPq8OddPseudo:
2855 case ARM::VLD4DUPq16EvenPseudo:
2856 case ARM::VLD4DUPq16OddPseudo:
2857 case ARM::VLD4DUPq32EvenPseudo:
2858 case ARM::VLD4DUPq32OddPseudo:
2859 case ARM::VLD4DUPq8OddPseudo_UPD:
2860 case ARM::VLD4DUPq16OddPseudo_UPD:
2861 case ARM::VLD4DUPq32OddPseudo_UPD:
2862 ExpandVLD(MBBI);
2863 return true;
2864
2865 case ARM::VST2q8Pseudo:
2866 case ARM::VST2q16Pseudo:
2867 case ARM::VST2q32Pseudo:
2868 case ARM::VST2q8PseudoWB_fixed:
2869 case ARM::VST2q16PseudoWB_fixed:
2870 case ARM::VST2q32PseudoWB_fixed:
2871 case ARM::VST2q8PseudoWB_register:
2872 case ARM::VST2q16PseudoWB_register:
2873 case ARM::VST2q32PseudoWB_register:
2874 case ARM::VST3d8Pseudo:
2875 case ARM::VST3d16Pseudo:
2876 case ARM::VST3d32Pseudo:
2877 case ARM::VST1d8TPseudo:
2878 case ARM::VST1d8TPseudoWB_fixed:
2879 case ARM::VST1d8TPseudoWB_register:
2880 case ARM::VST1d16TPseudo:
2881 case ARM::VST1d16TPseudoWB_fixed:
2882 case ARM::VST1d16TPseudoWB_register:
2883 case ARM::VST1d32TPseudo:
2884 case ARM::VST1d32TPseudoWB_fixed:
2885 case ARM::VST1d32TPseudoWB_register:
2886 case ARM::VST1d64TPseudo:
2887 case ARM::VST1d64TPseudoWB_fixed:
2888 case ARM::VST1d64TPseudoWB_register:
2889 case ARM::VST3d8Pseudo_UPD:
2890 case ARM::VST3d16Pseudo_UPD:
2891 case ARM::VST3d32Pseudo_UPD:
2892 case ARM::VST3q8Pseudo_UPD:
2893 case ARM::VST3q16Pseudo_UPD:
2894 case ARM::VST3q32Pseudo_UPD:
2895 case ARM::VST3q8oddPseudo:
2896 case ARM::VST3q16oddPseudo:
2897 case ARM::VST3q32oddPseudo:
2898 case ARM::VST3q8oddPseudo_UPD:
2899 case ARM::VST3q16oddPseudo_UPD:
2900 case ARM::VST3q32oddPseudo_UPD:
2901 case ARM::VST4d8Pseudo:
2902 case ARM::VST4d16Pseudo:
2903 case ARM::VST4d32Pseudo:
2904 case ARM::VST1d8QPseudo:
2905 case ARM::VST1d8QPseudoWB_fixed:
2906 case ARM::VST1d8QPseudoWB_register:
2907 case ARM::VST1d16QPseudo:
2908 case ARM::VST1d16QPseudoWB_fixed:
2909 case ARM::VST1d16QPseudoWB_register:
2910 case ARM::VST1d32QPseudo:
2911 case ARM::VST1d32QPseudoWB_fixed:
2912 case ARM::VST1d32QPseudoWB_register:
2913 case ARM::VST1d64QPseudo:
2914 case ARM::VST1d64QPseudoWB_fixed:
2915 case ARM::VST1d64QPseudoWB_register:
2916 case ARM::VST4d8Pseudo_UPD:
2917 case ARM::VST4d16Pseudo_UPD:
2918 case ARM::VST4d32Pseudo_UPD:
2919 case ARM::VST1q8HighQPseudo:
2920 case ARM::VST1q8LowQPseudo_UPD:
2921 case ARM::VST1q8HighTPseudo:
2922 case ARM::VST1q8LowTPseudo_UPD:
2923 case ARM::VST1q16HighQPseudo:
2924 case ARM::VST1q16LowQPseudo_UPD:
2925 case ARM::VST1q16HighTPseudo:
2926 case ARM::VST1q16LowTPseudo_UPD:
2927 case ARM::VST1q32HighQPseudo:
2928 case ARM::VST1q32LowQPseudo_UPD:
2929 case ARM::VST1q32HighTPseudo:
2930 case ARM::VST1q32LowTPseudo_UPD:
2931 case ARM::VST1q64HighQPseudo:
2932 case ARM::VST1q64LowQPseudo_UPD:
2933 case ARM::VST1q64HighTPseudo:
2934 case ARM::VST1q64LowTPseudo_UPD:
2935 case ARM::VST1q8HighTPseudo_UPD:
2936 case ARM::VST1q16HighTPseudo_UPD:
2937 case ARM::VST1q32HighTPseudo_UPD:
2938 case ARM::VST1q64HighTPseudo_UPD:
2939 case ARM::VST1q8HighQPseudo_UPD:
2940 case ARM::VST1q16HighQPseudo_UPD:
2941 case ARM::VST1q32HighQPseudo_UPD:
2942 case ARM::VST1q64HighQPseudo_UPD:
2943 case ARM::VST4q8Pseudo_UPD:
2944 case ARM::VST4q16Pseudo_UPD:
2945 case ARM::VST4q32Pseudo_UPD:
2946 case ARM::VST4q8oddPseudo:
2947 case ARM::VST4q16oddPseudo:
2948 case ARM::VST4q32oddPseudo:
2949 case ARM::VST4q8oddPseudo_UPD:
2950 case ARM::VST4q16oddPseudo_UPD:
2951 case ARM::VST4q32oddPseudo_UPD:
2952 ExpandVST(MBBI);
2953 return true;
2954
2955 case ARM::VLD1LNq8Pseudo:
2956 case ARM::VLD1LNq16Pseudo:
2957 case ARM::VLD1LNq32Pseudo:
2958 case ARM::VLD1LNq8Pseudo_UPD:
2959 case ARM::VLD1LNq16Pseudo_UPD:
2960 case ARM::VLD1LNq32Pseudo_UPD:
2961 case ARM::VLD2LNd8Pseudo:
2962 case ARM::VLD2LNd16Pseudo:
2963 case ARM::VLD2LNd32Pseudo:
2964 case ARM::VLD2LNq16Pseudo:
2965 case ARM::VLD2LNq32Pseudo:
2966 case ARM::VLD2LNd8Pseudo_UPD:
2967 case ARM::VLD2LNd16Pseudo_UPD:
2968 case ARM::VLD2LNd32Pseudo_UPD:
2969 case ARM::VLD2LNq16Pseudo_UPD:
2970 case ARM::VLD2LNq32Pseudo_UPD:
2971 case ARM::VLD3LNd8Pseudo:
2972 case ARM::VLD3LNd16Pseudo:
2973 case ARM::VLD3LNd32Pseudo:
2974 case ARM::VLD3LNq16Pseudo:
2975 case ARM::VLD3LNq32Pseudo:
2976 case ARM::VLD3LNd8Pseudo_UPD:
2977 case ARM::VLD3LNd16Pseudo_UPD:
2978 case ARM::VLD3LNd32Pseudo_UPD:
2979 case ARM::VLD3LNq16Pseudo_UPD:
2980 case ARM::VLD3LNq32Pseudo_UPD:
2981 case ARM::VLD4LNd8Pseudo:
2982 case ARM::VLD4LNd16Pseudo:
2983 case ARM::VLD4LNd32Pseudo:
2984 case ARM::VLD4LNq16Pseudo:
2985 case ARM::VLD4LNq32Pseudo:
2986 case ARM::VLD4LNd8Pseudo_UPD:
2987 case ARM::VLD4LNd16Pseudo_UPD:
2988 case ARM::VLD4LNd32Pseudo_UPD:
2989 case ARM::VLD4LNq16Pseudo_UPD:
2990 case ARM::VLD4LNq32Pseudo_UPD:
2991 case ARM::VST1LNq8Pseudo:
2992 case ARM::VST1LNq16Pseudo:
2993 case ARM::VST1LNq32Pseudo:
2994 case ARM::VST1LNq8Pseudo_UPD:
2995 case ARM::VST1LNq16Pseudo_UPD:
2996 case ARM::VST1LNq32Pseudo_UPD:
2997 case ARM::VST2LNd8Pseudo:
2998 case ARM::VST2LNd16Pseudo:
2999 case ARM::VST2LNd32Pseudo:
3000 case ARM::VST2LNq16Pseudo:
3001 case ARM::VST2LNq32Pseudo:
3002 case ARM::VST2LNd8Pseudo_UPD:
3003 case ARM::VST2LNd16Pseudo_UPD:
3004 case ARM::VST2LNd32Pseudo_UPD:
3005 case ARM::VST2LNq16Pseudo_UPD:
3006 case ARM::VST2LNq32Pseudo_UPD:
3007 case ARM::VST3LNd8Pseudo:
3008 case ARM::VST3LNd16Pseudo:
3009 case ARM::VST3LNd32Pseudo:
3010 case ARM::VST3LNq16Pseudo:
3011 case ARM::VST3LNq32Pseudo:
3012 case ARM::VST3LNd8Pseudo_UPD:
3013 case ARM::VST3LNd16Pseudo_UPD:
3014 case ARM::VST3LNd32Pseudo_UPD:
3015 case ARM::VST3LNq16Pseudo_UPD:
3016 case ARM::VST3LNq32Pseudo_UPD:
3017 case ARM::VST4LNd8Pseudo:
3018 case ARM::VST4LNd16Pseudo:
3019 case ARM::VST4LNd32Pseudo:
3020 case ARM::VST4LNq16Pseudo:
3021 case ARM::VST4LNq32Pseudo:
3022 case ARM::VST4LNd8Pseudo_UPD:
3023 case ARM::VST4LNd16Pseudo_UPD:
3024 case ARM::VST4LNd32Pseudo_UPD:
3025 case ARM::VST4LNq16Pseudo_UPD:
3026 case ARM::VST4LNq32Pseudo_UPD:
3027 ExpandLaneOp(MBBI);
3028 return true;
3029
3030 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
3031 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
3032 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
3033 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
3034
3035 case ARM::MQQPRLoad:
3036 case ARM::MQQPRStore:
3037 case ARM::MQQQQPRLoad:
3038 case ARM::MQQQQPRStore:
3039 ExpandMQQPRLoadStore(MBBI);
3040 return true;
3041
3042 case ARM::tCMP_SWAP_8:
3043 assert(STI->isThumb());
3044 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
3045 NextMBBI);
3046 case ARM::tCMP_SWAP_16:
3047 assert(STI->isThumb());
3048 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
3049 NextMBBI);
3050 case ARM::tCMP_SWAP_32:
3051 assert(STI->isThumb());
3052 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI);
3053
3054 case ARM::CMP_SWAP_8:
3055 assert(!STI->isThumb());
3056 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB,
3057 NextMBBI);
3058 case ARM::CMP_SWAP_16:
3059 assert(!STI->isThumb());
3060 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH,
3061 NextMBBI);
3062 case ARM::CMP_SWAP_32:
3063 assert(!STI->isThumb());
3064 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
3065
3066 case ARM::CMP_SWAP_64:
3067 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
3068
3069 case ARM::tBL_PUSHLR:
3070 case ARM::BL_PUSHLR: {
3071 const bool Thumb = Opcode == ARM::tBL_PUSHLR;
3072 Register Reg = MI.getOperand(0).getReg();
3073 assert(Reg == ARM::LR && "expect LR register!");
3074 MachineInstrBuilder MIB;
3075 if (Thumb) {
3076 // push {lr}
3077 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH))
3078 .add(predOps(ARMCC::AL))
3079 .addReg(Reg);
3080
3081 // bl __gnu_mcount_nc
3082 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
3083 } else {
3084 // stmdb sp!, {lr}
3085 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD))
3086 .addReg(ARM::SP, RegState::Define)
3087 .addReg(ARM::SP)
3088 .add(predOps(ARMCC::AL))
3089 .addReg(Reg);
3090
3091 // bl __gnu_mcount_nc
3092 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
3093 }
3094 MIB.cloneMemRefs(MI);
3095 for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
3096 MIB.add(MO);
3097 MI.eraseFromParent();
3098 return true;
3099 }
3100 case ARM::t2CALL_BTI: {
3101 MachineFunction &MF = *MI.getMF();
3102 MachineInstrBuilder MIB =
3103 BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::tBL));
3104 MIB.cloneMemRefs(MI);
3105 for (unsigned i = 0; i < MI.getNumOperands(); ++i)
3106 MIB.add(MI.getOperand(i));
3107 if (MI.isCandidateForCallSiteEntry())
3108 MF.moveCallSiteInfo(&MI, MIB.getInstr());
3109 MIBundleBuilder Bundler(MBB, MI);
3110 Bundler.append(MIB);
3111 Bundler.append(BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::t2BTI)));
3112 finalizeBundle(MBB, Bundler.begin(), Bundler.end());
3113 MI.eraseFromParent();
3114 return true;
3115 }
3116 case ARM::LOADDUAL:
3117 case ARM::STOREDUAL: {
3118 Register PairReg = MI.getOperand(0).getReg();
3119
3120 MachineInstrBuilder MIB =
3121 BuildMI(MBB, MBBI, MI.getDebugLoc(),
3122 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD))
3123 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0),
3124 Opcode == ARM::LOADDUAL ? RegState::Define : 0)
3125 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1),
3126 Opcode == ARM::LOADDUAL ? RegState::Define : 0);
3127 for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
3128 MIB.add(MO);
3129 MIB.add(predOps(ARMCC::AL));
3130 MIB.cloneMemRefs(MI);
3131 MI.eraseFromParent();
3132 return true;
3133 }
3134 }
3135 }
3136
ExpandMBB(MachineBasicBlock & MBB)3137 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
3138 bool Modified = false;
3139
3140 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
3141 while (MBBI != E) {
3142 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
3143 Modified |= ExpandMI(MBB, MBBI, NMBBI);
3144 MBBI = NMBBI;
3145 }
3146
3147 return Modified;
3148 }
3149
runOnMachineFunction(MachineFunction & MF)3150 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
3151 STI = &MF.getSubtarget<ARMSubtarget>();
3152 TII = STI->getInstrInfo();
3153 TRI = STI->getRegisterInfo();
3154 AFI = MF.getInfo<ARMFunctionInfo>();
3155
3156 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
3157 << "********** Function: " << MF.getName() << '\n');
3158
3159 bool Modified = false;
3160 for (MachineBasicBlock &MBB : MF)
3161 Modified |= ExpandMBB(MBB);
3162 if (VerifyARMPseudo)
3163 MF.verify(this, "After expanding ARM pseudo instructions.");
3164
3165 LLVM_DEBUG(dbgs() << "***************************************************\n");
3166 return Modified;
3167 }
3168
3169 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
3170 /// expansion pass.
createARMExpandPseudoPass()3171 FunctionPass *llvm::createARMExpandPseudoPass() {
3172 return new ARMExpandPseudo();
3173 }
3174