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Searched refs:ARM (Results 1 – 25 of 458) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp966 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP()
971 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP()
990 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP()
1081 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP_64()
1092 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP_64()
1110 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP_64()
1207 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; in ExpandMI()
1357 ARM::t2BICri : ARM::BICri; in ExpandMI()
1437 ? ARM::tLDRpci : ARM::t2LDRpci; in ExpandMI()
1472 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
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H A DARMFeatures.h29 case ARM::tADC: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
37 case ARM::tEOR: in isV8EligibleForIT()
43 case ARM::tMUL: in isV8EligibleForIT()
44 case ARM::tMVN: in isV8EligibleForIT()
45 case ARM::tORR: in isV8EligibleForIT()
46 case ARM::tROR: in isV8EligibleForIT()
47 case ARM::tRSB: in isV8EligibleForIT()
48 case ARM::tSBC: in isV8EligibleForIT()
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H A DARMBaseInstrInfo.cpp438 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
2179 {ARM::ADDSri, ARM::ADDri},
2180 {ARM::ADDSrr, ARM::ADDrr},
2181 {ARM::ADDSrsi, ARM::ADDrsi},
2182 {ARM::ADDSrsr, ARM::ADDrsr},
2184 {ARM::SUBSri, ARM::SUBri},
2185 {ARM::SUBSrr, ARM::SUBrr},
2189 {ARM::RSBSri, ARM::RSBri},
2196 {ARM::tADCS, ARM::tADC},
2201 {ARM::tSBCS, ARM::tSBC},
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H A DARMRegisterBankInfo.cpp31 namespace ARM { namespace
240 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
254 ? &ARM::ValueMappings[ARM::GPR3OpsIdx] in getInstrMapping()
266 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
276 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
277 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; in getInstrMapping()
354 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
355 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
356 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
366 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
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H A DARMTargetTransformInfo.h58 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
59 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
60 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
61 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
63 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
64 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
65 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
77 ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
78 ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
79 ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
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H A DThumb2SizeReduction.cpp85 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
86 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
119 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
121 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
132 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
141 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
151 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
266 case ARM::tMUL: in isHighLatencyCPSR()
394 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs()
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H A DThumb2InstrInfo.cpp371 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
376 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
379 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
403 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
408 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
411 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
435 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
436 case ARM::t2LDRHs: return ARM::t2LDRHi12; in immediateOffsetOpcode()
437 case ARM::t2LDRBs: return ARM::t2LDRBi12; in immediateOffsetOpcode()
440 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
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H A DARMInstrInfo.cpp61 case ARM::LDRH_PRE: in getUnindexedOpcode()
62 case ARM::LDRH_POST: in getUnindexedOpcode()
63 return ARM::LDRH; in getUnindexedOpcode()
69 case ARM::LDRSH_PRE: in getUnindexedOpcode()
71 return ARM::LDRSH; in getUnindexedOpcode()
80 case ARM::STRH_PRE: in getUnindexedOpcode()
82 return ARM::STRH; in getUnindexedOpcode()
100 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12); in expandLoadStackGuard()
102 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12); in expandLoadStackGuard()
107 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12); in expandLoadStackGuard()
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H A DARMLoadStoreOptimizer.cpp496 Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; in UpdateBaseRegUses()
498 Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi; in UpdateBaseRegUses()
701 isThumb1 ? ARM::tADDi8 : ARM::ADDri; in CreateLoadStoreMulti()
1023 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
1517 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1521 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1632 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1695 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1696 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1700 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
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H A DThumb1FrameLowering.cpp363 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
379 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
776 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) in spillCalleeSavedRegisters()
785 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
806 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
807 ARM::R5, ARM::R4, ARM::R3, in spillCalleeSavedRegisters()
808 ARM::R2, ARM::R1, ARM::R0}; in spillCalleeSavedRegisters()
809 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
914 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3, in restoreCalleeSavedRegisters()
915 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
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H A DARMCallingConv.h31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
163 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
165 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
166 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
167 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
168 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
169 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
170 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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H A DARMISelDAGToDAG.cpp1380 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1381 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1868 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLD()
1869 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLD()
2144 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLDSTLane()
2145 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLDSTLane()
2531 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
2660 ARM::t2ADDri : ARM::ADDri); in Select()
2912 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; in Select()
3937 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
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H A DARMFrameLowering.cpp1697 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1698 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1699 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1700 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1713 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1714 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1715 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1716 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1825 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { in determineCalleeSaves()
1846 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
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H A DARMAsmPrinter.cpp392 ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
1083 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) { in EmitUnwindingInstruction()
1390 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in EmitInstruction()
1518 case ARM::PICSTR: Opcode = ARM::STRrs; break; in EmitInstruction()
1520 case ARM::PICSTRH: Opcode = ARM::STRH; break; in EmitInstruction()
1521 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in EmitInstruction()
1523 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in EmitInstruction()
1524 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in EmitInstruction()
1525 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in EmitInstruction()
1586 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in EmitInstruction()
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H A DThumbRegisterInfo.cpp171 : ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr); in emitThumbRegPlusImmInReg()
228 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
243 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3; in emitThumbRegPlusImmediate()
251 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
349 case ARM::tLDRspi: in convertToNonSPOpcode()
350 return ARM::tLDRi; in convertToNonSPOpcode()
352 case ARM::tSTRspi: in convertToNonSPOpcode()
353 return ARM::tSTRi; in convertToNonSPOpcode()
417 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) { in rewriteFrameIndex()
585 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi)); in eliminateFrameIndex()
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H A DThumb1InstrInfo.cpp28 NopInst.setOpcode(ARM::tMOVr); in getNoop()
51 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
64 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
69 BuildMI(MBB, I, DL, get(ARM::tPUSH)) in copyPhysReg()
72 BuildMI(MBB, I, DL, get(ARM::tPOP)) in copyPhysReg()
83 assert((RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
87 if (RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
98 BuildMI(MBB, I, DL, get(ARM::tSTRspi)) in storeRegToStackSlot()
140 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi); in expandLoadStackGuard()
142 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi); in expandLoadStackGuard()
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H A DARMFastISel.cpp457 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP()
955 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
1583 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD; in SelectIToFP()
1609 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD; in SelectFPToI()
1772 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; in SelectBinaryIntOp()
1824 Opc = is64bit ? ARM::VADDD : ARM::VADDS; in SelectBinaryFPOp()
1827 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; in SelectBinaryFPOp()
1830 Opc = is64bit ? ARM::VMULD : ARM::VMULS; in SelectBinaryFPOp()
2188 return isThumb2 ? ARM::tBLXr : ARM::BLX; in ARMSelectCallOp()
2190 return isThumb2 ? ARM::tBL : ARM::BL; in ARMSelectCallOp()
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H A DARMInstructionSelector.cpp269 #define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC in OpcodeCache()
283 STORE16 = isThumb ? ARM::t2STRHi12 : ARM::STRH; in OpcodeCache()
284 LOAD16 = isThumb ? ARM::t2LDRHi12 : ARM::LDRH; in OpcodeCache()
329 return isStore ? ARM::VSTRS : ARM::VLDRS; in selectLoadStoreOpCode()
331 return isStore ? ARM::VSTRD : ARM::VLDRD; in selectLoadStoreOpCode()
603 ? (Indirect ? ARM::MOV_ga_pcrel_ldr : ARM::MOV_ga_pcrel) in selectGlobal()
604 : (Indirect ? ARM::LDRLIT_ga_pcrel_ldr : ARM::LDRLIT_ga_pcrel); in selectGlobal()
624 unsigned Opc = UseMovt ? ARM::MOV_ga_pcrel : ARM::LDRLIT_ga_pcrel; in selectGlobal()
903 CmpConstants Helper(ARM::CMPrr, ARM::INSTRUCTION_LIST_END, in select()
922 CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT, in select()
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/freebsd-12.1/contrib/llvm/include/llvm/Support/
H A DARMTargetParser.def90 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
94 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
98 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
99 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
102 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
103 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
106 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
107 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
111 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
112 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
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/freebsd-12.1/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMTargetStreamer.cpp131 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
173 emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM); in emitTargetAttributes()
215 emitFPU(ARM::FK_NEON_VFPV4); in emitTargetAttributes()
217 emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16 in emitTargetAttributes()
230 ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV5_SP_D16 in emitTargetAttributes()
235 ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV4_SP_D16 in emitTargetAttributes()
237 : ARM::FK_VFPV4); in emitTargetAttributes()
243 ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16 in emitTargetAttributes()
249 : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16 in emitTargetAttributes()
252 emitFPU(ARM::FK_VFPV2); in emitTargetAttributes()
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H A DARMAsmBackend.cpp184 case ARM::tBcc: in getRelaxedOpcode()
186 case ARM::tLDRpci: in getRelaxedOpcode()
188 case ARM::tADR: in getRelaxedOpcode()
190 case ARM::tB: in getRelaxedOpcode()
192 case ARM::tCBZ: in getRelaxedOpcode()
193 return ARM::tHINT; in getRelaxedOpcode()
194 case ARM::tCBNZ: in getRelaxedOpcode()
195 return ARM::tHINT; in getRelaxedOpcode()
281 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && in relaxInstruction()
1124 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; in generateCompactUnwindEncoding()
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H A DARMUnwindOpAsm.cpp53 assert(PI < ARM::EHABI::NUM_PERSONALITY_INDEX && in EmitPersonalityIndex()
55 EmitByte(ARM::EHABI::EHT_COMPACT | PI); in EmitPersonalityIndex()
61 EmitByte(ARM::EHABI::UNWIND_OPCODE_FINISH); in FillFinishOpcode()
129 EmitInt8(ARM::EHABI::UNWIND_OPCODE_SET_VSP | Reg); in EmitSetSP()
136 Buff[0] = ARM::EHABI::UNWIND_OPCODE_INC_VSP_ULEB128; in EmitSPOffset()
141 EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP | 0x3fu); in EmitSPOffset()
144 EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP | in EmitSPOffset()
148 EmitInt8(ARM::EHABI::UNWIND_OPCODE_DEC_VSP | 0x3fu); in EmitSPOffset()
151 EmitInt8(ARM::EHABI::UNWIND_OPCODE_DEC_VSP | in EmitSPOffset()
162 PersonalityIndex = ARM::EHABI::NUM_PERSONALITY_INDEX; in Finalize()
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/freebsd-12.1/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp870 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
871 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
872 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
873 ARM::R12, ARM::SP, ARM::LR, ARM::PC
993 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1019 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1071 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1072 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1073 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1074 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
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/freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3743 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
3744 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
3745 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
3746 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
3747 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
3748 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
3749 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
3750 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
9649 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveArch()
10592 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
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/freebsd-12.1/contrib/llvm/lib/Support/
H A DARMTargetParser.cpp28 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
89 ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) { in parseArchProfile()
240 ARM::EndianKind ARM::parseArchEndian(StringRef Arch) { in parseArchEndian()
259 ARM::ISAKind ARM::parseArchISA(StringRef Arch) { in parseArchISA()
359 ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) { in getFPUVersion()
365 ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) { in getFPURestriction()
448 StringRef ARM::getArchName(ARM::ArchKind AK) { in getArchName()
452 StringRef ARM::getCPUAttr(ARM::ArchKind AK) { in getCPUAttr()
456 StringRef ARM::getSubArch(ARM::ArchKind AK) { in getSubArch()
460 unsigned ARM::getArchAttr(ARM::ArchKind AK) { in getArchAttr()
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