Lines Matching refs:ARM
90 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
91 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
92 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
93 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
94 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
96 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
97 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
100 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
101 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
102 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
103 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
104 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
105 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
106 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
107 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
111 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), in ARMBaseInstrInfo()
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
201 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
210 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
223 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
230 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
438 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
440 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); in insertBranch()
551 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
552 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { in DefinesPredicate()
563 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
626 case ARM::tADC: // ADC (register) T1 in isEligibleForITBlock()
627 case ARM::tADDi3: // ADD (immediate) T1 in isEligibleForITBlock()
628 case ARM::tADDi8: // ADD (immediate) T2 in isEligibleForITBlock()
629 case ARM::tADDrr: // ADD (register) T1 in isEligibleForITBlock()
630 case ARM::tAND: // AND (register) T1 in isEligibleForITBlock()
631 case ARM::tASRri: // ASR (immediate) T1 in isEligibleForITBlock()
632 case ARM::tASRrr: // ASR (register) T1 in isEligibleForITBlock()
633 case ARM::tBIC: // BIC (register) T1 in isEligibleForITBlock()
634 case ARM::tEOR: // EOR (register) T1 in isEligibleForITBlock()
635 case ARM::tLSLri: // LSL (immediate) T1 in isEligibleForITBlock()
636 case ARM::tLSLrr: // LSL (register) T1 in isEligibleForITBlock()
637 case ARM::tLSRri: // LSR (immediate) T1 in isEligibleForITBlock()
638 case ARM::tLSRrr: // LSR (register) T1 in isEligibleForITBlock()
639 case ARM::tMUL: // MUL T1 in isEligibleForITBlock()
640 case ARM::tMVN: // MVN (register) T1 in isEligibleForITBlock()
641 case ARM::tORR: // ORR (register) T1 in isEligibleForITBlock()
642 case ARM::tROR: // ROR (register) T1 in isEligibleForITBlock()
643 case ARM::tRSB: // RSB (immediate) T1 in isEligibleForITBlock()
644 case ARM::tSBC: // SBC (register) T1 in isEligibleForITBlock()
645 case ARM::tSUBi3: // SUB (immediate) T1 in isEligibleForITBlock()
646 case ARM::tSUBi8: // SUB (immediate) T2 in isEligibleForITBlock()
647 case ARM::tSUBrr: // SUB (register) T1 in isEligibleForITBlock()
688 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
711 if (MI.getOpcode() == ARM::INLINEASM) { in getInstSizeInBytes()
724 case ARM::MOVi16_ga_pcrel: in getInstSizeInBytes()
725 case ARM::MOVTi16_ga_pcrel: in getInstSizeInBytes()
726 case ARM::t2MOVi16_ga_pcrel: in getInstSizeInBytes()
727 case ARM::t2MOVTi16_ga_pcrel: in getInstSizeInBytes()
729 case ARM::MOVi32imm: in getInstSizeInBytes()
730 case ARM::t2MOVi32imm: in getInstSizeInBytes()
732 case ARM::CONSTPOOL_ENTRY: in getInstSizeInBytes()
733 case ARM::JUMPTABLE_INSTS: in getInstSizeInBytes()
734 case ARM::JUMPTABLE_ADDRS: in getInstSizeInBytes()
735 case ARM::JUMPTABLE_TBB: in getInstSizeInBytes()
736 case ARM::JUMPTABLE_TBH: in getInstSizeInBytes()
740 case ARM::Int_eh_sjlj_longjmp: in getInstSizeInBytes()
742 case ARM::tInt_eh_sjlj_longjmp: in getInstSizeInBytes()
744 case ARM::tInt_WIN_eh_sjlj_longjmp: in getInstSizeInBytes()
746 case ARM::Int_eh_sjlj_setjmp: in getInstSizeInBytes()
747 case ARM::Int_eh_sjlj_setjmp_nofp: in getInstSizeInBytes()
749 case ARM::tInt_eh_sjlj_setjmp: in getInstSizeInBytes()
750 case ARM::t2Int_eh_sjlj_setjmp: in getInstSizeInBytes()
751 case ARM::t2Int_eh_sjlj_setjmp_nofp: in getInstSizeInBytes()
753 case ARM::SPACE: in getInstSizeInBytes()
774 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
775 : ARM::MRS; in copyFromCPSR()
786 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
794 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
795 : ARM::MSR; in copyToCPSR()
806 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
813 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
814 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
817 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
824 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
825 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
829 Opc = ARM::VMOVS; in copyPhysReg()
831 Opc = ARM::VMOVRS; in copyPhysReg()
833 Opc = ARM::VMOVSR; in copyPhysReg()
834 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
835 Opc = ARM::VMOVD; in copyPhysReg()
836 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
837 Opc = ARM::VORRq; in copyPhysReg()
842 if (Opc == ARM::VORRq) in copyPhysReg()
854 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
855 Opc = ARM::VORRq; in copyPhysReg()
856 BeginIdx = ARM::qsub_0; in copyPhysReg()
858 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
859 Opc = ARM::VORRq; in copyPhysReg()
860 BeginIdx = ARM::qsub_0; in copyPhysReg()
863 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
864 Opc = ARM::VMOVD; in copyPhysReg()
865 BeginIdx = ARM::dsub_0; in copyPhysReg()
867 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
868 Opc = ARM::VMOVD; in copyPhysReg()
869 BeginIdx = ARM::dsub_0; in copyPhysReg()
871 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
872 Opc = ARM::VMOVD; in copyPhysReg()
873 BeginIdx = ARM::dsub_0; in copyPhysReg()
875 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
876 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; in copyPhysReg()
877 BeginIdx = ARM::gsub_0; in copyPhysReg()
879 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
880 Opc = ARM::VMOVD; in copyPhysReg()
881 BeginIdx = ARM::dsub_0; in copyPhysReg()
884 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
885 Opc = ARM::VMOVD; in copyPhysReg()
886 BeginIdx = ARM::dsub_0; in copyPhysReg()
889 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
890 Opc = ARM::VMOVD; in copyPhysReg()
891 BeginIdx = ARM::dsub_0; in copyPhysReg()
894 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) { in copyPhysReg()
895 Opc = ARM::VMOVS; in copyPhysReg()
896 BeginIdx = ARM::ssub_0; in copyPhysReg()
898 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
901 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
929 if (Opc == ARM::VORRq) in copyPhysReg()
933 if (Opc == ARM::MOVr) in copyPhysReg()
953 (MI.getOpcode() == ARM::VORRq && in isCopyInstrImpl()
988 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
989 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH)) in storeRegToStackSlot()
999 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1000 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12)) in storeRegToStackSlot()
1006 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1007 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS)) in storeRegToStackSlot()
1017 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1018 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD)) in storeRegToStackSlot()
1024 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1026 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); in storeRegToStackSlot()
1027 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1028 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1034 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA)) in storeRegToStackSlot()
1038 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1039 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1045 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1048 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64)) in storeRegToStackSlot()
1055 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA)) in storeRegToStackSlot()
1065 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1068 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo)) in storeRegToStackSlot()
1076 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1080 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1081 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1082 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1088 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1092 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo)) in storeRegToStackSlot()
1100 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1104 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1105 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1106 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1107 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1113 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1114 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) in storeRegToStackSlot()
1118 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1119 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1120 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1121 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1122 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
1123 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
1124 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
1125 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
1138 case ARM::STRrs: in isStoreToStackSlot()
1139 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. in isStoreToStackSlot()
1147 case ARM::STRi12: in isStoreToStackSlot()
1148 case ARM::t2STRi12: in isStoreToStackSlot()
1149 case ARM::tSTRspi: in isStoreToStackSlot()
1150 case ARM::VSTRD: in isStoreToStackSlot()
1151 case ARM::VSTRS: in isStoreToStackSlot()
1158 case ARM::VST1q64: in isStoreToStackSlot()
1159 case ARM::VST1d64TPseudo: in isStoreToStackSlot()
1160 case ARM::VST1d64QPseudo: in isStoreToStackSlot()
1166 case ARM::VSTMQIA: in isStoreToStackSlot()
1205 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1206 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg) in loadRegFromStackSlot()
1215 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1216 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1221 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1222 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1231 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1232 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1237 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1241 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1242 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1243 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1249 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
1253 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1254 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1263 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1265 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1271 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1280 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1282 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1288 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1292 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1293 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1294 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1302 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1304 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1310 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1314 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1315 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1316 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1317 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1325 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1326 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1330 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1331 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1332 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1333 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1334 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1335 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1336 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1337 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1352 case ARM::LDRrs: in isLoadFromStackSlot()
1353 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. in isLoadFromStackSlot()
1361 case ARM::LDRi12: in isLoadFromStackSlot()
1362 case ARM::t2LDRi12: in isLoadFromStackSlot()
1363 case ARM::tLDRspi: in isLoadFromStackSlot()
1364 case ARM::VLDRD: in isLoadFromStackSlot()
1365 case ARM::VLDRS: in isLoadFromStackSlot()
1372 case ARM::VLD1q64: in isLoadFromStackSlot()
1373 case ARM::VLD1d8TPseudo: in isLoadFromStackSlot()
1374 case ARM::VLD1d16TPseudo: in isLoadFromStackSlot()
1375 case ARM::VLD1d32TPseudo: in isLoadFromStackSlot()
1376 case ARM::VLD1d64TPseudo: in isLoadFromStackSlot()
1377 case ARM::VLD1d8QPseudo: in isLoadFromStackSlot()
1378 case ARM::VLD1d16QPseudo: in isLoadFromStackSlot()
1379 case ARM::VLD1d32QPseudo: in isLoadFromStackSlot()
1380 case ARM::VLD1d64QPseudo: in isLoadFromStackSlot()
1386 case ARM::VLDMQIA: in isLoadFromStackSlot()
1422 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1423 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()
1424 : ARM::LDMIA_UPD)) in expandMEMCPY()
1427 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1432 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1433 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
1434 : ARM::STMIA_UPD)) in expandMEMCPY()
1437 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1474 if (MI.getOpcode() == ARM::MEMCPY) { in expandPostRAPseudo()
1490 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) in expandPostRAPseudo()
1494 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1495 &ARM::DPRRegClass); in expandPostRAPseudo()
1496 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
1497 &ARM::DPRRegClass); in expandPostRAPseudo()
1522 MI.setDesc(get(ARM::VMOVD)); in expandPostRAPseudo()
1603 case ARM::tLDRpci_pic: in reMaterialize()
1604 case ARM::t2LDRpci_pic: { in reMaterialize()
1625 case ARM::tLDRpci_pic: in duplicate()
1626 case ARM::t2LDRpci_pic: { in duplicate()
1646 if (Opcode == ARM::t2LDRpci || in produceSameValue()
1647 Opcode == ARM::t2LDRpci_pic || in produceSameValue()
1648 Opcode == ARM::tLDRpci || in produceSameValue()
1649 Opcode == ARM::tLDRpci_pic || in produceSameValue()
1650 Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1651 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1652 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1653 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1654 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1655 Opcode == ARM::t2MOV_ga_pcrel) { in produceSameValue()
1666 if (Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1667 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1668 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1669 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1670 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1671 Opcode == ARM::t2MOV_ga_pcrel) in produceSameValue()
1693 } else if (Opcode == ARM::PICLDR) { in produceSameValue()
1749 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1750 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1751 case ARM::LDRD: in areLoadsFromSameBasePtr()
1752 case ARM::LDRH: in areLoadsFromSameBasePtr()
1753 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1754 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1755 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1756 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1757 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1758 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1759 case ARM::t2LDRDi8: in areLoadsFromSameBasePtr()
1760 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1761 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1762 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1763 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1770 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1771 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1772 case ARM::LDRD: in areLoadsFromSameBasePtr()
1773 case ARM::LDRH: in areLoadsFromSameBasePtr()
1774 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1775 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1776 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1777 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1778 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1779 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1780 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1781 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1782 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1783 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1835 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
1836 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
1837 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && in shouldScheduleLoadsNear()
1838 Load2->getMachineOpcode() == ARM::t2LDRBi8))) in shouldScheduleLoadsNear()
1874 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) in isSchedulingBoundary()
1885 if (!MI.isCall() && MI.definesRegister(ARM::SP)) in isSchedulingBoundary()
1905 if (LastMI->getOpcode() == ARM::t2Bcc) { in isProfitableToIfCvt()
1909 if (CmpMI->getOpcode() == ARM::tCMPi8 || in isProfitableToIfCvt()
1910 CmpMI->getOpcode() == ARM::t2CMPri) { in isProfitableToIfCvt()
2005 if (Opc == ARM::B) in getMatchingCondBranchOpcode()
2006 return ARM::Bcc; in getMatchingCondBranchOpcode()
2007 if (Opc == ARM::tB) in getMatchingCondBranchOpcode()
2008 return ARM::tBcc; in getMatchingCondBranchOpcode()
2009 if (Opc == ARM::t2B) in getMatchingCondBranchOpcode()
2010 return ARM::t2Bcc; in getMatchingCondBranchOpcode()
2020 case ARM::MOVCCr: in commuteInstructionImpl()
2021 case ARM::t2MOVCCr: { in commuteInstructionImpl()
2026 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2083 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in analyzeSelect()
2104 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in optimizeSelect()
2179 {ARM::ADDSri, ARM::ADDri},
2180 {ARM::ADDSrr, ARM::ADDrr},
2181 {ARM::ADDSrsi, ARM::ADDrsi},
2182 {ARM::ADDSrsr, ARM::ADDrsr},
2184 {ARM::SUBSri, ARM::SUBri},
2185 {ARM::SUBSrr, ARM::SUBrr},
2186 {ARM::SUBSrsi, ARM::SUBrsi},
2187 {ARM::SUBSrsr, ARM::SUBrsr},
2189 {ARM::RSBSri, ARM::RSBri},
2190 {ARM::RSBSrsi, ARM::RSBrsi},
2191 {ARM::RSBSrsr, ARM::RSBrsr},
2193 {ARM::tADDSi3, ARM::tADDi3},
2194 {ARM::tADDSi8, ARM::tADDi8},
2195 {ARM::tADDSrr, ARM::tADDrr},
2196 {ARM::tADCS, ARM::tADC},
2198 {ARM::tSUBSi3, ARM::tSUBi3},
2199 {ARM::tSUBSi8, ARM::tSUBi8},
2200 {ARM::tSUBSrr, ARM::tSUBrr},
2201 {ARM::tSBCS, ARM::tSBC},
2202 {ARM::tRSBS, ARM::tRSB},
2204 {ARM::t2ADDSri, ARM::t2ADDri},
2205 {ARM::t2ADDSrr, ARM::t2ADDrr},
2206 {ARM::t2ADDSrs, ARM::t2ADDrs},
2208 {ARM::t2SUBSri, ARM::t2SUBri},
2209 {ARM::t2SUBSrr, ARM::t2SUBrr},
2210 {ARM::t2SUBSrs, ARM::t2SUBrs},
2212 {ARM::t2RSBSri, ARM::t2RSBri},
2213 {ARM::t2RSBSrs, ARM::t2RSBrs},
2231 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2253 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2280 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || in tryFoldSPUpdateIntoPushPop()
2281 MI->getOpcode() == ARM::VLDMDIA_UPD; in tryFoldSPUpdateIntoPushPop()
2282 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || in tryFoldSPUpdateIntoPushPop()
2283 MI->getOpcode() == ARM::tPOP || in tryFoldSPUpdateIntoPushPop()
2284 MI->getOpcode() == ARM::tPOP_RET; in tryFoldSPUpdateIntoPushPop()
2286 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && in tryFoldSPUpdateIntoPushPop()
2287 MI->getOperand(1).getReg() == ARM::SP)) && in tryFoldSPUpdateIntoPushPop()
2305 RegClass = &ARM::DPRRegClass; in tryFoldSPUpdateIntoPushPop()
2308 RegClass = &ARM::GPRRegClass; in tryFoldSPUpdateIntoPushPop()
2392 if (Opcode == ARM::INLINEASM) in rewriteARMFrameIndex()
2395 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2399 MI.setDesc(TII.get(ARM::MOVr)); in rewriteARMFrameIndex()
2407 MI.setDesc(TII.get(ARM::SUBri)); in rewriteARMFrameIndex()
2536 case ARM::CMPri: in analyzeCompare()
2537 case ARM::t2CMPri: in analyzeCompare()
2538 case ARM::tCMPi8: in analyzeCompare()
2544 case ARM::CMPrr: in analyzeCompare()
2545 case ARM::t2CMPrr: in analyzeCompare()
2551 case ARM::TSTri: in analyzeCompare()
2552 case ARM::t2TSTri: in analyzeCompare()
2570 case ARM::ANDri: in isSuitableForMask()
2571 case ARM::t2ANDri: in isSuitableForMask()
2623 if ((CmpI->getOpcode() == ARM::CMPrr || in isRedundantFlagInstr()
2624 CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2625 (OI->getOpcode() == ARM::SUBrr || in isRedundantFlagInstr()
2626 OI->getOpcode() == ARM::t2SUBrr) && in isRedundantFlagInstr()
2633 if ((CmpI->getOpcode() == ARM::CMPri || in isRedundantFlagInstr()
2634 CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
2635 (OI->getOpcode() == ARM::SUBri || in isRedundantFlagInstr()
2636 OI->getOpcode() == ARM::t2SUBri) && in isRedundantFlagInstr()
2641 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2642 (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr || in isRedundantFlagInstr()
2643 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr()
2654 case ARM::tLSLri: in isOptimizeCompareCandidate()
2655 case ARM::tLSRri: in isOptimizeCompareCandidate()
2656 case ARM::tLSLrr: in isOptimizeCompareCandidate()
2657 case ARM::tLSRrr: in isOptimizeCompareCandidate()
2658 case ARM::tSUBrr: in isOptimizeCompareCandidate()
2659 case ARM::tADDrr: in isOptimizeCompareCandidate()
2660 case ARM::tADDi3: in isOptimizeCompareCandidate()
2661 case ARM::tADDi8: in isOptimizeCompareCandidate()
2662 case ARM::tSUBi3: in isOptimizeCompareCandidate()
2663 case ARM::tSUBi8: in isOptimizeCompareCandidate()
2664 case ARM::tMUL: in isOptimizeCompareCandidate()
2667 case ARM::RSBrr: in isOptimizeCompareCandidate()
2668 case ARM::RSBri: in isOptimizeCompareCandidate()
2669 case ARM::RSCrr: in isOptimizeCompareCandidate()
2670 case ARM::RSCri: in isOptimizeCompareCandidate()
2671 case ARM::ADDrr: in isOptimizeCompareCandidate()
2672 case ARM::ADDri: in isOptimizeCompareCandidate()
2673 case ARM::ADCrr: in isOptimizeCompareCandidate()
2674 case ARM::ADCri: in isOptimizeCompareCandidate()
2675 case ARM::SUBrr: in isOptimizeCompareCandidate()
2676 case ARM::SUBri: in isOptimizeCompareCandidate()
2677 case ARM::SBCrr: in isOptimizeCompareCandidate()
2678 case ARM::SBCri: in isOptimizeCompareCandidate()
2679 case ARM::t2RSBri: in isOptimizeCompareCandidate()
2680 case ARM::t2ADDrr: in isOptimizeCompareCandidate()
2681 case ARM::t2ADDri: in isOptimizeCompareCandidate()
2682 case ARM::t2ADCrr: in isOptimizeCompareCandidate()
2683 case ARM::t2ADCri: in isOptimizeCompareCandidate()
2684 case ARM::t2SUBrr: in isOptimizeCompareCandidate()
2685 case ARM::t2SUBri: in isOptimizeCompareCandidate()
2686 case ARM::t2SBCrr: in isOptimizeCompareCandidate()
2687 case ARM::t2SBCri: in isOptimizeCompareCandidate()
2688 case ARM::ANDrr: in isOptimizeCompareCandidate()
2689 case ARM::ANDri: in isOptimizeCompareCandidate()
2690 case ARM::t2ANDrr: in isOptimizeCompareCandidate()
2691 case ARM::t2ANDri: in isOptimizeCompareCandidate()
2692 case ARM::ORRrr: in isOptimizeCompareCandidate()
2693 case ARM::ORRri: in isOptimizeCompareCandidate()
2694 case ARM::t2ORRrr: in isOptimizeCompareCandidate()
2695 case ARM::t2ORRri: in isOptimizeCompareCandidate()
2696 case ARM::EORrr: in isOptimizeCompareCandidate()
2697 case ARM::EORri: in isOptimizeCompareCandidate()
2698 case ARM::t2EORrr: in isOptimizeCompareCandidate()
2699 case ARM::t2EORri: in isOptimizeCompareCandidate()
2700 case ARM::t2LSRri: in isOptimizeCompareCandidate()
2701 case ARM::t2LSRrr: in isOptimizeCompareCandidate()
2702 case ARM::t2LSLri: in isOptimizeCompareCandidate()
2703 case ARM::t2LSLrr: in isOptimizeCompareCandidate()
2763 if (CmpInstr.getOpcode() == ARM::CMPri || in optimizeCompareInstr()
2764 CmpInstr.getOpcode() == ARM::t2CMPri) in optimizeCompareInstr()
2791 if (I->getOpcode() != ARM::tMOVi8) { in optimizeCompareInstr()
2821 if (Instr.modifiesRegister(ARM::CPSR, TRI) || in optimizeCompareInstr()
2822 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
2864 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()
2868 if (!MO.isReg() || MO.getReg() != ARM::CPSR) in optimizeCompareInstr()
2882 case ARM::VSELEQD: in optimizeCompareInstr()
2883 case ARM::VSELEQS: in optimizeCompareInstr()
2886 case ARM::VSELGTD: in optimizeCompareInstr()
2887 case ARM::VSELGTS: in optimizeCompareInstr()
2890 case ARM::VSELGED: in optimizeCompareInstr()
2891 case ARM::VSELGES: in optimizeCompareInstr()
2894 case ARM::VSELVSS: in optimizeCompareInstr()
2895 case ARM::VSELVSD: in optimizeCompareInstr()
2909 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr || in optimizeCompareInstr()
2910 Opc == ARM::SUBri || Opc == ARM::t2SUBri; in optimizeCompareInstr()
2956 if ((*SI)->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
2963 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
2975 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
3002 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) in FoldImmediate()
3015 if (MO.getReg() == ARM::CPSR && !MO.isDead()) in FoldImmediate()
3024 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR) in FoldImmediate()
3037 case ARM::SUBrr: in FoldImmediate()
3038 case ARM::ADDrr: in FoldImmediate()
3039 case ARM::ORRrr: in FoldImmediate()
3040 case ARM::EORrr: in FoldImmediate()
3041 case ARM::t2SUBrr: in FoldImmediate()
3042 case ARM::t2ADDrr: in FoldImmediate()
3043 case ARM::t2ORRrr: in FoldImmediate()
3044 case ARM::t2EORrr: { in FoldImmediate()
3048 case ARM::ADDrr: in FoldImmediate()
3049 case ARM::SUBrr: in FoldImmediate()
3050 if (UseOpc == ARM::SUBrr && Commute) in FoldImmediate()
3056 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate()
3059 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
3065 case ARM::ORRrr: in FoldImmediate()
3066 case ARM::EORrr: in FoldImmediate()
3073 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; in FoldImmediate()
3074 case ARM::EORrr: NewUseOpc = ARM::EORri; break; in FoldImmediate()
3077 case ARM::t2ADDrr: in FoldImmediate()
3078 case ARM::t2SUBrr: in FoldImmediate()
3079 if (UseOpc == ARM::t2SUBrr && Commute) in FoldImmediate()
3085 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri; in FoldImmediate()
3088 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri; in FoldImmediate()
3094 case ARM::t2ORRrr: in FoldImmediate()
3095 case ARM::t2EORrr: in FoldImmediate()
3102 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; in FoldImmediate()
3103 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; in FoldImmediate()
3138 case ARM::LDRrs: in getNumMicroOpsSwiftLdSt()
3139 case ARM::LDRBrs: in getNumMicroOpsSwiftLdSt()
3140 case ARM::STRrs: in getNumMicroOpsSwiftLdSt()
3141 case ARM::STRBrs: { in getNumMicroOpsSwiftLdSt()
3153 case ARM::LDRH: in getNumMicroOpsSwiftLdSt()
3154 case ARM::STRH: { in getNumMicroOpsSwiftLdSt()
3169 case ARM::LDRSB: in getNumMicroOpsSwiftLdSt()
3170 case ARM::LDRSH: in getNumMicroOpsSwiftLdSt()
3173 case ARM::LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3174 case ARM::LDRSH_POST: { in getNumMicroOpsSwiftLdSt()
3180 case ARM::LDR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3181 case ARM::LDRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3197 case ARM::STR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3198 case ARM::STRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3210 case ARM::LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3211 case ARM::STRH_PRE: { in getNumMicroOpsSwiftLdSt()
3221 case ARM::LDR_POST_REG: in getNumMicroOpsSwiftLdSt()
3222 case ARM::LDRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3223 case ARM::LDRH_POST: { in getNumMicroOpsSwiftLdSt()
3229 case ARM::LDR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3230 case ARM::LDRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3231 case ARM::LDR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3232 case ARM::LDRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3233 case ARM::STRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3234 case ARM::STRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3235 case ARM::STRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3236 case ARM::STRH_POST: in getNumMicroOpsSwiftLdSt()
3237 case ARM::STR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3238 case ARM::STR_POST_REG: in getNumMicroOpsSwiftLdSt()
3239 case ARM::STR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3242 case ARM::LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3243 case ARM::LDRSH_PRE: { in getNumMicroOpsSwiftLdSt()
3261 case ARM::LDRD: { in getNumMicroOpsSwiftLdSt()
3271 case ARM::STRD: { in getNumMicroOpsSwiftLdSt()
3279 case ARM::LDRD_POST: in getNumMicroOpsSwiftLdSt()
3280 case ARM::t2LDRD_POST: in getNumMicroOpsSwiftLdSt()
3283 case ARM::STRD_POST: in getNumMicroOpsSwiftLdSt()
3284 case ARM::t2STRD_POST: in getNumMicroOpsSwiftLdSt()
3287 case ARM::LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3297 case ARM::t2LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3303 case ARM::STRD_PRE: { in getNumMicroOpsSwiftLdSt()
3311 case ARM::t2STRD_PRE: in getNumMicroOpsSwiftLdSt()
3314 case ARM::t2LDR_POST: in getNumMicroOpsSwiftLdSt()
3315 case ARM::t2LDRB_POST: in getNumMicroOpsSwiftLdSt()
3316 case ARM::t2LDRB_PRE: in getNumMicroOpsSwiftLdSt()
3317 case ARM::t2LDRSBi12: in getNumMicroOpsSwiftLdSt()
3318 case ARM::t2LDRSBi8: in getNumMicroOpsSwiftLdSt()
3319 case ARM::t2LDRSBpci: in getNumMicroOpsSwiftLdSt()
3320 case ARM::t2LDRSBs: in getNumMicroOpsSwiftLdSt()
3321 case ARM::t2LDRH_POST: in getNumMicroOpsSwiftLdSt()
3322 case ARM::t2LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3323 case ARM::t2LDRSBT: in getNumMicroOpsSwiftLdSt()
3324 case ARM::t2LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3325 case ARM::t2LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3326 case ARM::t2LDRSH_POST: in getNumMicroOpsSwiftLdSt()
3327 case ARM::t2LDRSH_PRE: in getNumMicroOpsSwiftLdSt()
3328 case ARM::t2LDRSHi12: in getNumMicroOpsSwiftLdSt()
3329 case ARM::t2LDRSHi8: in getNumMicroOpsSwiftLdSt()
3330 case ARM::t2LDRSHpci: in getNumMicroOpsSwiftLdSt()
3331 case ARM::t2LDRSHs: in getNumMicroOpsSwiftLdSt()
3334 case ARM::t2LDRDi8: { in getNumMicroOpsSwiftLdSt()
3340 case ARM::t2STRB_POST: in getNumMicroOpsSwiftLdSt()
3341 case ARM::t2STRB_PRE: in getNumMicroOpsSwiftLdSt()
3342 case ARM::t2STRBs: in getNumMicroOpsSwiftLdSt()
3343 case ARM::t2STRDi8: in getNumMicroOpsSwiftLdSt()
3344 case ARM::t2STRH_POST: in getNumMicroOpsSwiftLdSt()
3345 case ARM::t2STRH_PRE: in getNumMicroOpsSwiftLdSt()
3346 case ARM::t2STRHs: in getNumMicroOpsSwiftLdSt()
3347 case ARM::t2STR_POST: in getNumMicroOpsSwiftLdSt()
3348 case ARM::t2STR_PRE: in getNumMicroOpsSwiftLdSt()
3349 case ARM::t2STRs: in getNumMicroOpsSwiftLdSt()
3392 case ARM::VLDMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3393 case ARM::VLDMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3394 case ARM::VLDMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3395 case ARM::VLDMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3396 case ARM::VSTMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3397 case ARM::VSTMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3398 case ARM::VSTMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3399 case ARM::VSTMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3400 case ARM::LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3401 case ARM::LDMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3402 case ARM::LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3403 case ARM::LDMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3404 case ARM::STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3405 case ARM::STMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3406 case ARM::STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3407 case ARM::STMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3408 case ARM::tLDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3409 case ARM::tSTMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3410 case ARM::t2LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3411 case ARM::t2LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3412 case ARM::t2STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3413 case ARM::t2STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3416 case ARM::LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3417 case ARM::tPOP_RET: in getNumMicroOpsSingleIssuePlusExtras()
3418 case ARM::t2LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3444 case ARM::VLDMQIA: in getNumMicroOps()
3445 case ARM::VSTMQIA: in getNumMicroOps()
3458 case ARM::VLDMDIA: in getNumMicroOps()
3459 case ARM::VLDMDIA_UPD: in getNumMicroOps()
3460 case ARM::VLDMDDB_UPD: in getNumMicroOps()
3461 case ARM::VLDMSIA: in getNumMicroOps()
3462 case ARM::VLDMSIA_UPD: in getNumMicroOps()
3463 case ARM::VLDMSDB_UPD: in getNumMicroOps()
3464 case ARM::VSTMDIA: in getNumMicroOps()
3465 case ARM::VSTMDIA_UPD: in getNumMicroOps()
3466 case ARM::VSTMDDB_UPD: in getNumMicroOps()
3467 case ARM::VSTMSIA: in getNumMicroOps()
3468 case ARM::VSTMSIA_UPD: in getNumMicroOps()
3469 case ARM::VSTMSDB_UPD: { in getNumMicroOps()
3474 case ARM::LDMIA_RET: in getNumMicroOps()
3475 case ARM::LDMIA: in getNumMicroOps()
3476 case ARM::LDMDA: in getNumMicroOps()
3477 case ARM::LDMDB: in getNumMicroOps()
3478 case ARM::LDMIB: in getNumMicroOps()
3479 case ARM::LDMIA_UPD: in getNumMicroOps()
3480 case ARM::LDMDA_UPD: in getNumMicroOps()
3481 case ARM::LDMDB_UPD: in getNumMicroOps()
3482 case ARM::LDMIB_UPD: in getNumMicroOps()
3483 case ARM::STMIA: in getNumMicroOps()
3484 case ARM::STMDA: in getNumMicroOps()
3485 case ARM::STMDB: in getNumMicroOps()
3486 case ARM::STMIB: in getNumMicroOps()
3487 case ARM::STMIA_UPD: in getNumMicroOps()
3488 case ARM::STMDA_UPD: in getNumMicroOps()
3489 case ARM::STMDB_UPD: in getNumMicroOps()
3490 case ARM::STMIB_UPD: in getNumMicroOps()
3491 case ARM::tLDMIA: in getNumMicroOps()
3492 case ARM::tLDMIA_UPD: in getNumMicroOps()
3493 case ARM::tSTMIA_UPD: in getNumMicroOps()
3494 case ARM::tPOP_RET: in getNumMicroOps()
3495 case ARM::tPOP: in getNumMicroOps()
3496 case ARM::tPUSH: in getNumMicroOps()
3497 case ARM::t2LDMIA_RET: in getNumMicroOps()
3498 case ARM::t2LDMIA: in getNumMicroOps()
3499 case ARM::t2LDMDB: in getNumMicroOps()
3500 case ARM::t2LDMIA_UPD: in getNumMicroOps()
3501 case ARM::t2LDMDB_UPD: in getNumMicroOps()
3502 case ARM::t2STMIA: in getNumMicroOps()
3503 case ARM::t2STMDB: in getNumMicroOps()
3504 case ARM::t2STMIA_UPD: in getNumMicroOps()
3505 case ARM::t2STMDB_UPD: { in getNumMicroOps()
3560 case ARM::VLDMSIA: in getVLDMDefCycle()
3561 case ARM::VLDMSIA_UPD: in getVLDMDefCycle()
3562 case ARM::VLDMSDB_UPD: in getVLDMDefCycle()
3651 case ARM::VSTMSIA: in getVSTMUseCycle()
3652 case ARM::VSTMSIA_UPD: in getVSTMUseCycle()
3653 case ARM::VSTMSDB_UPD: in getVSTMUseCycle()
3721 case ARM::VLDMDIA: in getOperandLatency()
3722 case ARM::VLDMDIA_UPD: in getOperandLatency()
3723 case ARM::VLDMDDB_UPD: in getOperandLatency()
3724 case ARM::VLDMSIA: in getOperandLatency()
3725 case ARM::VLDMSIA_UPD: in getOperandLatency()
3726 case ARM::VLDMSDB_UPD: in getOperandLatency()
3730 case ARM::LDMIA_RET: in getOperandLatency()
3731 case ARM::LDMIA: in getOperandLatency()
3732 case ARM::LDMDA: in getOperandLatency()
3733 case ARM::LDMDB: in getOperandLatency()
3734 case ARM::LDMIB: in getOperandLatency()
3735 case ARM::LDMIA_UPD: in getOperandLatency()
3736 case ARM::LDMDA_UPD: in getOperandLatency()
3737 case ARM::LDMDB_UPD: in getOperandLatency()
3738 case ARM::LDMIB_UPD: in getOperandLatency()
3739 case ARM::tLDMIA: in getOperandLatency()
3740 case ARM::tLDMIA_UPD: in getOperandLatency()
3741 case ARM::tPUSH: in getOperandLatency()
3742 case ARM::t2LDMIA_RET: in getOperandLatency()
3743 case ARM::t2LDMIA: in getOperandLatency()
3744 case ARM::t2LDMDB: in getOperandLatency()
3745 case ARM::t2LDMIA_UPD: in getOperandLatency()
3746 case ARM::t2LDMDB_UPD: in getOperandLatency()
3762 case ARM::VSTMDIA: in getOperandLatency()
3763 case ARM::VSTMDIA_UPD: in getOperandLatency()
3764 case ARM::VSTMDDB_UPD: in getOperandLatency()
3765 case ARM::VSTMSIA: in getOperandLatency()
3766 case ARM::VSTMSIA_UPD: in getOperandLatency()
3767 case ARM::VSTMSDB_UPD: in getOperandLatency()
3771 case ARM::STMIA: in getOperandLatency()
3772 case ARM::STMDA: in getOperandLatency()
3773 case ARM::STMDB: in getOperandLatency()
3774 case ARM::STMIB: in getOperandLatency()
3775 case ARM::STMIA_UPD: in getOperandLatency()
3776 case ARM::STMDA_UPD: in getOperandLatency()
3777 case ARM::STMDB_UPD: in getOperandLatency()
3778 case ARM::STMIB_UPD: in getOperandLatency()
3779 case ARM::tSTMIA_UPD: in getOperandLatency()
3780 case ARM::tPOP_RET: in getOperandLatency()
3781 case ARM::tPOP: in getOperandLatency()
3782 case ARM::t2STMIA: in getOperandLatency()
3783 case ARM::t2STMDB: in getOperandLatency()
3784 case ARM::t2STMIA_UPD: in getOperandLatency()
3785 case ARM::t2STMDB_UPD: in getOperandLatency()
3849 if (II->getOpcode() != ARM::t2IT) in getBundledUseMI()
3875 case ARM::LDRrs: in adjustDefLatency()
3876 case ARM::LDRBrs: { in adjustDefLatency()
3884 case ARM::t2LDRs: in adjustDefLatency()
3885 case ARM::t2LDRBs: in adjustDefLatency()
3886 case ARM::t2LDRHs: in adjustDefLatency()
3887 case ARM::t2LDRSHs: { in adjustDefLatency()
3900 case ARM::LDRrs: in adjustDefLatency()
3901 case ARM::LDRBrs: { in adjustDefLatency()
3915 case ARM::t2LDRs: in adjustDefLatency()
3916 case ARM::t2LDRBs: in adjustDefLatency()
3917 case ARM::t2LDRHs: in adjustDefLatency()
3918 case ARM::t2LDRSHs: { in adjustDefLatency()
3931 case ARM::VLD1q8: in adjustDefLatency()
3932 case ARM::VLD1q16: in adjustDefLatency()
3933 case ARM::VLD1q32: in adjustDefLatency()
3934 case ARM::VLD1q64: in adjustDefLatency()
3935 case ARM::VLD1q8wb_fixed: in adjustDefLatency()
3936 case ARM::VLD1q16wb_fixed: in adjustDefLatency()
3937 case ARM::VLD1q32wb_fixed: in adjustDefLatency()
3938 case ARM::VLD1q64wb_fixed: in adjustDefLatency()
3939 case ARM::VLD1q8wb_register: in adjustDefLatency()
3940 case ARM::VLD1q16wb_register: in adjustDefLatency()
3941 case ARM::VLD1q32wb_register: in adjustDefLatency()
3942 case ARM::VLD1q64wb_register: in adjustDefLatency()
3943 case ARM::VLD2d8: in adjustDefLatency()
3944 case ARM::VLD2d16: in adjustDefLatency()
3945 case ARM::VLD2d32: in adjustDefLatency()
3946 case ARM::VLD2q8: in adjustDefLatency()
3947 case ARM::VLD2q16: in adjustDefLatency()
3948 case ARM::VLD2q32: in adjustDefLatency()
3949 case ARM::VLD2d8wb_fixed: in adjustDefLatency()
3950 case ARM::VLD2d16wb_fixed: in adjustDefLatency()
3951 case ARM::VLD2d32wb_fixed: in adjustDefLatency()
3952 case ARM::VLD2q8wb_fixed: in adjustDefLatency()
3953 case ARM::VLD2q16wb_fixed: in adjustDefLatency()
3954 case ARM::VLD2q32wb_fixed: in adjustDefLatency()
3955 case ARM::VLD2d8wb_register: in adjustDefLatency()
3956 case ARM::VLD2d16wb_register: in adjustDefLatency()
3957 case ARM::VLD2d32wb_register: in adjustDefLatency()
3958 case ARM::VLD2q8wb_register: in adjustDefLatency()
3959 case ARM::VLD2q16wb_register: in adjustDefLatency()
3960 case ARM::VLD2q32wb_register: in adjustDefLatency()
3961 case ARM::VLD3d8: in adjustDefLatency()
3962 case ARM::VLD3d16: in adjustDefLatency()
3963 case ARM::VLD3d32: in adjustDefLatency()
3964 case ARM::VLD1d64T: in adjustDefLatency()
3965 case ARM::VLD3d8_UPD: in adjustDefLatency()
3966 case ARM::VLD3d16_UPD: in adjustDefLatency()
3967 case ARM::VLD3d32_UPD: in adjustDefLatency()
3968 case ARM::VLD1d64Twb_fixed: in adjustDefLatency()
3969 case ARM::VLD1d64Twb_register: in adjustDefLatency()
3970 case ARM::VLD3q8_UPD: in adjustDefLatency()
3971 case ARM::VLD3q16_UPD: in adjustDefLatency()
3972 case ARM::VLD3q32_UPD: in adjustDefLatency()
3973 case ARM::VLD4d8: in adjustDefLatency()
3974 case ARM::VLD4d16: in adjustDefLatency()
3975 case ARM::VLD4d32: in adjustDefLatency()
3976 case ARM::VLD1d64Q: in adjustDefLatency()
3977 case ARM::VLD4d8_UPD: in adjustDefLatency()
3978 case ARM::VLD4d16_UPD: in adjustDefLatency()
3979 case ARM::VLD4d32_UPD: in adjustDefLatency()
3980 case ARM::VLD1d64Qwb_fixed: in adjustDefLatency()
3981 case ARM::VLD1d64Qwb_register: in adjustDefLatency()
3982 case ARM::VLD4q8_UPD: in adjustDefLatency()
3983 case ARM::VLD4q16_UPD: in adjustDefLatency()
3984 case ARM::VLD4q32_UPD: in adjustDefLatency()
3985 case ARM::VLD1DUPq8: in adjustDefLatency()
3986 case ARM::VLD1DUPq16: in adjustDefLatency()
3987 case ARM::VLD1DUPq32: in adjustDefLatency()
3988 case ARM::VLD1DUPq8wb_fixed: in adjustDefLatency()
3989 case ARM::VLD1DUPq16wb_fixed: in adjustDefLatency()
3990 case ARM::VLD1DUPq32wb_fixed: in adjustDefLatency()
3991 case ARM::VLD1DUPq8wb_register: in adjustDefLatency()
3992 case ARM::VLD1DUPq16wb_register: in adjustDefLatency()
3993 case ARM::VLD1DUPq32wb_register: in adjustDefLatency()
3994 case ARM::VLD2DUPd8: in adjustDefLatency()
3995 case ARM::VLD2DUPd16: in adjustDefLatency()
3996 case ARM::VLD2DUPd32: in adjustDefLatency()
3997 case ARM::VLD2DUPd8wb_fixed: in adjustDefLatency()
3998 case ARM::VLD2DUPd16wb_fixed: in adjustDefLatency()
3999 case ARM::VLD2DUPd32wb_fixed: in adjustDefLatency()
4000 case ARM::VLD2DUPd8wb_register: in adjustDefLatency()
4001 case ARM::VLD2DUPd16wb_register: in adjustDefLatency()
4002 case ARM::VLD2DUPd32wb_register: in adjustDefLatency()
4003 case ARM::VLD4DUPd8: in adjustDefLatency()
4004 case ARM::VLD4DUPd16: in adjustDefLatency()
4005 case ARM::VLD4DUPd32: in adjustDefLatency()
4006 case ARM::VLD4DUPd8_UPD: in adjustDefLatency()
4007 case ARM::VLD4DUPd16_UPD: in adjustDefLatency()
4008 case ARM::VLD4DUPd32_UPD: in adjustDefLatency()
4009 case ARM::VLD1LNd8: in adjustDefLatency()
4010 case ARM::VLD1LNd16: in adjustDefLatency()
4011 case ARM::VLD1LNd32: in adjustDefLatency()
4012 case ARM::VLD1LNd8_UPD: in adjustDefLatency()
4013 case ARM::VLD1LNd16_UPD: in adjustDefLatency()
4014 case ARM::VLD1LNd32_UPD: in adjustDefLatency()
4015 case ARM::VLD2LNd8: in adjustDefLatency()
4016 case ARM::VLD2LNd16: in adjustDefLatency()
4017 case ARM::VLD2LNd32: in adjustDefLatency()
4018 case ARM::VLD2LNq16: in adjustDefLatency()
4019 case ARM::VLD2LNq32: in adjustDefLatency()
4020 case ARM::VLD2LNd8_UPD: in adjustDefLatency()
4021 case ARM::VLD2LNd16_UPD: in adjustDefLatency()
4022 case ARM::VLD2LNd32_UPD: in adjustDefLatency()
4023 case ARM::VLD2LNq16_UPD: in adjustDefLatency()
4024 case ARM::VLD2LNq32_UPD: in adjustDefLatency()
4025 case ARM::VLD4LNd8: in adjustDefLatency()
4026 case ARM::VLD4LNd16: in adjustDefLatency()
4027 case ARM::VLD4LNd32: in adjustDefLatency()
4028 case ARM::VLD4LNq16: in adjustDefLatency()
4029 case ARM::VLD4LNq32: in adjustDefLatency()
4030 case ARM::VLD4LNd8_UPD: in adjustDefLatency()
4031 case ARM::VLD4LNd16_UPD: in adjustDefLatency()
4032 case ARM::VLD4LNd32_UPD: in adjustDefLatency()
4033 case ARM::VLD4LNq16_UPD: in adjustDefLatency()
4034 case ARM::VLD4LNq32_UPD: in adjustDefLatency()
4085 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
4086 if (DefMI.getOpcode() == ARM::FMSTAT) { in getOperandLatencyImpl()
4179 case ARM::LDRrs: in getOperandLatency()
4180 case ARM::LDRBrs: { in getOperandLatency()
4189 case ARM::t2LDRs: in getOperandLatency()
4190 case ARM::t2LDRBs: in getOperandLatency()
4191 case ARM::t2LDRHs: in getOperandLatency()
4192 case ARM::t2LDRSHs: { in getOperandLatency()
4206 case ARM::LDRrs: in getOperandLatency()
4207 case ARM::LDRBrs: { in getOperandLatency()
4219 case ARM::t2LDRs: in getOperandLatency()
4220 case ARM::t2LDRBs: in getOperandLatency()
4221 case ARM::t2LDRHs: in getOperandLatency()
4222 case ARM::t2LDRSHs: in getOperandLatency()
4232 case ARM::VLD1q8: in getOperandLatency()
4233 case ARM::VLD1q16: in getOperandLatency()
4234 case ARM::VLD1q32: in getOperandLatency()
4235 case ARM::VLD1q64: in getOperandLatency()
4236 case ARM::VLD1q8wb_register: in getOperandLatency()
4237 case ARM::VLD1q16wb_register: in getOperandLatency()
4238 case ARM::VLD1q32wb_register: in getOperandLatency()
4239 case ARM::VLD1q64wb_register: in getOperandLatency()
4240 case ARM::VLD1q8wb_fixed: in getOperandLatency()
4241 case ARM::VLD1q16wb_fixed: in getOperandLatency()
4242 case ARM::VLD1q32wb_fixed: in getOperandLatency()
4243 case ARM::VLD1q64wb_fixed: in getOperandLatency()
4244 case ARM::VLD2d8: in getOperandLatency()
4245 case ARM::VLD2d16: in getOperandLatency()
4246 case ARM::VLD2d32: in getOperandLatency()
4247 case ARM::VLD2q8Pseudo: in getOperandLatency()
4248 case ARM::VLD2q16Pseudo: in getOperandLatency()
4249 case ARM::VLD2q32Pseudo: in getOperandLatency()
4250 case ARM::VLD2d8wb_fixed: in getOperandLatency()
4251 case ARM::VLD2d16wb_fixed: in getOperandLatency()
4252 case ARM::VLD2d32wb_fixed: in getOperandLatency()
4253 case ARM::VLD2q8PseudoWB_fixed: in getOperandLatency()
4254 case ARM::VLD2q16PseudoWB_fixed: in getOperandLatency()
4255 case ARM::VLD2q32PseudoWB_fixed: in getOperandLatency()
4256 case ARM::VLD2d8wb_register: in getOperandLatency()
4257 case ARM::VLD2d16wb_register: in getOperandLatency()
4258 case ARM::VLD2d32wb_register: in getOperandLatency()
4259 case ARM::VLD2q8PseudoWB_register: in getOperandLatency()
4260 case ARM::VLD2q16PseudoWB_register: in getOperandLatency()
4261 case ARM::VLD2q32PseudoWB_register: in getOperandLatency()
4262 case ARM::VLD3d8Pseudo: in getOperandLatency()
4263 case ARM::VLD3d16Pseudo: in getOperandLatency()
4264 case ARM::VLD3d32Pseudo: in getOperandLatency()
4265 case ARM::VLD1d8TPseudo: in getOperandLatency()
4266 case ARM::VLD1d16TPseudo: in getOperandLatency()
4267 case ARM::VLD1d32TPseudo: in getOperandLatency()
4268 case ARM::VLD1d64TPseudo: in getOperandLatency()
4269 case ARM::VLD1d64TPseudoWB_fixed: in getOperandLatency()
4270 case ARM::VLD1d64TPseudoWB_register: in getOperandLatency()
4271 case ARM::VLD3d8Pseudo_UPD: in getOperandLatency()
4272 case ARM::VLD3d16Pseudo_UPD: in getOperandLatency()
4273 case ARM::VLD3d32Pseudo_UPD: in getOperandLatency()
4274 case ARM::VLD3q8Pseudo_UPD: in getOperandLatency()
4275 case ARM::VLD3q16Pseudo_UPD: in getOperandLatency()
4276 case ARM::VLD3q32Pseudo_UPD: in getOperandLatency()
4277 case ARM::VLD3q8oddPseudo: in getOperandLatency()
4278 case ARM::VLD3q16oddPseudo: in getOperandLatency()
4279 case ARM::VLD3q32oddPseudo: in getOperandLatency()
4280 case ARM::VLD3q8oddPseudo_UPD: in getOperandLatency()
4281 case ARM::VLD3q16oddPseudo_UPD: in getOperandLatency()
4282 case ARM::VLD3q32oddPseudo_UPD: in getOperandLatency()
4283 case ARM::VLD4d8Pseudo: in getOperandLatency()
4284 case ARM::VLD4d16Pseudo: in getOperandLatency()
4285 case ARM::VLD4d32Pseudo: in getOperandLatency()
4286 case ARM::VLD1d8QPseudo: in getOperandLatency()
4287 case ARM::VLD1d16QPseudo: in getOperandLatency()
4288 case ARM::VLD1d32QPseudo: in getOperandLatency()
4289 case ARM::VLD1d64QPseudo: in getOperandLatency()
4290 case ARM::VLD1d64QPseudoWB_fixed: in getOperandLatency()
4291 case ARM::VLD1d64QPseudoWB_register: in getOperandLatency()
4292 case ARM::VLD1q8HighQPseudo: in getOperandLatency()
4293 case ARM::VLD1q8LowQPseudo_UPD: in getOperandLatency()
4294 case ARM::VLD1q8HighTPseudo: in getOperandLatency()
4295 case ARM::VLD1q8LowTPseudo_UPD: in getOperandLatency()
4296 case ARM::VLD1q16HighQPseudo: in getOperandLatency()
4297 case ARM::VLD1q16LowQPseudo_UPD: in getOperandLatency()
4298 case ARM::VLD1q16HighTPseudo: in getOperandLatency()
4299 case ARM::VLD1q16LowTPseudo_UPD: in getOperandLatency()
4300 case ARM::VLD1q32HighQPseudo: in getOperandLatency()
4301 case ARM::VLD1q32LowQPseudo_UPD: in getOperandLatency()
4302 case ARM::VLD1q32HighTPseudo: in getOperandLatency()
4303 case ARM::VLD1q32LowTPseudo_UPD: in getOperandLatency()
4304 case ARM::VLD1q64HighQPseudo: in getOperandLatency()
4305 case ARM::VLD1q64LowQPseudo_UPD: in getOperandLatency()
4306 case ARM::VLD1q64HighTPseudo: in getOperandLatency()
4307 case ARM::VLD1q64LowTPseudo_UPD: in getOperandLatency()
4308 case ARM::VLD4d8Pseudo_UPD: in getOperandLatency()
4309 case ARM::VLD4d16Pseudo_UPD: in getOperandLatency()
4310 case ARM::VLD4d32Pseudo_UPD: in getOperandLatency()
4311 case ARM::VLD4q8Pseudo_UPD: in getOperandLatency()
4312 case ARM::VLD4q16Pseudo_UPD: in getOperandLatency()
4313 case ARM::VLD4q32Pseudo_UPD: in getOperandLatency()
4314 case ARM::VLD4q8oddPseudo: in getOperandLatency()
4315 case ARM::VLD4q16oddPseudo: in getOperandLatency()
4316 case ARM::VLD4q32oddPseudo: in getOperandLatency()
4317 case ARM::VLD4q8oddPseudo_UPD: in getOperandLatency()
4318 case ARM::VLD4q16oddPseudo_UPD: in getOperandLatency()
4319 case ARM::VLD4q32oddPseudo_UPD: in getOperandLatency()
4320 case ARM::VLD1DUPq8: in getOperandLatency()
4321 case ARM::VLD1DUPq16: in getOperandLatency()
4322 case ARM::VLD1DUPq32: in getOperandLatency()
4323 case ARM::VLD1DUPq8wb_fixed: in getOperandLatency()
4324 case ARM::VLD1DUPq16wb_fixed: in getOperandLatency()
4325 case ARM::VLD1DUPq32wb_fixed: in getOperandLatency()
4326 case ARM::VLD1DUPq8wb_register: in getOperandLatency()
4327 case ARM::VLD1DUPq16wb_register: in getOperandLatency()
4328 case ARM::VLD1DUPq32wb_register: in getOperandLatency()
4329 case ARM::VLD2DUPd8: in getOperandLatency()
4330 case ARM::VLD2DUPd16: in getOperandLatency()
4331 case ARM::VLD2DUPd32: in getOperandLatency()
4332 case ARM::VLD2DUPd8wb_fixed: in getOperandLatency()
4333 case ARM::VLD2DUPd16wb_fixed: in getOperandLatency()
4334 case ARM::VLD2DUPd32wb_fixed: in getOperandLatency()
4335 case ARM::VLD2DUPd8wb_register: in getOperandLatency()
4336 case ARM::VLD2DUPd16wb_register: in getOperandLatency()
4337 case ARM::VLD2DUPd32wb_register: in getOperandLatency()
4338 case ARM::VLD2DUPq8EvenPseudo: in getOperandLatency()
4339 case ARM::VLD2DUPq8OddPseudo: in getOperandLatency()
4340 case ARM::VLD2DUPq16EvenPseudo: in getOperandLatency()
4341 case ARM::VLD2DUPq16OddPseudo: in getOperandLatency()
4342 case ARM::VLD2DUPq32EvenPseudo: in getOperandLatency()
4343 case ARM::VLD2DUPq32OddPseudo: in getOperandLatency()
4344 case ARM::VLD3DUPq8EvenPseudo: in getOperandLatency()
4345 case ARM::VLD3DUPq8OddPseudo: in getOperandLatency()
4346 case ARM::VLD3DUPq16EvenPseudo: in getOperandLatency()
4347 case ARM::VLD3DUPq16OddPseudo: in getOperandLatency()
4348 case ARM::VLD3DUPq32EvenPseudo: in getOperandLatency()
4349 case ARM::VLD3DUPq32OddPseudo: in getOperandLatency()
4350 case ARM::VLD4DUPd8Pseudo: in getOperandLatency()
4351 case ARM::VLD4DUPd16Pseudo: in getOperandLatency()
4352 case ARM::VLD4DUPd32Pseudo: in getOperandLatency()
4353 case ARM::VLD4DUPd8Pseudo_UPD: in getOperandLatency()
4354 case ARM::VLD4DUPd16Pseudo_UPD: in getOperandLatency()
4355 case ARM::VLD4DUPd32Pseudo_UPD: in getOperandLatency()
4356 case ARM::VLD4DUPq8EvenPseudo: in getOperandLatency()
4357 case ARM::VLD4DUPq8OddPseudo: in getOperandLatency()
4358 case ARM::VLD4DUPq16EvenPseudo: in getOperandLatency()
4359 case ARM::VLD4DUPq16OddPseudo: in getOperandLatency()
4360 case ARM::VLD4DUPq32EvenPseudo: in getOperandLatency()
4361 case ARM::VLD4DUPq32OddPseudo: in getOperandLatency()
4362 case ARM::VLD1LNq8Pseudo: in getOperandLatency()
4363 case ARM::VLD1LNq16Pseudo: in getOperandLatency()
4364 case ARM::VLD1LNq32Pseudo: in getOperandLatency()
4365 case ARM::VLD1LNq8Pseudo_UPD: in getOperandLatency()
4366 case ARM::VLD1LNq16Pseudo_UPD: in getOperandLatency()
4367 case ARM::VLD1LNq32Pseudo_UPD: in getOperandLatency()
4368 case ARM::VLD2LNd8Pseudo: in getOperandLatency()
4369 case ARM::VLD2LNd16Pseudo: in getOperandLatency()
4370 case ARM::VLD2LNd32Pseudo: in getOperandLatency()
4371 case ARM::VLD2LNq16Pseudo: in getOperandLatency()
4372 case ARM::VLD2LNq32Pseudo: in getOperandLatency()
4373 case ARM::VLD2LNd8Pseudo_UPD: in getOperandLatency()
4374 case ARM::VLD2LNd16Pseudo_UPD: in getOperandLatency()
4375 case ARM::VLD2LNd32Pseudo_UPD: in getOperandLatency()
4376 case ARM::VLD2LNq16Pseudo_UPD: in getOperandLatency()
4377 case ARM::VLD2LNq32Pseudo_UPD: in getOperandLatency()
4378 case ARM::VLD4LNd8Pseudo: in getOperandLatency()
4379 case ARM::VLD4LNd16Pseudo: in getOperandLatency()
4380 case ARM::VLD4LNd32Pseudo: in getOperandLatency()
4381 case ARM::VLD4LNq16Pseudo: in getOperandLatency()
4382 case ARM::VLD4LNq32Pseudo: in getOperandLatency()
4383 case ARM::VLD4LNd8Pseudo_UPD: in getOperandLatency()
4384 case ARM::VLD4LNd16Pseudo_UPD: in getOperandLatency()
4385 case ARM::VLD4LNd32Pseudo_UPD: in getOperandLatency()
4386 case ARM::VLD4LNq16Pseudo_UPD: in getOperandLatency()
4387 case ARM::VLD4LNq32Pseudo_UPD: in getOperandLatency()
4407 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getPredicationCost()
4430 if (I->getOpcode() != ARM::t2IT) in getInstrLatency()
4437 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getInstrLatency()
4479 case ARM::VLDMQIA: in getInstrLatency()
4480 case ARM::VSTMQIA: in getInstrLatency()
4610 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4616 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR || in getExecutionDomain()
4617 MI.getOpcode() == ARM::VMOVS)) in getExecutionDomain()
4639 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4642 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4646 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4679 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
4704 case ARM::VMOVD: in setExecutionDomain()
4722 MI.setDesc(get(ARM::VORRd)); in setExecutionDomain()
4728 case ARM::VMOVRS: in setExecutionDomain()
4745 MI.setDesc(get(ARM::VGETLNi32)); in setExecutionDomain()
4755 case ARM::VMOVSR: { in setExecutionDomain()
4775 MI.setDesc(get(ARM::VSETLNi32)); in setExecutionDomain()
4789 case ARM::VMOVS: { in setExecutionDomain()
4811 MI.setDesc(get(ARM::VDUPLN32d)); in setExecutionDomain()
4839 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32), in setExecutionDomain()
4858 MI.setDesc(get(ARM::VEXTd32)); in setExecutionDomain()
4919 case ARM::VLDRS: in getPartialRegUpdateClearance()
4920 case ARM::FCONSTS: in getPartialRegUpdateClearance()
4921 case ARM::VMOVSR: in getPartialRegUpdateClearance()
4922 case ARM::VMOVv8i8: in getPartialRegUpdateClearance()
4923 case ARM::VMOVv4i16: in getPartialRegUpdateClearance()
4924 case ARM::VMOVv2i32: in getPartialRegUpdateClearance()
4925 case ARM::VMOVv2f32: in getPartialRegUpdateClearance()
4926 case ARM::VMOVv1i64: in getPartialRegUpdateClearance()
4931 case ARM::VLD1LNd32: in getPartialRegUpdateClearance()
4948 } else if (ARM::SPRRegClass.contains(Reg)) { in getPartialRegUpdateClearance()
4950 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
4951 &ARM::DPRRegClass); in getPartialRegUpdateClearance()
4975 if (ARM::SPRRegClass.contains(Reg)) { in breakPartialRegDependency()
4976 DReg = ARM::D0 + (Reg - ARM::S0) / 2; in breakPartialRegDependency()
4980 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); in breakPartialRegDependency()
4991 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg) in breakPartialRegDependency()
4998 return Subtarget.getFeatureBits()[ARM::HasV6KOps]; in hasNOP()
5022 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
5031 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5036 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
5049 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
5059 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
5072 case ARM::VSETLNi32: in getInsertSubregLikeInputs()
5084 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1; in getInsertSubregLikeInputs()