Lines Matching refs:ARM
260 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
406 TII.get(ARM::VMOVSR), MoveReg) in ARMMoveToFPReg()
416 TII.get(ARM::VMOVRS), MoveReg) in ARMMoveToIntReg()
435 Opc = ARM::FCONSTD; in ARMMaterializeFP()
438 Opc = ARM::FCONSTS; in ARMMaterializeFP()
457 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP()
475 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt()
476 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt()
477 &ARM::GPRRegClass; in ARMMaterializeInt()
491 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt()
492 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt()
493 &ARM::GPRRegClass; in ARMMaterializeInt()
523 TII.get(ARM::t2LDRpci), ResultReg) in ARMMaterializeInt()
527 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
529 TII.get(ARM::LDRcp), ResultReg) in ARMMaterializeInt()
549 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass in ARMMaterializeGV()
550 : &ARM::GPRRegClass; in ARMMaterializeGV()
569 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel; in ARMMaterializeGV()
571 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm; in ARMMaterializeGV()
596 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci; in ARMMaterializeGV()
604 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
606 TII.get(ARM::LDRcp), DestReg) in ARMMaterializeGV()
612 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV()
630 TII.get(ARM::t2LDRi12), NewDestReg) in ARMMaterializeGV()
635 TII.get(ARM::LDRi12), NewDestReg) in ARMMaterializeGV()
677 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca()
852 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass in ARMSimplifyAddress()
853 : &ARM::GPRRegClass; in ARMSimplifyAddress()
855 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress()
932 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
934 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; in ARMEmitLoad()
937 Opc = ARM::LDRBi12; in ARMEmitLoad()
939 Opc = ARM::LDRSB; in ARMEmitLoad()
943 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; in ARMEmitLoad()
951 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
953 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; in ARMEmitLoad()
955 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
958 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; in ARMEmitLoad()
966 Opc = ARM::t2LDRi8; in ARMEmitLoad()
968 Opc = ARM::t2LDRi12; in ARMEmitLoad()
970 Opc = ARM::LDRi12; in ARMEmitLoad()
972 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; in ARMEmitLoad()
980 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; in ARMEmitLoad()
981 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; in ARMEmitLoad()
983 Opc = ARM::VLDRS; in ARMEmitLoad()
994 Opc = ARM::VLDRD; in ARMEmitLoad()
1014 TII.get(ARM::VMOVSR), MoveReg) in ARMEmitLoad()
1065 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass in ARMEmitStore()
1066 : &ARM::GPRRegClass); in ARMEmitStore()
1067 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; in ARMEmitStore()
1078 StrOpc = ARM::t2STRBi8; in ARMEmitStore()
1080 StrOpc = ARM::t2STRBi12; in ARMEmitStore()
1082 StrOpc = ARM::STRBi12; in ARMEmitStore()
1091 StrOpc = ARM::t2STRHi8; in ARMEmitStore()
1093 StrOpc = ARM::t2STRHi12; in ARMEmitStore()
1095 StrOpc = ARM::STRH; in ARMEmitStore()
1105 StrOpc = ARM::t2STRi8; in ARMEmitStore()
1107 StrOpc = ARM::t2STRi12; in ARMEmitStore()
1109 StrOpc = ARM::STRi12; in ARMEmitStore()
1118 TII.get(ARM::VMOVRS), MoveReg) in ARMEmitStore()
1122 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12; in ARMEmitStore()
1124 StrOpc = ARM::VSTRS; in ARMEmitStore()
1134 StrOpc = ARM::VSTRD; in ARMEmitStore()
1267 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; in SelectBranch()
1269 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1277 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; in SelectBranch()
1290 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; in SelectBranch()
1292 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1315 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; in SelectBranch()
1328 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; in SelectBranch()
1330 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1339 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; in SelectIndirectBr()
1403 CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS; in ARMEmitCmp()
1405 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES; in ARMEmitCmp()
1411 CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD; in ARMEmitCmp()
1413 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED; in ARMEmitCmp()
1423 CmpOpc = ARM::t2CMPrr; in ARMEmitCmp()
1425 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri; in ARMEmitCmp()
1428 CmpOpc = ARM::CMPrr; in ARMEmitCmp()
1430 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri; in ARMEmitCmp()
1475 TII.get(ARM::FMSTAT))); in ARMEmitCmp()
1495 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; in SelectCmp()
1496 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass in SelectCmp()
1497 : &ARM::GPRRegClass; in SelectCmp()
1504 .addImm(ARMPred).addReg(ARM::CPSR); in SelectCmp()
1521 unsigned Result = createResultReg(&ARM::DPRRegClass); in SelectFPExt()
1523 TII.get(ARM::VCVTDS), Result) in SelectFPExt()
1540 unsigned Result = createResultReg(&ARM::SPRRegClass); in SelectFPTrunc()
1542 TII.get(ARM::VCVTSD), Result) in SelectFPTrunc()
1581 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS; in SelectIToFP()
1583 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD; in SelectIToFP()
1607 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS; in SelectFPToI()
1609 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD; in SelectFPToI()
1660 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; in SelectSelect()
1670 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass; in SelectSelect()
1671 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr; in SelectSelect()
1673 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass; in SelectSelect()
1675 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; in SelectSelect()
1677 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi; in SelectSelect()
1688 .addReg(ARM::CPSR); in SelectSelect()
1696 .addReg(ARM::CPSR); in SelectSelect()
1772 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; in SelectBinaryIntOp()
1775 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr; in SelectBinaryIntOp()
1778 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr; in SelectBinaryIntOp()
1790 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectBinaryIntOp()
1824 Opc = is64bit ? ARM::VADDD : ARM::VADDS; in SelectBinaryFPOp()
1827 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; in SelectBinaryFPOp()
1830 Opc = is64bit ? ARM::VMULD : ARM::VMULS; in SelectBinaryFPOp()
2017 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
2032 Addr.Base.Reg = ARM::SP; in ProcessCallArgs()
2066 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
2188 return isThumb2 ? ARM::tBLXr : ARM::BLX; in ARMSelectCallOp()
2190 return isThumb2 ? ARM::tBL : ARM::BL; in ARMSelectCallOp()
2504 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; in SelectIntrinsicCall()
2505 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass in SelectIntrinsicCall()
2506 : &ARM::GPRRegClass; in SelectIntrinsicCall()
2581 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP)); in SelectIntrinsicCall()
2634 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass }, in ARMEmitIntExt()
2635 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass } in ARMEmitIntExt()
2647 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 }, in ARMEmitIntExt()
2648 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } }, in ARMEmitIntExt()
2649 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 }, in ARMEmitIntExt()
2650 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } }, in ARMEmitIntExt()
2651 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 }, in ARMEmitIntExt()
2652 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } } in ARMEmitIntExt()
2655 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2656 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2657 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2658 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2659 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2660 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2665 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2666 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2667 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2668 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
2669 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2670 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } in ARMEmitIntExt()
2673 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2674 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2675 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2676 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
2677 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2678 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } } in ARMEmitIntExt()
2700 assert(ARM::KILL != Opc && "Invalid table entry"); in ARMEmitIntExt()
2703 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) && in ARMEmitIntExt()
2708 bool setsCPSR = &ARM::tGPRRegClass == RC; in ARMEmitIntExt()
2709 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi; in ARMEmitIntExt()
2735 MIB.addReg(ARM::CPSR, RegState::Define); in ARMEmitIntExt()
2786 unsigned Opc = ARM::MOVsr; in SelectShift()
2797 Opc = ARM::MOVsi; in SelectShift()
2805 if (Opc == ARM::MOVsr) { in SelectShift()
2810 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectShift()
2817 if (Opc == ARM::MOVsi) in SelectShift()
2819 else if (Opc == ARM::MOVsr) { in SelectShift()
2909 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2910 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2911 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2912 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2913 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2978 unsigned TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); in ARMLowerPICELF()
2979 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp; in ARMLowerPICELF()
2984 if (Opc == ARM::LDRcp) in ARMLowerPICELF()
2990 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR in ARMLowerPICELF()
2991 : ARM::PICADD; in ARMLowerPICELF()
3003 TII.get(ARM::t2LDRi12), NewDestReg) in ARMLowerPICELF()
3063 ARM::R0, ARM::R1, ARM::R2, ARM::R3 in fastLowerArguments()
3066 const TargetRegisterClass *RC = &ARM::rGPRRegClass; in fastLowerArguments()
3086 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo, in createFastISel()