Lines Matching refs:ARM
72 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitSPUpdate()
98 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
101 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
173 case ARM::R8: in emitPrologue()
174 case ARM::R9: in emitPrologue()
175 case ARM::R10: in emitPrologue()
176 case ARM::R11: in emitPrologue()
182 case ARM::R4: in emitPrologue()
183 case ARM::R5: in emitPrologue()
184 case ARM::R6: in emitPrologue()
185 case ARM::R7: in emitPrologue()
186 case ARM::LR: in emitPrologue()
196 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { in emitPrologue()
235 case ARM::R8: in emitPrologue()
236 case ARM::R9: in emitPrologue()
237 case ARM::R10: in emitPrologue()
238 case ARM::R11: in emitPrologue()
239 case ARM::R12: in emitPrologue()
243 case ARM::R0: in emitPrologue()
244 case ARM::R1: in emitPrologue()
245 case ARM::R2: in emitPrologue()
246 case ARM::R3: in emitPrologue()
247 case ARM::R4: in emitPrologue()
248 case ARM::R5: in emitPrologue()
249 case ARM::R6: in emitPrologue()
250 case ARM::R7: in emitPrologue()
251 case ARM::LR: in emitPrologue()
265 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
266 .addReg(ARM::SP) in emitPrologue()
298 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr) in emitPrologue()
300 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { in emitPrologue()
316 case ARM::R8: in emitPrologue()
317 case ARM::R9: in emitPrologue()
318 case ARM::R10: in emitPrologue()
319 case ARM::R11: in emitPrologue()
320 case ARM::R12: { in emitPrologue()
363 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
364 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
367 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4) in emitPrologue()
368 .addDef(ARM::CPSR) in emitPrologue()
369 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
373 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4) in emitPrologue()
374 .addDef(ARM::CPSR) in emitPrologue()
375 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
379 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
380 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
391 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) in emitPrologue()
392 .addReg(ARM::SP) in emitPrologue()
407 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() && in isCSRestore()
410 else if (MI.getOpcode() == ARM::tPOP) { in isCSRestore()
412 } else if (MI.getOpcode() == ARM::tMOVr) { in isCSRestore()
415 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) && in isCSRestore()
416 ARM::hGPRRegClass.contains(Dst)); in isCSRestore()
464 assert(!MFI.getPristineRegs(MF).test(ARM::R4) && in emitEpilogue()
466 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
468 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
469 .addReg(ARM::R4) in emitEpilogue()
472 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
476 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET && in emitEpilogue()
477 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) { in emitEpilogue()
509 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
554 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB) in emitPopSpecialFixUp()
555 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET || in emitPopSpecialFixUp()
556 MBBI->getOpcode() == ARM::tPOP_RET); in emitPopSpecialFixUp()
560 assert(MBBI_prev->getOpcode() == ARM::tPOP); in emitPopSpecialFixUp()
562 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET) in emitPopSpecialFixUp()
570 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET) in emitPopSpecialFixUp()
573 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)) in emitPopSpecialFixUp()
579 MIB.addReg(ARM::PC, RegState::Define); in emitPopSpecialFixUp()
613 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp()
618 PopFriendly.set(ARM::R7); in emitPopSpecialFixUp()
624 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
626 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
627 GPRsNoLRSP.reset(ARM::SP); in emitPopSpecialFixUp()
628 GPRsNoLRSP.reset(ARM::PC); in emitPopSpecialFixUp()
638 if (PrevMBBI->getOpcode() == ARM::tPOP) { in emitPopSpecialFixUp()
656 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi)) in emitPopSpecialFixUp()
658 .addReg(ARM::SP) in emitPopSpecialFixUp()
662 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
663 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
676 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
682 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) { in emitPopSpecialFixUp()
686 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP)) in emitPopSpecialFixUp()
691 MO.getReg() != ARM::PC) { in emitPopSpecialFixUp()
701 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET)) in emitPopSpecialFixUp()
706 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)) in emitPopSpecialFixUp()
712 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
713 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
718 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
726 using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
761 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in spillCalleeSavedRegisters()
763 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in spillCalleeSavedRegisters()
769 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters()
776 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) in spillCalleeSavedRegisters()
784 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in spillCalleeSavedRegisters()
785 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
806 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
807 ARM::R5, ARM::R4, ARM::R3, in spillCalleeSavedRegisters()
808 ARM::R2, ARM::R1, ARM::R0}; in spillCalleeSavedRegisters()
809 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
825 BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in spillCalleeSavedRegisters()
835 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in spillCalleeSavedRegisters()
885 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in restoreCalleeSavedRegisters()
887 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in restoreCalleeSavedRegisters()
895 if ((ARM::tGPRRegClass.contains(Reg)) && in restoreCalleeSavedRegisters()
903 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) { in restoreCalleeSavedRegisters()
904 CopyRegs[ARM::R0] = true; in restoreCalleeSavedRegisters()
905 CopyRegs[ARM::R1] = true; in restoreCalleeSavedRegisters()
906 CopyRegs[ARM::R2] = true; in restoreCalleeSavedRegisters()
907 CopyRegs[ARM::R3] = true; in restoreCalleeSavedRegisters()
914 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3, in restoreCalleeSavedRegisters()
915 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
916 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11}; in restoreCalleeSavedRegisters()
933 BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in restoreCalleeSavedRegisters()
940 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in restoreCalleeSavedRegisters()
952 BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in restoreCalleeSavedRegisters()
960 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR)) in restoreCalleeSavedRegisters()
963 if (Reg == ARM::LR) { in restoreCalleeSavedRegisters()
966 MI->getOpcode() == ARM::TCRETURNdi || in restoreCalleeSavedRegisters()
967 MI->getOpcode() == ARM::TCRETURNri) in restoreCalleeSavedRegisters()
983 Reg = ARM::PC; in restoreCalleeSavedRegisters()
984 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); in restoreCalleeSavedRegisters()