Lines Matching refs:ARM
105 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
164 FPReg = ARM::SP; in reset()
230 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
287 return MRI->getSubReg(QReg, ARM::dsub_0); in getDRegFromQReg()
435 return getSTI().getFeatureBits()[ARM::ModeThumb]; in isThumb()
439 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbOne()
443 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbTwo()
447 return getSTI().getFeatureBits()[ARM::HasV4TOps]; in hasThumb()
451 return getSTI().getFeatureBits()[ARM::FeatureThumb2]; in hasThumb2()
455 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
459 return getSTI().getFeatureBits()[ARM::HasV6T2Ops]; in hasV6T2Ops()
463 return getSTI().getFeatureBits()[ARM::HasV6MOps]; in hasV6MOps()
467 return getSTI().getFeatureBits()[ARM::HasV7Ops]; in hasV7Ops()
471 return getSTI().getFeatureBits()[ARM::HasV8Ops]; in hasV8Ops()
475 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; in hasV8MBaseline()
479 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps]; in hasV8MMainline()
483 return getSTI().getFeatureBits()[ARM::Feature8MSecExt]; in has8MSecExt()
487 return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; in hasARM()
491 return getSTI().getFeatureBits()[ARM::FeatureDSP]; in hasDSP()
495 return getSTI().getFeatureBits()[ARM::FeatureD16]; in hasD16()
499 return getSTI().getFeatureBits()[ARM::HasV8_1aOps]; in hasV8_1aOps()
503 return getSTI().getFeatureBits()[ARM::FeatureRAS]; in hasRAS()
508 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); in SwitchMode()
515 return getSTI().getFeatureBits()[ARM::FeatureMClass]; in isMClass()
987 if(Memory.BaseRegNum != ARM::PC) return false; in isThumbMemPC()
1180 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) in isMem()
1183 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) in isMem()
1190 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1192 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1197 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedImm()
1240 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); in isPostIdxRegShifted()
1256 if (Memory.BaseRegNum != ARM::PC) in isMemPCRelImm12()
1448 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) in isT2MemRegOffset()
1500 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) in isMemThumbSPI()
1537 if (Memory.BaseRegNum == ARM::PC) return false; in isMemImm8Offset()
1558 if (Memory.BaseRegNum == ARM::PC) return false; in isMemNegImm8Offset()
1636 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPair()
1653 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] in isVecListDPairSpaced()
1682 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPairAllLanes()
2018 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2795 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONi8ReplicateOperands()
2796 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONi8ReplicateOperands()
2838 assert((Inst.getOpcode() == ARM::VMOVv4i16 || in addNEONvmovi16ReplicateOperands()
2839 Inst.getOpcode() == ARM::VMOVv8i16 || in addNEONvmovi16ReplicateOperands()
2840 Inst.getOpcode() == ARM::VMVNv4i16 || in addNEONvmovi16ReplicateOperands()
2841 Inst.getOpcode() == ARM::VMVNv8i16) && in addNEONvmovi16ReplicateOperands()
2862 assert((Inst.getOpcode() == ARM::VMOVv2i32 || in addNEONvmovi32ReplicateOperands()
2863 Inst.getOpcode() == ARM::VMOVv4i32 || in addNEONvmovi32ReplicateOperands()
2864 Inst.getOpcode() == ARM::VMVNv2i32 || in addNEONvmovi32ReplicateOperands()
2865 Inst.getOpcode() == ARM::VMVNv4i32) && in addNEONvmovi32ReplicateOperands()
3047 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) in CreateRegList()
3049 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. in CreateRegList()
3391 .Case("r13", ARM::SP) in tryParseRegister()
3392 .Case("r14", ARM::LR) in tryParseRegister()
3393 .Case("r15", ARM::PC) in tryParseRegister()
3394 .Case("ip", ARM::R12) in tryParseRegister()
3396 .Case("a1", ARM::R0) in tryParseRegister()
3397 .Case("a2", ARM::R1) in tryParseRegister()
3398 .Case("a3", ARM::R2) in tryParseRegister()
3399 .Case("a4", ARM::R3) in tryParseRegister()
3400 .Case("v1", ARM::R4) in tryParseRegister()
3401 .Case("v2", ARM::R5) in tryParseRegister()
3402 .Case("v3", ARM::R6) in tryParseRegister()
3403 .Case("v4", ARM::R7) in tryParseRegister()
3404 .Case("v5", ARM::R8) in tryParseRegister()
3405 .Case("v6", ARM::R9) in tryParseRegister()
3406 .Case("v7", ARM::R10) in tryParseRegister()
3407 .Case("v8", ARM::R11) in tryParseRegister()
3408 .Case("sb", ARM::R9) in tryParseRegister()
3409 .Case("sl", ARM::R10) in tryParseRegister()
3410 .Case("fp", ARM::R11) in tryParseRegister()
3426 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31) in tryParseRegister()
3739 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in getNextRegister()
3743 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
3744 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
3745 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
3746 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
3747 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
3748 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
3749 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
3750 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
3775 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
3782 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
3783 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; in parseRegisterList()
3784 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) in parseRegisterList()
3785 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; in parseRegisterList()
3786 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) in parseRegisterList()
3787 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; in parseRegisterList()
3807 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseRegisterList()
3837 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
3846 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
3857 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && in parseRegisterList()
3952 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { in parseVectorList()
3972 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
3979 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
3980 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
3984 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
3985 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
4017 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4047 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseVectorList()
4054 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { in parseVectorList()
4093 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4158 &ARMMCRegisterClasses[ARM::DPairRegClassID] : in parseVectorList()
4159 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; in parseVectorList()
4160 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4170 &ARMMCRegisterClasses[ARM::DPairRegClassID] : in parseVectorList()
4171 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; in parseVectorList()
4172 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
5010 case ARM::tB: in cvtThumbBranches()
5011 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; in cvtThumbBranches()
5013 case ARM::t2B: in cvtThumbBranches()
5014 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; in cvtThumbBranches()
5024 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
5025 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
5032 case ARM::tB: in cvtThumbBranches()
5033 case ARM::tBcc: in cvtThumbBranches()
5034 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
5036 case ARM::t2B: in cvtThumbBranches()
5037 case ARM::t2Bcc: in cvtThumbBranches()
5038 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
5046 case ARM::tB: { in cvtThumbBranches()
5049 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
5053 case ARM::tBcc: { in cvtThumbBranches()
5056 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
5794 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || in tryConvertingToTwoOperandForm()
5795 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
5797 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || in tryConvertingToTwoOperandForm()
5798 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
5799 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && in tryConvertingToTwoOperandForm()
5824 ((Mnemonic == "add" && Op4Reg != ARM::SP) || in tryConvertingToTwoOperandForm()
5888 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5913 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
5965 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5988 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in shouldOmitPredicateOperand()
5990 ARMMCRegisterClasses[ARM::QPRRegClassID].contains( in shouldOmitPredicateOperand()
6039 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()
6049 if (Op2.getReg() == ARM::PC) in fixupGNULDRDAlias()
6052 if (!PairedReg || PairedReg == ARM::PC || in fixupGNULDRDAlias()
6053 (PairedReg == ARM::SP && !hasV8Ops())) in fixupGNULDRDAlias()
6155 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
6264 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
6279 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, in ParseInstruction()
6280 &(MRI->getRegClass(ARM::GPRPairRegClassID))); in ParseInstruction()
6297 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
6299 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
6341 return Inst.getOpcode() == ARM::tBKPT || in instIsBreakpoint()
6342 Inst.getOpcode() == ARM::BKPT || in instIsBreakpoint()
6343 Inst.getOpcode() == ARM::tHLT || in instIsBreakpoint()
6344 Inst.getOpcode() == ARM::HLT; in instIsBreakpoint()
6353 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetLDMRegList()
6354 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); in validatetLDMRegList()
6355 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetLDMRegList()
6372 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetSTMRegList()
6373 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetSTMRegList()
6475 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && in validateInstruction()
6476 Inst.getOpcode() != ARM::t2Bcc) { in validateInstruction()
6492 case ARM::t2IT: { in validateInstruction()
6507 case ARM::LDRD: in validateInstruction()
6512 case ARM::LDRD_PRE: in validateInstruction()
6513 case ARM::LDRD_POST: in validateInstruction()
6518 case ARM::t2LDRDi8: in validateInstruction()
6523 case ARM::t2LDRD_PRE: in validateInstruction()
6524 case ARM::t2LDRD_POST: in validateInstruction()
6529 case ARM::t2BXJ: { in validateInstruction()
6532 if (RmReg == ARM::SP && !hasV8Ops()) in validateInstruction()
6537 case ARM::STRD: in validateInstruction()
6542 case ARM::STRD_PRE: in validateInstruction()
6543 case ARM::STRD_POST: in validateInstruction()
6548 case ARM::t2STRD_PRE: in validateInstruction()
6549 case ARM::t2STRD_POST: in validateInstruction()
6554 case ARM::STR_PRE_IMM: in validateInstruction()
6555 case ARM::STR_PRE_REG: in validateInstruction()
6556 case ARM::t2STR_PRE: in validateInstruction()
6557 case ARM::STR_POST_IMM: in validateInstruction()
6558 case ARM::STR_POST_REG: in validateInstruction()
6559 case ARM::t2STR_POST: in validateInstruction()
6560 case ARM::STRH_PRE: in validateInstruction()
6561 case ARM::t2STRH_PRE: in validateInstruction()
6562 case ARM::STRH_POST: in validateInstruction()
6563 case ARM::t2STRH_POST: in validateInstruction()
6564 case ARM::STRB_PRE_IMM: in validateInstruction()
6565 case ARM::STRB_PRE_REG: in validateInstruction()
6566 case ARM::t2STRB_PRE: in validateInstruction()
6567 case ARM::STRB_POST_IMM: in validateInstruction()
6568 case ARM::STRB_POST_REG: in validateInstruction()
6569 case ARM::t2STRB_POST: { in validateInstruction()
6579 case ARM::LDR_PRE_IMM: in validateInstruction()
6580 case ARM::LDR_PRE_REG: in validateInstruction()
6581 case ARM::t2LDR_PRE: in validateInstruction()
6582 case ARM::LDR_POST_IMM: in validateInstruction()
6583 case ARM::LDR_POST_REG: in validateInstruction()
6584 case ARM::t2LDR_POST: in validateInstruction()
6585 case ARM::LDRH_PRE: in validateInstruction()
6586 case ARM::t2LDRH_PRE: in validateInstruction()
6587 case ARM::LDRH_POST: in validateInstruction()
6588 case ARM::t2LDRH_POST: in validateInstruction()
6589 case ARM::LDRSH_PRE: in validateInstruction()
6590 case ARM::t2LDRSH_PRE: in validateInstruction()
6591 case ARM::LDRSH_POST: in validateInstruction()
6592 case ARM::t2LDRSH_POST: in validateInstruction()
6593 case ARM::LDRB_PRE_IMM: in validateInstruction()
6594 case ARM::LDRB_PRE_REG: in validateInstruction()
6595 case ARM::t2LDRB_PRE: in validateInstruction()
6596 case ARM::LDRB_POST_IMM: in validateInstruction()
6597 case ARM::LDRB_POST_REG: in validateInstruction()
6598 case ARM::t2LDRB_POST: in validateInstruction()
6599 case ARM::LDRSB_PRE: in validateInstruction()
6600 case ARM::t2LDRSB_PRE: in validateInstruction()
6601 case ARM::LDRSB_POST: in validateInstruction()
6602 case ARM::t2LDRSB_POST: { in validateInstruction()
6612 case ARM::SBFX: in validateInstruction()
6613 case ARM::t2SBFX: in validateInstruction()
6614 case ARM::UBFX: in validateInstruction()
6615 case ARM::t2UBFX: { in validateInstruction()
6625 case ARM::tLDMIA: { in validateInstruction()
6655 case ARM::LDMIA_UPD: in validateInstruction()
6656 case ARM::LDMDB_UPD: in validateInstruction()
6657 case ARM::LDMIB_UPD: in validateInstruction()
6658 case ARM::LDMDA_UPD: in validateInstruction()
6667 case ARM::t2LDMIA: in validateInstruction()
6668 case ARM::t2LDMDB: in validateInstruction()
6672 case ARM::t2STMIA: in validateInstruction()
6673 case ARM::t2STMDB: in validateInstruction()
6677 case ARM::t2LDMIA_UPD: in validateInstruction()
6678 case ARM::t2LDMDB_UPD: in validateInstruction()
6679 case ARM::t2STMIA_UPD: in validateInstruction()
6680 case ARM::t2STMDB_UPD: in validateInstruction()
6685 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in validateInstruction()
6694 case ARM::sysLDMIA_UPD: in validateInstruction()
6695 case ARM::sysLDMDA_UPD: in validateInstruction()
6696 case ARM::sysLDMDB_UPD: in validateInstruction()
6697 case ARM::sysLDMIB_UPD: in validateInstruction()
6698 if (!listContainsReg(Inst, 3, ARM::PC)) in validateInstruction()
6703 case ARM::sysSTMIA_UPD: in validateInstruction()
6704 case ARM::sysSTMDA_UPD: in validateInstruction()
6705 case ARM::sysSTMDB_UPD: in validateInstruction()
6706 case ARM::sysSTMIB_UPD: in validateInstruction()
6709 case ARM::tMUL: in validateInstruction()
6730 case ARM::tPOP: { in validateInstruction()
6732 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && in validateInstruction()
6740 case ARM::tPUSH: { in validateInstruction()
6742 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && in validateInstruction()
6750 case ARM::tSTMIA_UPD: { in validateInstruction()
6769 case ARM::tADDrSP: in validateInstruction()
6780 case ARM::tB: in validateInstruction()
6784 case ARM::t2B: { in validateInstruction()
6791 case ARM::tBcc: in validateInstruction()
6795 case ARM::t2Bcc: { in validateInstruction()
6801 case ARM::tCBZ: in validateInstruction()
6802 case ARM::tCBNZ: { in validateInstruction()
6807 case ARM::MOVi16: in validateInstruction()
6808 case ARM::MOVTi16: in validateInstruction()
6809 case ARM::t2MOVi16: in validateInstruction()
6810 case ARM::t2MOVTi16: in validateInstruction()
6832 case ARM::HINT: in validateInstruction()
6833 case ARM::t2HINT: { in validateInstruction()
6848 case ARM::DSB: in validateInstruction()
6849 case ARM::t2DSB: { in validateInstruction()
6868 case ARM::VMOVRRS: { in validateInstruction()
6877 case ARM::VMOVSRR: { in validateInstruction()
6886 case ARM::VLDMDIA: in validateInstruction()
6887 case ARM::VSTMDIA: { in validateInstruction()
6904 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
6905 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
6906 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
6907 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
6908 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
6909 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
6910 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; in getRealVSTOpcode()
6911 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; in getRealVSTOpcode()
6912 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; in getRealVSTOpcode()
6915 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
6916 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
6917 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
6918 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
6919 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
6921 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
6922 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
6923 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
6924 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
6925 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
6927 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; in getRealVSTOpcode()
6928 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; in getRealVSTOpcode()
6929 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; in getRealVSTOpcode()
6930 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; in getRealVSTOpcode()
6931 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; in getRealVSTOpcode()
6934 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
6935 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
6936 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
6937 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
6938 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
6939 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
6940 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
6941 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
6942 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
6943 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
6944 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; in getRealVSTOpcode()
6945 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; in getRealVSTOpcode()
6946 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; in getRealVSTOpcode()
6947 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; in getRealVSTOpcode()
6948 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; in getRealVSTOpcode()
6951 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
6952 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
6953 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
6954 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
6955 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
6956 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
6957 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
6958 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
6959 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
6960 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
6961 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
6962 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
6963 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; in getRealVSTOpcode()
6964 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; in getRealVSTOpcode()
6965 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; in getRealVSTOpcode()
6966 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; in getRealVSTOpcode()
6967 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; in getRealVSTOpcode()
6968 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; in getRealVSTOpcode()
6971 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
6972 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
6973 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
6974 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
6975 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
6976 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
6977 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
6978 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
6979 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
6980 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
6981 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; in getRealVSTOpcode()
6982 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; in getRealVSTOpcode()
6983 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; in getRealVSTOpcode()
6984 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; in getRealVSTOpcode()
6985 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; in getRealVSTOpcode()
6988 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
6989 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
6990 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
6991 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
6992 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
6993 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
6994 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
6995 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
6996 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
6997 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
6998 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
6999 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
7000 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; in getRealVSTOpcode()
7001 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; in getRealVSTOpcode()
7002 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; in getRealVSTOpcode()
7003 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; in getRealVSTOpcode()
7004 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; in getRealVSTOpcode()
7005 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; in getRealVSTOpcode()
7013 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
7014 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
7015 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
7016 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
7017 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
7018 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
7019 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; in getRealVLDOpcode()
7020 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; in getRealVLDOpcode()
7021 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; in getRealVLDOpcode()
7024 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
7025 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
7026 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
7027 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
7028 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
7029 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
7030 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
7031 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
7032 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
7033 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
7034 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; in getRealVLDOpcode()
7035 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; in getRealVLDOpcode()
7036 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; in getRealVLDOpcode()
7037 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; in getRealVLDOpcode()
7038 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; in getRealVLDOpcode()
7041 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
7042 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
7043 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
7044 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
7045 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
7046 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
7047 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
7048 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
7049 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
7050 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
7051 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
7052 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
7053 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; in getRealVLDOpcode()
7054 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; in getRealVLDOpcode()
7055 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; in getRealVLDOpcode()
7056 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; in getRealVLDOpcode()
7057 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; in getRealVLDOpcode()
7058 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; in getRealVLDOpcode()
7061 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
7062 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
7063 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
7064 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
7065 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
7066 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
7067 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
7068 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
7069 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
7070 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
7071 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; in getRealVLDOpcode()
7072 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; in getRealVLDOpcode()
7073 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; in getRealVLDOpcode()
7074 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; in getRealVLDOpcode()
7075 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; in getRealVLDOpcode()
7078 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
7079 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
7080 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
7081 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
7082 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
7083 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
7084 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
7085 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
7086 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
7087 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
7088 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
7089 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
7090 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; in getRealVLDOpcode()
7091 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; in getRealVLDOpcode()
7092 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; in getRealVLDOpcode()
7093 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; in getRealVLDOpcode()
7094 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; in getRealVLDOpcode()
7095 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; in getRealVLDOpcode()
7098 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
7099 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
7100 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
7101 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
7102 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
7103 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
7104 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
7105 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
7106 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
7107 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
7108 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; in getRealVLDOpcode()
7109 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; in getRealVLDOpcode()
7110 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; in getRealVLDOpcode()
7111 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; in getRealVLDOpcode()
7112 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; in getRealVLDOpcode()
7115 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
7116 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
7117 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
7118 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
7119 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
7120 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
7121 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
7122 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
7123 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
7124 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
7125 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
7126 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
7127 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; in getRealVLDOpcode()
7128 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; in getRealVLDOpcode()
7129 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; in getRealVLDOpcode()
7130 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; in getRealVLDOpcode()
7131 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; in getRealVLDOpcode()
7132 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; in getRealVLDOpcode()
7135 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
7136 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
7137 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
7138 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
7139 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
7140 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
7141 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
7142 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
7143 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
7144 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
7145 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
7146 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
7147 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; in getRealVLDOpcode()
7148 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; in getRealVLDOpcode()
7149 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; in getRealVLDOpcode()
7150 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; in getRealVLDOpcode()
7151 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; in getRealVLDOpcode()
7152 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; in getRealVLDOpcode()
7172 case ARM::LDRT_POST: in processInstruction()
7173 case ARM::LDRBT_POST: { in processInstruction()
7175 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM in processInstruction()
7176 : ARM::LDRBT_POST_IMM; in processInstruction()
7190 case ARM::STRT_POST: in processInstruction()
7191 case ARM::STRBT_POST: { in processInstruction()
7193 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM in processInstruction()
7194 : ARM::STRBT_POST_IMM; in processInstruction()
7208 case ARM::ADDri: { in processInstruction()
7209 if (Inst.getOperand(1).getReg() != ARM::PC || in processInstruction()
7214 TmpInst.setOpcode(ARM::ADR); in processInstruction()
7245 case ARM::t2LDRpcrel: in processInstruction()
7250 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
7252 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
7254 case ARM::t2LDRBpcrel: in processInstruction()
7255 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
7257 case ARM::t2LDRHpcrel: in processInstruction()
7258 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
7260 case ARM::t2LDRSBpcrel: in processInstruction()
7261 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
7263 case ARM::t2LDRSHpcrel: in processInstruction()
7264 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
7266 case ARM::LDRConstPool: in processInstruction()
7267 case ARM::tLDRConstPool: in processInstruction()
7268 case ARM::t2LDRConstPool: { in processInstruction()
7273 if (Inst.getOpcode() == ARM::LDRConstPool) in processInstruction()
7274 TmpInst.setOpcode(ARM::LDRi12); in processInstruction()
7275 else if (Inst.getOpcode() == ARM::tLDRConstPool) in processInstruction()
7276 TmpInst.setOpcode(ARM::tLDRpci); in processInstruction()
7277 else if (Inst.getOpcode() == ARM::t2LDRConstPool) in processInstruction()
7278 TmpInst.setOpcode(ARM::t2LDRpci); in processInstruction()
7286 Inst.getOperand(0).getReg() != ARM::PC && in processInstruction()
7287 Inst.getOperand(0).getReg() != ARM::SP) { in processInstruction()
7292 if (Inst.getOpcode() == ARM::LDRConstPool) { in processInstruction()
7296 TmpInst.setOpcode(ARM::MOVi); in processInstruction()
7300 TmpInst.setOpcode(ARM::MVNi); in processInstruction()
7304 TmpInst.setOpcode(ARM::MOVi16); in processInstruction()
7314 TmpInst.setOpcode(ARM::t2MOVi); in processInstruction()
7317 TmpInst.setOpcode(ARM::t2MVNi); in processInstruction()
7322 TmpInst.setOpcode(ARM::t2MOVi16); in processInstruction()
7345 if (TmpInst.getOpcode() == ARM::LDRi12) in processInstruction()
7353 case ARM::VST1LNdWB_register_Asm_8: in processInstruction()
7354 case ARM::VST1LNdWB_register_Asm_16: in processInstruction()
7355 case ARM::VST1LNdWB_register_Asm_32: { in processInstruction()
7373 case ARM::VST2LNdWB_register_Asm_8: in processInstruction()
7374 case ARM::VST2LNdWB_register_Asm_16: in processInstruction()
7375 case ARM::VST2LNdWB_register_Asm_32: in processInstruction()
7376 case ARM::VST2LNqWB_register_Asm_16: in processInstruction()
7377 case ARM::VST2LNqWB_register_Asm_32: { in processInstruction()
7397 case ARM::VST3LNdWB_register_Asm_8: in processInstruction()
7398 case ARM::VST3LNdWB_register_Asm_16: in processInstruction()
7399 case ARM::VST3LNdWB_register_Asm_32: in processInstruction()
7400 case ARM::VST3LNqWB_register_Asm_16: in processInstruction()
7401 case ARM::VST3LNqWB_register_Asm_32: { in processInstruction()
7423 case ARM::VST4LNdWB_register_Asm_8: in processInstruction()
7424 case ARM::VST4LNdWB_register_Asm_16: in processInstruction()
7425 case ARM::VST4LNdWB_register_Asm_32: in processInstruction()
7426 case ARM::VST4LNqWB_register_Asm_16: in processInstruction()
7427 case ARM::VST4LNqWB_register_Asm_32: { in processInstruction()
7451 case ARM::VST1LNdWB_fixed_Asm_8: in processInstruction()
7452 case ARM::VST1LNdWB_fixed_Asm_16: in processInstruction()
7453 case ARM::VST1LNdWB_fixed_Asm_32: { in processInstruction()
7471 case ARM::VST2LNdWB_fixed_Asm_8: in processInstruction()
7472 case ARM::VST2LNdWB_fixed_Asm_16: in processInstruction()
7473 case ARM::VST2LNdWB_fixed_Asm_32: in processInstruction()
7474 case ARM::VST2LNqWB_fixed_Asm_16: in processInstruction()
7475 case ARM::VST2LNqWB_fixed_Asm_32: { in processInstruction()
7495 case ARM::VST3LNdWB_fixed_Asm_8: in processInstruction()
7496 case ARM::VST3LNdWB_fixed_Asm_16: in processInstruction()
7497 case ARM::VST3LNdWB_fixed_Asm_32: in processInstruction()
7498 case ARM::VST3LNqWB_fixed_Asm_16: in processInstruction()
7499 case ARM::VST3LNqWB_fixed_Asm_32: { in processInstruction()
7521 case ARM::VST4LNdWB_fixed_Asm_8: in processInstruction()
7522 case ARM::VST4LNdWB_fixed_Asm_16: in processInstruction()
7523 case ARM::VST4LNdWB_fixed_Asm_32: in processInstruction()
7524 case ARM::VST4LNqWB_fixed_Asm_16: in processInstruction()
7525 case ARM::VST4LNqWB_fixed_Asm_32: { in processInstruction()
7549 case ARM::VST1LNdAsm_8: in processInstruction()
7550 case ARM::VST1LNdAsm_16: in processInstruction()
7551 case ARM::VST1LNdAsm_32: { in processInstruction()
7567 case ARM::VST2LNdAsm_8: in processInstruction()
7568 case ARM::VST2LNdAsm_16: in processInstruction()
7569 case ARM::VST2LNdAsm_32: in processInstruction()
7570 case ARM::VST2LNqAsm_16: in processInstruction()
7571 case ARM::VST2LNqAsm_32: { in processInstruction()
7589 case ARM::VST3LNdAsm_8: in processInstruction()
7590 case ARM::VST3LNdAsm_16: in processInstruction()
7591 case ARM::VST3LNdAsm_32: in processInstruction()
7592 case ARM::VST3LNqAsm_16: in processInstruction()
7593 case ARM::VST3LNqAsm_32: { in processInstruction()
7613 case ARM::VST4LNdAsm_8: in processInstruction()
7614 case ARM::VST4LNdAsm_16: in processInstruction()
7615 case ARM::VST4LNdAsm_32: in processInstruction()
7616 case ARM::VST4LNqAsm_16: in processInstruction()
7617 case ARM::VST4LNqAsm_32: { in processInstruction()
7640 case ARM::VLD1LNdWB_register_Asm_8: in processInstruction()
7641 case ARM::VLD1LNdWB_register_Asm_16: in processInstruction()
7642 case ARM::VLD1LNdWB_register_Asm_32: { in processInstruction()
7661 case ARM::VLD2LNdWB_register_Asm_8: in processInstruction()
7662 case ARM::VLD2LNdWB_register_Asm_16: in processInstruction()
7663 case ARM::VLD2LNdWB_register_Asm_32: in processInstruction()
7664 case ARM::VLD2LNqWB_register_Asm_16: in processInstruction()
7665 case ARM::VLD2LNqWB_register_Asm_32: { in processInstruction()
7688 case ARM::VLD3LNdWB_register_Asm_8: in processInstruction()
7689 case ARM::VLD3LNdWB_register_Asm_16: in processInstruction()
7690 case ARM::VLD3LNdWB_register_Asm_32: in processInstruction()
7691 case ARM::VLD3LNqWB_register_Asm_16: in processInstruction()
7692 case ARM::VLD3LNqWB_register_Asm_32: { in processInstruction()
7719 case ARM::VLD4LNdWB_register_Asm_8: in processInstruction()
7720 case ARM::VLD4LNdWB_register_Asm_16: in processInstruction()
7721 case ARM::VLD4LNdWB_register_Asm_32: in processInstruction()
7722 case ARM::VLD4LNqWB_register_Asm_16: in processInstruction()
7723 case ARM::VLD4LNqWB_register_Asm_32: { in processInstruction()
7754 case ARM::VLD1LNdWB_fixed_Asm_8: in processInstruction()
7755 case ARM::VLD1LNdWB_fixed_Asm_16: in processInstruction()
7756 case ARM::VLD1LNdWB_fixed_Asm_32: { in processInstruction()
7775 case ARM::VLD2LNdWB_fixed_Asm_8: in processInstruction()
7776 case ARM::VLD2LNdWB_fixed_Asm_16: in processInstruction()
7777 case ARM::VLD2LNdWB_fixed_Asm_32: in processInstruction()
7778 case ARM::VLD2LNqWB_fixed_Asm_16: in processInstruction()
7779 case ARM::VLD2LNqWB_fixed_Asm_32: { in processInstruction()
7802 case ARM::VLD3LNdWB_fixed_Asm_8: in processInstruction()
7803 case ARM::VLD3LNdWB_fixed_Asm_16: in processInstruction()
7804 case ARM::VLD3LNdWB_fixed_Asm_32: in processInstruction()
7805 case ARM::VLD3LNqWB_fixed_Asm_16: in processInstruction()
7806 case ARM::VLD3LNqWB_fixed_Asm_32: { in processInstruction()
7833 case ARM::VLD4LNdWB_fixed_Asm_8: in processInstruction()
7834 case ARM::VLD4LNdWB_fixed_Asm_16: in processInstruction()
7835 case ARM::VLD4LNdWB_fixed_Asm_32: in processInstruction()
7836 case ARM::VLD4LNqWB_fixed_Asm_16: in processInstruction()
7837 case ARM::VLD4LNqWB_fixed_Asm_32: { in processInstruction()
7868 case ARM::VLD1LNdAsm_8: in processInstruction()
7869 case ARM::VLD1LNdAsm_16: in processInstruction()
7870 case ARM::VLD1LNdAsm_32: { in processInstruction()
7887 case ARM::VLD2LNdAsm_8: in processInstruction()
7888 case ARM::VLD2LNdAsm_16: in processInstruction()
7889 case ARM::VLD2LNdAsm_32: in processInstruction()
7890 case ARM::VLD2LNqAsm_16: in processInstruction()
7891 case ARM::VLD2LNqAsm_32: { in processInstruction()
7912 case ARM::VLD3LNdAsm_8: in processInstruction()
7913 case ARM::VLD3LNdAsm_16: in processInstruction()
7914 case ARM::VLD3LNdAsm_32: in processInstruction()
7915 case ARM::VLD3LNqAsm_16: in processInstruction()
7916 case ARM::VLD3LNqAsm_32: { in processInstruction()
7941 case ARM::VLD4LNdAsm_8: in processInstruction()
7942 case ARM::VLD4LNdAsm_16: in processInstruction()
7943 case ARM::VLD4LNdAsm_32: in processInstruction()
7944 case ARM::VLD4LNqAsm_16: in processInstruction()
7945 case ARM::VLD4LNqAsm_32: { in processInstruction()
7975 case ARM::VLD3DUPdAsm_8: in processInstruction()
7976 case ARM::VLD3DUPdAsm_16: in processInstruction()
7977 case ARM::VLD3DUPdAsm_32: in processInstruction()
7978 case ARM::VLD3DUPqAsm_8: in processInstruction()
7979 case ARM::VLD3DUPqAsm_16: in processInstruction()
7980 case ARM::VLD3DUPqAsm_32: { in processInstruction()
7997 case ARM::VLD3DUPdWB_fixed_Asm_8: in processInstruction()
7998 case ARM::VLD3DUPdWB_fixed_Asm_16: in processInstruction()
7999 case ARM::VLD3DUPdWB_fixed_Asm_32: in processInstruction()
8000 case ARM::VLD3DUPqWB_fixed_Asm_8: in processInstruction()
8001 case ARM::VLD3DUPqWB_fixed_Asm_16: in processInstruction()
8002 case ARM::VLD3DUPqWB_fixed_Asm_32: { in processInstruction()
8021 case ARM::VLD3DUPdWB_register_Asm_8: in processInstruction()
8022 case ARM::VLD3DUPdWB_register_Asm_16: in processInstruction()
8023 case ARM::VLD3DUPdWB_register_Asm_32: in processInstruction()
8024 case ARM::VLD3DUPqWB_register_Asm_8: in processInstruction()
8025 case ARM::VLD3DUPqWB_register_Asm_16: in processInstruction()
8026 case ARM::VLD3DUPqWB_register_Asm_32: { in processInstruction()
8046 case ARM::VLD3dAsm_8: in processInstruction()
8047 case ARM::VLD3dAsm_16: in processInstruction()
8048 case ARM::VLD3dAsm_32: in processInstruction()
8049 case ARM::VLD3qAsm_8: in processInstruction()
8050 case ARM::VLD3qAsm_16: in processInstruction()
8051 case ARM::VLD3qAsm_32: { in processInstruction()
8068 case ARM::VLD3dWB_fixed_Asm_8: in processInstruction()
8069 case ARM::VLD3dWB_fixed_Asm_16: in processInstruction()
8070 case ARM::VLD3dWB_fixed_Asm_32: in processInstruction()
8071 case ARM::VLD3qWB_fixed_Asm_8: in processInstruction()
8072 case ARM::VLD3qWB_fixed_Asm_16: in processInstruction()
8073 case ARM::VLD3qWB_fixed_Asm_32: { in processInstruction()
8092 case ARM::VLD3dWB_register_Asm_8: in processInstruction()
8093 case ARM::VLD3dWB_register_Asm_16: in processInstruction()
8094 case ARM::VLD3dWB_register_Asm_32: in processInstruction()
8095 case ARM::VLD3qWB_register_Asm_8: in processInstruction()
8096 case ARM::VLD3qWB_register_Asm_16: in processInstruction()
8097 case ARM::VLD3qWB_register_Asm_32: { in processInstruction()
8117 case ARM::VLD4DUPdAsm_8: in processInstruction()
8118 case ARM::VLD4DUPdAsm_16: in processInstruction()
8119 case ARM::VLD4DUPdAsm_32: in processInstruction()
8120 case ARM::VLD4DUPqAsm_8: in processInstruction()
8121 case ARM::VLD4DUPqAsm_16: in processInstruction()
8122 case ARM::VLD4DUPqAsm_32: { in processInstruction()
8141 case ARM::VLD4DUPdWB_fixed_Asm_8: in processInstruction()
8142 case ARM::VLD4DUPdWB_fixed_Asm_16: in processInstruction()
8143 case ARM::VLD4DUPdWB_fixed_Asm_32: in processInstruction()
8144 case ARM::VLD4DUPqWB_fixed_Asm_8: in processInstruction()
8145 case ARM::VLD4DUPqWB_fixed_Asm_16: in processInstruction()
8146 case ARM::VLD4DUPqWB_fixed_Asm_32: { in processInstruction()
8167 case ARM::VLD4DUPdWB_register_Asm_8: in processInstruction()
8168 case ARM::VLD4DUPdWB_register_Asm_16: in processInstruction()
8169 case ARM::VLD4DUPdWB_register_Asm_32: in processInstruction()
8170 case ARM::VLD4DUPqWB_register_Asm_8: in processInstruction()
8171 case ARM::VLD4DUPqWB_register_Asm_16: in processInstruction()
8172 case ARM::VLD4DUPqWB_register_Asm_32: { in processInstruction()
8194 case ARM::VLD4dAsm_8: in processInstruction()
8195 case ARM::VLD4dAsm_16: in processInstruction()
8196 case ARM::VLD4dAsm_32: in processInstruction()
8197 case ARM::VLD4qAsm_8: in processInstruction()
8198 case ARM::VLD4qAsm_16: in processInstruction()
8199 case ARM::VLD4qAsm_32: { in processInstruction()
8218 case ARM::VLD4dWB_fixed_Asm_8: in processInstruction()
8219 case ARM::VLD4dWB_fixed_Asm_16: in processInstruction()
8220 case ARM::VLD4dWB_fixed_Asm_32: in processInstruction()
8221 case ARM::VLD4qWB_fixed_Asm_8: in processInstruction()
8222 case ARM::VLD4qWB_fixed_Asm_16: in processInstruction()
8223 case ARM::VLD4qWB_fixed_Asm_32: { in processInstruction()
8244 case ARM::VLD4dWB_register_Asm_8: in processInstruction()
8245 case ARM::VLD4dWB_register_Asm_16: in processInstruction()
8246 case ARM::VLD4dWB_register_Asm_32: in processInstruction()
8247 case ARM::VLD4qWB_register_Asm_8: in processInstruction()
8248 case ARM::VLD4qWB_register_Asm_16: in processInstruction()
8249 case ARM::VLD4qWB_register_Asm_32: { in processInstruction()
8271 case ARM::VST3dAsm_8: in processInstruction()
8272 case ARM::VST3dAsm_16: in processInstruction()
8273 case ARM::VST3dAsm_32: in processInstruction()
8274 case ARM::VST3qAsm_8: in processInstruction()
8275 case ARM::VST3qAsm_16: in processInstruction()
8276 case ARM::VST3qAsm_32: { in processInstruction()
8293 case ARM::VST3dWB_fixed_Asm_8: in processInstruction()
8294 case ARM::VST3dWB_fixed_Asm_16: in processInstruction()
8295 case ARM::VST3dWB_fixed_Asm_32: in processInstruction()
8296 case ARM::VST3qWB_fixed_Asm_8: in processInstruction()
8297 case ARM::VST3qWB_fixed_Asm_16: in processInstruction()
8298 case ARM::VST3qWB_fixed_Asm_32: { in processInstruction()
8317 case ARM::VST3dWB_register_Asm_8: in processInstruction()
8318 case ARM::VST3dWB_register_Asm_16: in processInstruction()
8319 case ARM::VST3dWB_register_Asm_32: in processInstruction()
8320 case ARM::VST3qWB_register_Asm_8: in processInstruction()
8321 case ARM::VST3qWB_register_Asm_16: in processInstruction()
8322 case ARM::VST3qWB_register_Asm_32: { in processInstruction()
8342 case ARM::VST4dAsm_8: in processInstruction()
8343 case ARM::VST4dAsm_16: in processInstruction()
8344 case ARM::VST4dAsm_32: in processInstruction()
8345 case ARM::VST4qAsm_8: in processInstruction()
8346 case ARM::VST4qAsm_16: in processInstruction()
8347 case ARM::VST4qAsm_32: { in processInstruction()
8366 case ARM::VST4dWB_fixed_Asm_8: in processInstruction()
8367 case ARM::VST4dWB_fixed_Asm_16: in processInstruction()
8368 case ARM::VST4dWB_fixed_Asm_32: in processInstruction()
8369 case ARM::VST4qWB_fixed_Asm_8: in processInstruction()
8370 case ARM::VST4qWB_fixed_Asm_16: in processInstruction()
8371 case ARM::VST4qWB_fixed_Asm_32: { in processInstruction()
8392 case ARM::VST4dWB_register_Asm_8: in processInstruction()
8393 case ARM::VST4dWB_register_Asm_16: in processInstruction()
8394 case ARM::VST4dWB_register_Asm_32: in processInstruction()
8395 case ARM::VST4qWB_register_Asm_8: in processInstruction()
8396 case ARM::VST4qWB_register_Asm_16: in processInstruction()
8397 case ARM::VST4qWB_register_Asm_32: { in processInstruction()
8419 case ARM::t2LSLri: in processInstruction()
8420 case ARM::t2LSRri: in processInstruction()
8421 case ARM::t2ASRri: in processInstruction()
8424 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
8429 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
8430 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
8431 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
8448 case ARM::t2MOVsr: in processInstruction()
8449 case ARM::t2MOVSsr: { in processInstruction()
8458 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && in processInstruction()
8465 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
8466 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; in processInstruction()
8467 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; in processInstruction()
8468 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
8474 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
8481 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
8485 case ARM::t2MOVsi: in processInstruction()
8486 case ARM::t2MOVSsi: { in processInstruction()
8493 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && in processInstruction()
8511 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr; in processInstruction()
8515 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
8516 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; in processInstruction()
8517 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; in processInstruction()
8518 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
8519 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
8527 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
8529 if (newOpc != ARM::t2RRX && !isMov) in processInstruction()
8535 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
8540 case ARM::ASRr: in processInstruction()
8541 case ARM::LSRr: in processInstruction()
8542 case ARM::LSLr: in processInstruction()
8543 case ARM::RORr: { in processInstruction()
8547 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
8548 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; in processInstruction()
8549 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; in processInstruction()
8550 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
8554 TmpInst.setOpcode(ARM::MOVsr); in processInstruction()
8565 case ARM::ASRi: in processInstruction()
8566 case ARM::LSRi: in processInstruction()
8567 case ARM::LSLi: in processInstruction()
8568 case ARM::RORi: { in processInstruction()
8572 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
8573 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; in processInstruction()
8574 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; in processInstruction()
8575 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
8579 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; in processInstruction()
8588 if (Opc == ARM::MOVsi) in processInstruction()
8596 case ARM::RRXi: { in processInstruction()
8599 TmpInst.setOpcode(ARM::MOVsi); in processInstruction()
8609 case ARM::t2LDMIA_UPD: { in processInstruction()
8615 TmpInst.setOpcode(ARM::t2LDR_POST); in processInstruction()
8625 case ARM::t2STMDB_UPD: { in processInstruction()
8631 TmpInst.setOpcode(ARM::t2STR_PRE); in processInstruction()
8641 case ARM::LDMIA_UPD: in processInstruction()
8647 TmpInst.setOpcode(ARM::LDR_POST_IMM); in processInstruction()
8659 case ARM::STMDB_UPD: in processInstruction()
8665 TmpInst.setOpcode(ARM::STR_PRE_IMM); in processInstruction()
8675 case ARM::t2ADDri12: in processInstruction()
8681 Inst.setOpcode(ARM::t2ADDri); in processInstruction()
8684 case ARM::t2SUBri12: in processInstruction()
8690 Inst.setOpcode(ARM::t2SUBri); in processInstruction()
8693 case ARM::tADDi8: in processInstruction()
8699 Inst.setOpcode(ARM::tADDi3); in processInstruction()
8703 case ARM::tSUBi8: in processInstruction()
8709 Inst.setOpcode(ARM::tSUBi3); in processInstruction()
8713 case ARM::t2ADDri: in processInstruction()
8714 case ARM::t2SUBri: { in processInstruction()
8723 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
8727 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? in processInstruction()
8728 ARM::tADDi8 : ARM::tSUBi8); in processInstruction()
8738 case ARM::t2ADDrr: { in processInstruction()
8756 TmpInst.setOpcode(ARM::tADDhirr); in processInstruction()
8765 case ARM::tADDrSP: in processInstruction()
8769 Inst.setOpcode(ARM::t2ADDrr); in processInstruction()
8774 case ARM::tB: in processInstruction()
8777 Inst.setOpcode(ARM::tBcc); in processInstruction()
8781 case ARM::t2B: in processInstruction()
8784 Inst.setOpcode(ARM::t2Bcc); in processInstruction()
8788 case ARM::t2Bcc: in processInstruction()
8791 Inst.setOpcode(ARM::t2B); in processInstruction()
8795 case ARM::tBcc: in processInstruction()
8798 Inst.setOpcode(ARM::tB); in processInstruction()
8802 case ARM::tLDMIA: { in processInstruction()
8817 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); in processInstruction()
8827 case ARM::tSTMIA_UPD: { in processInstruction()
8836 Inst.setOpcode(ARM::t2STMIA_UPD); in processInstruction()
8841 case ARM::tPOP: { in processInstruction()
8846 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) in processInstruction()
8849 Inst.setOpcode(ARM::t2LDMIA_UPD); in processInstruction()
8851 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8852 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8855 case ARM::tPUSH: { in processInstruction()
8857 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) in processInstruction()
8860 Inst.setOpcode(ARM::t2STMDB_UPD); in processInstruction()
8862 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8863 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8866 case ARM::t2MOVi: in processInstruction()
8872 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
8876 TmpInst.setOpcode(ARM::tMOVi8); in processInstruction()
8887 case ARM::t2MOVr: in processInstruction()
8893 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
8897 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); in processInstruction()
8907 case ARM::t2SXTH: in processInstruction()
8908 case ARM::t2SXTB: in processInstruction()
8909 case ARM::t2UXTH: in processInstruction()
8910 case ARM::t2UXTB: in processInstruction()
8920 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
8921 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
8922 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
8923 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
8937 case ARM::MOVsi: { in processInstruction()
8945 TmpInst.setOpcode(ARM::MOVr); in processInstruction()
8956 case ARM::ANDrsi: in processInstruction()
8957 case ARM::ORRrsi: in processInstruction()
8958 case ARM::EORrsi: in processInstruction()
8959 case ARM::BICrsi: in processInstruction()
8960 case ARM::SUBrsi: in processInstruction()
8961 case ARM::ADDrsi: { in processInstruction()
8967 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; in processInstruction()
8968 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; in processInstruction()
8969 case ARM::EORrsi: newOpc = ARM::EORrr; break; in processInstruction()
8970 case ARM::BICrsi: newOpc = ARM::BICrr; break; in processInstruction()
8971 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; in processInstruction()
8972 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; in processInstruction()
8991 case ARM::ITasm: in processInstruction()
8992 case ARM::t2IT: { in processInstruction()
9004 case ARM::t2LSLrr: in processInstruction()
9005 case ARM::t2LSRrr: in processInstruction()
9006 case ARM::t2ASRrr: in processInstruction()
9007 case ARM::t2SBCrr: in processInstruction()
9008 case ARM::t2RORrr: in processInstruction()
9009 case ARM::t2BICrr: in processInstruction()
9014 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
9019 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; in processInstruction()
9020 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; in processInstruction()
9021 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; in processInstruction()
9022 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; in processInstruction()
9023 case ARM::t2RORrr: NewOpc = ARM::tROR; break; in processInstruction()
9024 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; in processInstruction()
9039 case ARM::t2ANDrr: in processInstruction()
9040 case ARM::t2EORrr: in processInstruction()
9041 case ARM::t2ADCrr: in processInstruction()
9042 case ARM::t2ORRrr: in processInstruction()
9050 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
9055 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; in processInstruction()
9056 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; in processInstruction()
9057 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; in processInstruction()
9058 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; in processInstruction()
9098 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
9102 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
9105 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
9109 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) in checkTargetMatchPredicate()
9114 if (Opc == ARM::tADDhirr && !hasV6MOps() && in checkTargetMatchPredicate()
9119 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()
9128 if (Opc == ARM::t2MOVr && !hasV8Ops()) in checkTargetMatchPredicate()
9131 if (Inst.getOperand(0).getReg() == ARM::SP && in checkTargetMatchPredicate()
9132 Inst.getOperand(1).getReg() == ARM::SP) in checkTargetMatchPredicate()
9135 if (Inst.getOperand(4).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
9136 (Inst.getOperand(0).getReg() == ARM::SP || in checkTargetMatchPredicate()
9137 Inst.getOperand(1).getReg() == ARM::SP)) in checkTargetMatchPredicate()
9143 if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) && in checkTargetMatchPredicate()
9144 Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops())) in checkTargetMatchPredicate()
9148 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) { in checkTargetMatchPredicate()
9150 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops()) in checkTargetMatchPredicate()
9152 else if (Inst.getOperand(I).getReg() == ARM::PC) in checkTargetMatchPredicate()
9174 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || in isITBlockTerminator()
9180 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) in isITBlockTerminator()
9234 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) { in MatchInstruction()
9328 if (Inst.getOpcode() == ARM::ITasm) in MatchAndEmitInstruction()
9649 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveArch()
9651 if (ID == ARM::ArchKind::INVALID) in parseDirectiveArch()
9657 STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str()); in parseDirectiveArch()
9781 unsigned ID = ARM::parseFPU(FPU); in parseDirectiveFPU()
9783 if (!ARM::getFPUFeatures(ID, Features)) in parseDirectiveFPU()
9946 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, in parseDirectiveSetFP()
10175 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) in parseDirectivePersonalityIndex()
10262 if (UC.getFPReg() != ARM::SP) in parseDirectiveMovSP()
10269 if (SPReg == ARM::SP || SPReg == ARM::PC) in parseDirectiveMovSP()
10311 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveObjectArch()
10313 if (ID == ARM::ArchKind::INVALID) in parseDirectiveObjectArch()
10590 { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
10591 { ARM::AEK_CRYPTO, Feature_HasV8,
10592 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10593 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
10594 { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
10595 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
10596 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
10597 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10598 { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
10600 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
10601 { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
10602 { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
10604 { ARM::AEK_OS, Feature_None, {} },
10605 { ARM::AEK_IWMMXT, Feature_None, {} },
10606 { ARM::AEK_IWMMXT2, Feature_None, {} },
10607 { ARM::AEK_MAVERICK, Feature_None, {} },
10608 { ARM::AEK_XSCALE, Feature_None, {} },
10632 unsigned FeatureKind = ARM::parseArchExt(Name); in parseDirectiveArchExtension()
10633 if (FeatureKind == ARM::AEK_INVALID) in parseDirectiveArchExtension()
10690 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) in validateTargetOperandClass()
10695 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) in validateTargetOperandClass()