Lines Matching refs:ARM
47 NopInst.setOpcode(ARM::tHINT); in getNoop()
89 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
127 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
130 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
149 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
150 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
159 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
165 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
168 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
169 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
170 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
191 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
192 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
200 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
207 &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in loadRegFromStackSlot()
210 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot()
211 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
212 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
227 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12); in expandLoadStackGuard()
229 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12); in expandLoadStackGuard()
240 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
251 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
257 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
263 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) in emitT2RegPlusImmediate()
272 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) in emitT2RegPlusImmediate()
284 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) in emitT2RegPlusImmediate()
298 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
300 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
304 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
309 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
311 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) { in emitT2RegPlusImmediate()
313 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
324 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
336 assert(DestReg != ARM::SP && BaseReg != ARM::SP); in emitT2RegPlusImmediate()
337 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
341 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in emitT2RegPlusImmediate()
371 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
372 case ARM::t2LDRHi12: return ARM::t2LDRHi8; in negativeOffsetOpcode()
373 case ARM::t2LDRBi12: return ARM::t2LDRBi8; in negativeOffsetOpcode()
374 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8; in negativeOffsetOpcode()
375 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8; in negativeOffsetOpcode()
376 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
377 case ARM::t2STRBi12: return ARM::t2STRBi8; in negativeOffsetOpcode()
378 case ARM::t2STRHi12: return ARM::t2STRHi8; in negativeOffsetOpcode()
379 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
381 case ARM::t2LDRi8: in negativeOffsetOpcode()
382 case ARM::t2LDRHi8: in negativeOffsetOpcode()
383 case ARM::t2LDRBi8: in negativeOffsetOpcode()
384 case ARM::t2LDRSHi8: in negativeOffsetOpcode()
385 case ARM::t2LDRSBi8: in negativeOffsetOpcode()
386 case ARM::t2STRi8: in negativeOffsetOpcode()
387 case ARM::t2STRBi8: in negativeOffsetOpcode()
388 case ARM::t2STRHi8: in negativeOffsetOpcode()
389 case ARM::t2PLDi8: in negativeOffsetOpcode()
403 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
404 case ARM::t2LDRHi8: return ARM::t2LDRHi12; in positiveOffsetOpcode()
405 case ARM::t2LDRBi8: return ARM::t2LDRBi12; in positiveOffsetOpcode()
406 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12; in positiveOffsetOpcode()
407 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12; in positiveOffsetOpcode()
408 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
409 case ARM::t2STRBi8: return ARM::t2STRBi12; in positiveOffsetOpcode()
410 case ARM::t2STRHi8: return ARM::t2STRHi12; in positiveOffsetOpcode()
411 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
413 case ARM::t2LDRi12: in positiveOffsetOpcode()
414 case ARM::t2LDRHi12: in positiveOffsetOpcode()
415 case ARM::t2LDRBi12: in positiveOffsetOpcode()
416 case ARM::t2LDRSHi12: in positiveOffsetOpcode()
417 case ARM::t2LDRSBi12: in positiveOffsetOpcode()
418 case ARM::t2STRi12: in positiveOffsetOpcode()
419 case ARM::t2STRBi12: in positiveOffsetOpcode()
420 case ARM::t2STRHi12: in positiveOffsetOpcode()
421 case ARM::t2PLDi12: in positiveOffsetOpcode()
435 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
436 case ARM::t2LDRHs: return ARM::t2LDRHi12; in immediateOffsetOpcode()
437 case ARM::t2LDRBs: return ARM::t2LDRBi12; in immediateOffsetOpcode()
438 case ARM::t2LDRSHs: return ARM::t2LDRSHi12; in immediateOffsetOpcode()
439 case ARM::t2LDRSBs: return ARM::t2LDRSBi12; in immediateOffsetOpcode()
440 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
441 case ARM::t2STRBs: return ARM::t2STRBi12; in immediateOffsetOpcode()
442 case ARM::t2STRHs: return ARM::t2STRHi12; in immediateOffsetOpcode()
443 case ARM::t2PLDs: return ARM::t2PLDi12; in immediateOffsetOpcode()
445 case ARM::t2LDRi12: in immediateOffsetOpcode()
446 case ARM::t2LDRHi12: in immediateOffsetOpcode()
447 case ARM::t2LDRBi12: in immediateOffsetOpcode()
448 case ARM::t2LDRSHi12: in immediateOffsetOpcode()
449 case ARM::t2LDRSBi12: in immediateOffsetOpcode()
450 case ARM::t2STRi12: in immediateOffsetOpcode()
451 case ARM::t2STRBi12: in immediateOffsetOpcode()
452 case ARM::t2STRHi12: in immediateOffsetOpcode()
453 case ARM::t2PLDi12: in immediateOffsetOpcode()
454 case ARM::t2LDRi8: in immediateOffsetOpcode()
455 case ARM::t2LDRHi8: in immediateOffsetOpcode()
456 case ARM::t2LDRBi8: in immediateOffsetOpcode()
457 case ARM::t2LDRSHi8: in immediateOffsetOpcode()
458 case ARM::t2LDRSBi8: in immediateOffsetOpcode()
459 case ARM::t2STRi8: in immediateOffsetOpcode()
460 case ARM::t2STRBi8: in immediateOffsetOpcode()
461 case ARM::t2STRHi8: in immediateOffsetOpcode()
462 case ARM::t2PLDi8: in immediateOffsetOpcode()
481 if (Opcode == ARM::INLINEASM) in rewriteT2FrameIndex()
484 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { in rewriteT2FrameIndex()
489 !MI.definesRegister(ARM::CPSR)) { in rewriteT2FrameIndex()
491 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
501 bool HasCCOut = Opcode != ARM::t2ADDri12; in rewriteT2FrameIndex()
506 MI.setDesc(TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
508 MI.setDesc(TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
524 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
677 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) in getITInstrPredicate()