Lines Matching refs:ARM
153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
164 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
165 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
166 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 …
167 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
168 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
169 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,f…
170 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
171 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
172 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
173 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
174 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,fal…
175 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,fal…
176 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
177 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
178 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,fal…
179 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,fal…
180 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
181 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
182 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,fal…
183 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,fal…
184 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
185 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
186 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false…
187 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false…
189 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
190 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
191 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
192 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
193 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
194 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
196 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
197 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
198 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
199 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
200 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
201 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
202 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
203 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
204 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
205 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
207 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
208 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
209 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,fa…
210 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
211 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
212 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,fa…
213 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
214 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
215 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,fal…
217 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
218 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
219 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
220 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
221 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
222 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
223 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
224 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
225 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
226 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
227 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
228 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
230 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
231 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
232 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
233 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
234 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
235 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
236 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
237 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
238 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
239 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
241 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
242 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
243 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
244 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
245 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
246 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
248 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
249 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
250 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
251 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
252 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
253 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
254 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
255 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
256 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
258 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
259 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
260 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
261 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
262 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
263 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
264 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
265 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
266 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
267 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
268 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
269 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
271 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
272 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
273 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
274 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
275 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
276 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
277 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
278 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
279 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
280 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
282 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
283 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
284 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
285 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
286 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
287 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
289 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
290 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
291 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
292 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
293 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
294 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
295 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
296 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
297 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
299 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
300 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
301 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
302 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
303 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
304 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
306 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
307 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
308 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
309 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
310 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
311 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false…
312 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,f…
313 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
314 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false…
315 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,…
316 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
317 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
318 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
319 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
320 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,fa…
321 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,fa…
322 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
323 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
324 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,fa…
325 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,fa…
326 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
327 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
328 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,fa…
329 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,fa…
330 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
331 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
332 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,fals…
333 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,fals…
335 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
336 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
337 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
338 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
339 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
340 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
341 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
342 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
343 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
344 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
346 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
347 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
348 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,f…
349 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
350 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
351 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,f…
352 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
353 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
354 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,fa…
356 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
357 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
358 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
359 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
360 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
361 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
362 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
363 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
364 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
365 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
367 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
368 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
369 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
370 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
371 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
372 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
374 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
375 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
376 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
377 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
378 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
379 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
380 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
381 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
382 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
384 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
385 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
386 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
387 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
388 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
389 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
390 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
391 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
392 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
393 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
395 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
396 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
397 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
398 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
399 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
400 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
402 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
403 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
404 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
405 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
406 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
407 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
408 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
409 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
410 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
440 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
441 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
442 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
443 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
445 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
446 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
447 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
448 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
450 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
451 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
452 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
453 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
455 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
456 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
457 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
458 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
461 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
462 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
463 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
464 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
485 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 || in ExpandVLD()
486 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || in ExpandVLD()
487 TableEntry->RealOpc == ARM::VLD2DUPd32x2) { in ExpandVLD()
490 SubRegIndex = ARM::dsub_0; in ExpandVLD()
493 SubRegIndex = ARM::dsub_1; in ExpandVLD()
496 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, in ExpandVLD()
497 &ARM::DPairSpcRegClass); in ExpandVLD()
528 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || in ExpandVLD()
529 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || in ExpandVLD()
530 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || in ExpandVLD()
531 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || in ExpandVLD()
532 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || in ExpandVLD()
533 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || in ExpandVLD()
534 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || in ExpandVLD()
535 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) { in ExpandVLD()
548 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 && in ExpandVLD()
549 TableEntry->RealOpc != ARM::VLD2DUPd16x2 && in ExpandVLD()
550 TableEntry->RealOpc != ARM::VLD2DUPd32x2) { in ExpandVLD()
608 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || in ExpandVST()
609 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || in ExpandVST()
610 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || in ExpandVST()
611 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || in ExpandVST()
612 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || in ExpandVST()
613 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || in ExpandVST()
614 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || in ExpandVST()
615 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { in ExpandVST()
829 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; in ExpandMOV32BitImm()
835 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { in ExpandMOV32BitImm()
840 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
841 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
864 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { in ExpandMOV32BitImm()
865 LO16Opc = ARM::t2MOVi16; in ExpandMOV32BitImm()
866 HI16Opc = ARM::t2MOVTi16; in ExpandMOV32BitImm()
868 LO16Opc = ARM::MOVi16; in ExpandMOV32BitImm()
869 HI16Opc = ARM::MOVTi16; in ExpandMOV32BitImm()
962 if (LdrexOp == ARM::t2LDREX) in ExpandCMP_SWAP()
966 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP()
971 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP()
975 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
986 if (StrexOp == ARM::t2STREX) in ExpandCMP_SWAP()
990 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP()
998 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1031 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair()
1032 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair()
1056 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
1057 unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
1058 unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()
1059 unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
1075 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; in ExpandCMP_SWAP_64()
1081 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP_64()
1090 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1092 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP_64()
1096 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1104 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; in ExpandCMP_SWAP_64()
1110 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP_64()
1118 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1154 case ARM::TCRETURNdi: in ExpandMI()
1155 case ARM::TCRETURNri: { in ExpandMI()
1169 if (RetOpcode == ARM::TCRETURNdi) { in ExpandMI()
1172 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) in ExpandMI()
1173 : ARM::TAILJMPd; in ExpandMI()
1187 } else if (RetOpcode == ARM::TCRETURNri) { in ExpandMI()
1189 STI->isThumb() ? ARM::tTAILJMPr in ExpandMI()
1190 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); in ExpandMI()
1205 case ARM::VMOVScc: in ExpandMI()
1206 case ARM::VMOVDcc: { in ExpandMI()
1207 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; in ExpandMI()
1218 case ARM::t2MOVCCr: in ExpandMI()
1219 case ARM::MOVCCr: { in ExpandMI()
1220 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; in ExpandMI()
1232 case ARM::MOVCCsi: { in ExpandMI()
1233 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
1245 case ARM::MOVCCsr: { in ExpandMI()
1246 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), in ExpandMI()
1259 case ARM::t2MOVCCi16: in ExpandMI()
1260 case ARM::MOVCCi16: { in ExpandMI()
1261 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI()
1271 case ARM::t2MOVCCi: in ExpandMI()
1272 case ARM::MOVCCi: { in ExpandMI()
1273 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; in ExpandMI()
1285 case ARM::t2MVNCCi: in ExpandMI()
1286 case ARM::MVNCCi: { in ExpandMI()
1287 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; in ExpandMI()
1299 case ARM::t2MOVCClsl: in ExpandMI()
1300 case ARM::t2MOVCClsr: in ExpandMI()
1301 case ARM::t2MOVCCasr: in ExpandMI()
1302 case ARM::t2MOVCCror: { in ExpandMI()
1305 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
1306 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
1307 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
1308 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
1322 case ARM::Int_eh_sjlj_dispatchsetup: { in ExpandMI()
1337 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
1340 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
1343 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
1357 ARM::t2BICri : ARM::BICri; in ExpandMI()
1358 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) in ExpandMI()
1359 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
1370 case ARM::MOVsrl_flag: in ExpandMI()
1371 case ARM::MOVsra_flag: { in ExpandMI()
1373 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
1377 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) in ExpandMI()
1379 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
1383 case ARM::RRX: { in ExpandMI()
1386 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
1396 case ARM::tTPsoft: in ExpandMI()
1397 case ARM::TPsoft: { in ExpandMI()
1398 const bool Thumb = Opcode == ARM::tTPsoft; in ExpandMI()
1410 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) in ExpandMI()
1417 TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); in ExpandMI()
1423 TII->get(Thumb ? ARM::tBL : ARM::BL)); in ExpandMI()
1434 case ARM::tLDRpci_pic: in ExpandMI()
1435 case ARM::t2LDRpci_pic: { in ExpandMI()
1436 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) in ExpandMI()
1437 ? ARM::tLDRpci : ARM::t2LDRpci; in ExpandMI()
1446 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) in ExpandMI()
1455 case ARM::LDRLIT_ga_abs: in ExpandMI()
1456 case ARM::LDRLIT_ga_pcrel: in ExpandMI()
1457 case ARM::LDRLIT_ga_pcrel_ldr: in ExpandMI()
1458 case ARM::tLDRLIT_ga_abs: in ExpandMI()
1459 case ARM::tLDRLIT_ga_pcrel: { in ExpandMI()
1466 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
1468 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
1469 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; in ExpandMI()
1472 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
1473 : ARM::tPICADD; in ExpandMI()
1513 case ARM::MOV_ga_pcrel: in ExpandMI()
1514 case ARM::MOV_ga_pcrel_ldr: in ExpandMI()
1515 case ARM::t2MOV_ga_pcrel: { in ExpandMI()
1523 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; in ExpandMI()
1524 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; in ExpandMI()
1525 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; in ExpandMI()
1529 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
1530 : ARM::tPICADD; in ExpandMI()
1547 if (Opcode == ARM::MOV_ga_pcrel_ldr) in ExpandMI()
1555 case ARM::MOVi32imm: in ExpandMI()
1556 case ARM::MOVCCi32imm: in ExpandMI()
1557 case ARM::t2MOVi32imm: in ExpandMI()
1558 case ARM::t2MOVCCi32imm: in ExpandMI()
1562 case ARM::SUBS_PC_LR: { in ExpandMI()
1564 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) in ExpandMI()
1565 .addReg(ARM::LR) in ExpandMI()
1569 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
1574 case ARM::VLDMQIA: { in ExpandMI()
1575 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI()
1592 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); in ExpandMI()
1593 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI()
1605 case ARM::VSTMQIA: { in ExpandMI()
1606 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI()
1624 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); in ExpandMI()
1625 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI()
1638 case ARM::VLD2q8Pseudo: in ExpandMI()
1639 case ARM::VLD2q16Pseudo: in ExpandMI()
1640 case ARM::VLD2q32Pseudo: in ExpandMI()
1641 case ARM::VLD2q8PseudoWB_fixed: in ExpandMI()
1642 case ARM::VLD2q16PseudoWB_fixed: in ExpandMI()
1643 case ARM::VLD2q32PseudoWB_fixed: in ExpandMI()
1644 case ARM::VLD2q8PseudoWB_register: in ExpandMI()
1645 case ARM::VLD2q16PseudoWB_register: in ExpandMI()
1646 case ARM::VLD2q32PseudoWB_register: in ExpandMI()
1647 case ARM::VLD3d8Pseudo: in ExpandMI()
1648 case ARM::VLD3d16Pseudo: in ExpandMI()
1649 case ARM::VLD3d32Pseudo: in ExpandMI()
1650 case ARM::VLD1d8TPseudo: in ExpandMI()
1651 case ARM::VLD1d16TPseudo: in ExpandMI()
1652 case ARM::VLD1d32TPseudo: in ExpandMI()
1653 case ARM::VLD1d64TPseudo: in ExpandMI()
1654 case ARM::VLD1d64TPseudoWB_fixed: in ExpandMI()
1655 case ARM::VLD1d64TPseudoWB_register: in ExpandMI()
1656 case ARM::VLD3d8Pseudo_UPD: in ExpandMI()
1657 case ARM::VLD3d16Pseudo_UPD: in ExpandMI()
1658 case ARM::VLD3d32Pseudo_UPD: in ExpandMI()
1659 case ARM::VLD3q8Pseudo_UPD: in ExpandMI()
1660 case ARM::VLD3q16Pseudo_UPD: in ExpandMI()
1661 case ARM::VLD3q32Pseudo_UPD: in ExpandMI()
1662 case ARM::VLD3q8oddPseudo: in ExpandMI()
1663 case ARM::VLD3q16oddPseudo: in ExpandMI()
1664 case ARM::VLD3q32oddPseudo: in ExpandMI()
1665 case ARM::VLD3q8oddPseudo_UPD: in ExpandMI()
1666 case ARM::VLD3q16oddPseudo_UPD: in ExpandMI()
1667 case ARM::VLD3q32oddPseudo_UPD: in ExpandMI()
1668 case ARM::VLD4d8Pseudo: in ExpandMI()
1669 case ARM::VLD4d16Pseudo: in ExpandMI()
1670 case ARM::VLD4d32Pseudo: in ExpandMI()
1671 case ARM::VLD1d8QPseudo: in ExpandMI()
1672 case ARM::VLD1d16QPseudo: in ExpandMI()
1673 case ARM::VLD1d32QPseudo: in ExpandMI()
1674 case ARM::VLD1d64QPseudo: in ExpandMI()
1675 case ARM::VLD1d64QPseudoWB_fixed: in ExpandMI()
1676 case ARM::VLD1d64QPseudoWB_register: in ExpandMI()
1677 case ARM::VLD1q8HighQPseudo: in ExpandMI()
1678 case ARM::VLD1q8LowQPseudo_UPD: in ExpandMI()
1679 case ARM::VLD1q8HighTPseudo: in ExpandMI()
1680 case ARM::VLD1q8LowTPseudo_UPD: in ExpandMI()
1681 case ARM::VLD1q16HighQPseudo: in ExpandMI()
1682 case ARM::VLD1q16LowQPseudo_UPD: in ExpandMI()
1683 case ARM::VLD1q16HighTPseudo: in ExpandMI()
1684 case ARM::VLD1q16LowTPseudo_UPD: in ExpandMI()
1685 case ARM::VLD1q32HighQPseudo: in ExpandMI()
1686 case ARM::VLD1q32LowQPseudo_UPD: in ExpandMI()
1687 case ARM::VLD1q32HighTPseudo: in ExpandMI()
1688 case ARM::VLD1q32LowTPseudo_UPD: in ExpandMI()
1689 case ARM::VLD1q64HighQPseudo: in ExpandMI()
1690 case ARM::VLD1q64LowQPseudo_UPD: in ExpandMI()
1691 case ARM::VLD1q64HighTPseudo: in ExpandMI()
1692 case ARM::VLD1q64LowTPseudo_UPD: in ExpandMI()
1693 case ARM::VLD4d8Pseudo_UPD: in ExpandMI()
1694 case ARM::VLD4d16Pseudo_UPD: in ExpandMI()
1695 case ARM::VLD4d32Pseudo_UPD: in ExpandMI()
1696 case ARM::VLD4q8Pseudo_UPD: in ExpandMI()
1697 case ARM::VLD4q16Pseudo_UPD: in ExpandMI()
1698 case ARM::VLD4q32Pseudo_UPD: in ExpandMI()
1699 case ARM::VLD4q8oddPseudo: in ExpandMI()
1700 case ARM::VLD4q16oddPseudo: in ExpandMI()
1701 case ARM::VLD4q32oddPseudo: in ExpandMI()
1702 case ARM::VLD4q8oddPseudo_UPD: in ExpandMI()
1703 case ARM::VLD4q16oddPseudo_UPD: in ExpandMI()
1704 case ARM::VLD4q32oddPseudo_UPD: in ExpandMI()
1705 case ARM::VLD3DUPd8Pseudo: in ExpandMI()
1706 case ARM::VLD3DUPd16Pseudo: in ExpandMI()
1707 case ARM::VLD3DUPd32Pseudo: in ExpandMI()
1708 case ARM::VLD3DUPd8Pseudo_UPD: in ExpandMI()
1709 case ARM::VLD3DUPd16Pseudo_UPD: in ExpandMI()
1710 case ARM::VLD3DUPd32Pseudo_UPD: in ExpandMI()
1711 case ARM::VLD4DUPd8Pseudo: in ExpandMI()
1712 case ARM::VLD4DUPd16Pseudo: in ExpandMI()
1713 case ARM::VLD4DUPd32Pseudo: in ExpandMI()
1714 case ARM::VLD4DUPd8Pseudo_UPD: in ExpandMI()
1715 case ARM::VLD4DUPd16Pseudo_UPD: in ExpandMI()
1716 case ARM::VLD4DUPd32Pseudo_UPD: in ExpandMI()
1717 case ARM::VLD2DUPq8EvenPseudo: in ExpandMI()
1718 case ARM::VLD2DUPq8OddPseudo: in ExpandMI()
1719 case ARM::VLD2DUPq16EvenPseudo: in ExpandMI()
1720 case ARM::VLD2DUPq16OddPseudo: in ExpandMI()
1721 case ARM::VLD2DUPq32EvenPseudo: in ExpandMI()
1722 case ARM::VLD2DUPq32OddPseudo: in ExpandMI()
1723 case ARM::VLD3DUPq8EvenPseudo: in ExpandMI()
1724 case ARM::VLD3DUPq8OddPseudo: in ExpandMI()
1725 case ARM::VLD3DUPq16EvenPseudo: in ExpandMI()
1726 case ARM::VLD3DUPq16OddPseudo: in ExpandMI()
1727 case ARM::VLD3DUPq32EvenPseudo: in ExpandMI()
1728 case ARM::VLD3DUPq32OddPseudo: in ExpandMI()
1729 case ARM::VLD4DUPq8EvenPseudo: in ExpandMI()
1730 case ARM::VLD4DUPq8OddPseudo: in ExpandMI()
1731 case ARM::VLD4DUPq16EvenPseudo: in ExpandMI()
1732 case ARM::VLD4DUPq16OddPseudo: in ExpandMI()
1733 case ARM::VLD4DUPq32EvenPseudo: in ExpandMI()
1734 case ARM::VLD4DUPq32OddPseudo: in ExpandMI()
1738 case ARM::VST2q8Pseudo: in ExpandMI()
1739 case ARM::VST2q16Pseudo: in ExpandMI()
1740 case ARM::VST2q32Pseudo: in ExpandMI()
1741 case ARM::VST2q8PseudoWB_fixed: in ExpandMI()
1742 case ARM::VST2q16PseudoWB_fixed: in ExpandMI()
1743 case ARM::VST2q32PseudoWB_fixed: in ExpandMI()
1744 case ARM::VST2q8PseudoWB_register: in ExpandMI()
1745 case ARM::VST2q16PseudoWB_register: in ExpandMI()
1746 case ARM::VST2q32PseudoWB_register: in ExpandMI()
1747 case ARM::VST3d8Pseudo: in ExpandMI()
1748 case ARM::VST3d16Pseudo: in ExpandMI()
1749 case ARM::VST3d32Pseudo: in ExpandMI()
1750 case ARM::VST1d8TPseudo: in ExpandMI()
1751 case ARM::VST1d16TPseudo: in ExpandMI()
1752 case ARM::VST1d32TPseudo: in ExpandMI()
1753 case ARM::VST1d64TPseudo: in ExpandMI()
1754 case ARM::VST3d8Pseudo_UPD: in ExpandMI()
1755 case ARM::VST3d16Pseudo_UPD: in ExpandMI()
1756 case ARM::VST3d32Pseudo_UPD: in ExpandMI()
1757 case ARM::VST1d64TPseudoWB_fixed: in ExpandMI()
1758 case ARM::VST1d64TPseudoWB_register: in ExpandMI()
1759 case ARM::VST3q8Pseudo_UPD: in ExpandMI()
1760 case ARM::VST3q16Pseudo_UPD: in ExpandMI()
1761 case ARM::VST3q32Pseudo_UPD: in ExpandMI()
1762 case ARM::VST3q8oddPseudo: in ExpandMI()
1763 case ARM::VST3q16oddPseudo: in ExpandMI()
1764 case ARM::VST3q32oddPseudo: in ExpandMI()
1765 case ARM::VST3q8oddPseudo_UPD: in ExpandMI()
1766 case ARM::VST3q16oddPseudo_UPD: in ExpandMI()
1767 case ARM::VST3q32oddPseudo_UPD: in ExpandMI()
1768 case ARM::VST4d8Pseudo: in ExpandMI()
1769 case ARM::VST4d16Pseudo: in ExpandMI()
1770 case ARM::VST4d32Pseudo: in ExpandMI()
1771 case ARM::VST1d8QPseudo: in ExpandMI()
1772 case ARM::VST1d16QPseudo: in ExpandMI()
1773 case ARM::VST1d32QPseudo: in ExpandMI()
1774 case ARM::VST1d64QPseudo: in ExpandMI()
1775 case ARM::VST4d8Pseudo_UPD: in ExpandMI()
1776 case ARM::VST4d16Pseudo_UPD: in ExpandMI()
1777 case ARM::VST4d32Pseudo_UPD: in ExpandMI()
1778 case ARM::VST1d64QPseudoWB_fixed: in ExpandMI()
1779 case ARM::VST1d64QPseudoWB_register: in ExpandMI()
1780 case ARM::VST1q8HighQPseudo: in ExpandMI()
1781 case ARM::VST1q8LowQPseudo_UPD: in ExpandMI()
1782 case ARM::VST1q8HighTPseudo: in ExpandMI()
1783 case ARM::VST1q8LowTPseudo_UPD: in ExpandMI()
1784 case ARM::VST1q16HighQPseudo: in ExpandMI()
1785 case ARM::VST1q16LowQPseudo_UPD: in ExpandMI()
1786 case ARM::VST1q16HighTPseudo: in ExpandMI()
1787 case ARM::VST1q16LowTPseudo_UPD: in ExpandMI()
1788 case ARM::VST1q32HighQPseudo: in ExpandMI()
1789 case ARM::VST1q32LowQPseudo_UPD: in ExpandMI()
1790 case ARM::VST1q32HighTPseudo: in ExpandMI()
1791 case ARM::VST1q32LowTPseudo_UPD: in ExpandMI()
1792 case ARM::VST1q64HighQPseudo: in ExpandMI()
1793 case ARM::VST1q64LowQPseudo_UPD: in ExpandMI()
1794 case ARM::VST1q64HighTPseudo: in ExpandMI()
1795 case ARM::VST1q64LowTPseudo_UPD: in ExpandMI()
1796 case ARM::VST4q8Pseudo_UPD: in ExpandMI()
1797 case ARM::VST4q16Pseudo_UPD: in ExpandMI()
1798 case ARM::VST4q32Pseudo_UPD: in ExpandMI()
1799 case ARM::VST4q8oddPseudo: in ExpandMI()
1800 case ARM::VST4q16oddPseudo: in ExpandMI()
1801 case ARM::VST4q32oddPseudo: in ExpandMI()
1802 case ARM::VST4q8oddPseudo_UPD: in ExpandMI()
1803 case ARM::VST4q16oddPseudo_UPD: in ExpandMI()
1804 case ARM::VST4q32oddPseudo_UPD: in ExpandMI()
1808 case ARM::VLD1LNq8Pseudo: in ExpandMI()
1809 case ARM::VLD1LNq16Pseudo: in ExpandMI()
1810 case ARM::VLD1LNq32Pseudo: in ExpandMI()
1811 case ARM::VLD1LNq8Pseudo_UPD: in ExpandMI()
1812 case ARM::VLD1LNq16Pseudo_UPD: in ExpandMI()
1813 case ARM::VLD1LNq32Pseudo_UPD: in ExpandMI()
1814 case ARM::VLD2LNd8Pseudo: in ExpandMI()
1815 case ARM::VLD2LNd16Pseudo: in ExpandMI()
1816 case ARM::VLD2LNd32Pseudo: in ExpandMI()
1817 case ARM::VLD2LNq16Pseudo: in ExpandMI()
1818 case ARM::VLD2LNq32Pseudo: in ExpandMI()
1819 case ARM::VLD2LNd8Pseudo_UPD: in ExpandMI()
1820 case ARM::VLD2LNd16Pseudo_UPD: in ExpandMI()
1821 case ARM::VLD2LNd32Pseudo_UPD: in ExpandMI()
1822 case ARM::VLD2LNq16Pseudo_UPD: in ExpandMI()
1823 case ARM::VLD2LNq32Pseudo_UPD: in ExpandMI()
1824 case ARM::VLD3LNd8Pseudo: in ExpandMI()
1825 case ARM::VLD3LNd16Pseudo: in ExpandMI()
1826 case ARM::VLD3LNd32Pseudo: in ExpandMI()
1827 case ARM::VLD3LNq16Pseudo: in ExpandMI()
1828 case ARM::VLD3LNq32Pseudo: in ExpandMI()
1829 case ARM::VLD3LNd8Pseudo_UPD: in ExpandMI()
1830 case ARM::VLD3LNd16Pseudo_UPD: in ExpandMI()
1831 case ARM::VLD3LNd32Pseudo_UPD: in ExpandMI()
1832 case ARM::VLD3LNq16Pseudo_UPD: in ExpandMI()
1833 case ARM::VLD3LNq32Pseudo_UPD: in ExpandMI()
1834 case ARM::VLD4LNd8Pseudo: in ExpandMI()
1835 case ARM::VLD4LNd16Pseudo: in ExpandMI()
1836 case ARM::VLD4LNd32Pseudo: in ExpandMI()
1837 case ARM::VLD4LNq16Pseudo: in ExpandMI()
1838 case ARM::VLD4LNq32Pseudo: in ExpandMI()
1839 case ARM::VLD4LNd8Pseudo_UPD: in ExpandMI()
1840 case ARM::VLD4LNd16Pseudo_UPD: in ExpandMI()
1841 case ARM::VLD4LNd32Pseudo_UPD: in ExpandMI()
1842 case ARM::VLD4LNq16Pseudo_UPD: in ExpandMI()
1843 case ARM::VLD4LNq32Pseudo_UPD: in ExpandMI()
1844 case ARM::VST1LNq8Pseudo: in ExpandMI()
1845 case ARM::VST1LNq16Pseudo: in ExpandMI()
1846 case ARM::VST1LNq32Pseudo: in ExpandMI()
1847 case ARM::VST1LNq8Pseudo_UPD: in ExpandMI()
1848 case ARM::VST1LNq16Pseudo_UPD: in ExpandMI()
1849 case ARM::VST1LNq32Pseudo_UPD: in ExpandMI()
1850 case ARM::VST2LNd8Pseudo: in ExpandMI()
1851 case ARM::VST2LNd16Pseudo: in ExpandMI()
1852 case ARM::VST2LNd32Pseudo: in ExpandMI()
1853 case ARM::VST2LNq16Pseudo: in ExpandMI()
1854 case ARM::VST2LNq32Pseudo: in ExpandMI()
1855 case ARM::VST2LNd8Pseudo_UPD: in ExpandMI()
1856 case ARM::VST2LNd16Pseudo_UPD: in ExpandMI()
1857 case ARM::VST2LNd32Pseudo_UPD: in ExpandMI()
1858 case ARM::VST2LNq16Pseudo_UPD: in ExpandMI()
1859 case ARM::VST2LNq32Pseudo_UPD: in ExpandMI()
1860 case ARM::VST3LNd8Pseudo: in ExpandMI()
1861 case ARM::VST3LNd16Pseudo: in ExpandMI()
1862 case ARM::VST3LNd32Pseudo: in ExpandMI()
1863 case ARM::VST3LNq16Pseudo: in ExpandMI()
1864 case ARM::VST3LNq32Pseudo: in ExpandMI()
1865 case ARM::VST3LNd8Pseudo_UPD: in ExpandMI()
1866 case ARM::VST3LNd16Pseudo_UPD: in ExpandMI()
1867 case ARM::VST3LNd32Pseudo_UPD: in ExpandMI()
1868 case ARM::VST3LNq16Pseudo_UPD: in ExpandMI()
1869 case ARM::VST3LNq32Pseudo_UPD: in ExpandMI()
1870 case ARM::VST4LNd8Pseudo: in ExpandMI()
1871 case ARM::VST4LNd16Pseudo: in ExpandMI()
1872 case ARM::VST4LNd32Pseudo: in ExpandMI()
1873 case ARM::VST4LNq16Pseudo: in ExpandMI()
1874 case ARM::VST4LNq32Pseudo: in ExpandMI()
1875 case ARM::VST4LNd8Pseudo_UPD: in ExpandMI()
1876 case ARM::VST4LNd16Pseudo_UPD: in ExpandMI()
1877 case ARM::VST4LNd32Pseudo_UPD: in ExpandMI()
1878 case ARM::VST4LNq16Pseudo_UPD: in ExpandMI()
1879 case ARM::VST4LNq32Pseudo_UPD: in ExpandMI()
1883 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; in ExpandMI()
1884 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; in ExpandMI()
1885 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; in ExpandMI()
1886 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; in ExpandMI()
1888 case ARM::CMP_SWAP_8: in ExpandMI()
1890 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, in ExpandMI()
1891 ARM::tUXTB, NextMBBI); in ExpandMI()
1893 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, in ExpandMI()
1894 ARM::UXTB, NextMBBI); in ExpandMI()
1895 case ARM::CMP_SWAP_16: in ExpandMI()
1897 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, in ExpandMI()
1898 ARM::tUXTH, NextMBBI); in ExpandMI()
1900 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, in ExpandMI()
1901 ARM::UXTH, NextMBBI); in ExpandMI()
1902 case ARM::CMP_SWAP_32: in ExpandMI()
1904 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, in ExpandMI()
1907 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
1909 case ARM::CMP_SWAP_64: in ExpandMI()