49   if (ARM::tGPRRegClass.hasSubClassEq(RC))  in getLargestLegalSuperClass()
50     return &ARM::tGPRRegClass;  in getLargestLegalSuperClass()
59   return &ARM::tGPRRegClass;  in getPointerRegClass()
76   BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))  in emitThumb1LoadConstPool()
95   BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))  in emitThumb2LoadConstPool()
143   if (DestReg == ARM::SP)  in emitThumbRegPlusImmInReg()
144     assert(BaseReg == ARM::SP && "Unexpected!");  in emitThumbRegPlusImmInReg()
146     LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);  in emitThumbRegPlusImmInReg()
149     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)  in emitThumbRegPlusImmInReg()
154     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)  in emitThumbRegPlusImmInReg()
158     BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)  in emitThumbRegPlusImmInReg()
163     BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), LdReg)  in emitThumbRegPlusImmInReg()
170   int Opc = (isSub) ? ARM::tSUBrr  in emitThumbRegPlusImmInReg()
171                     : ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr);  in emitThumbRegPlusImmInReg()
173   if (Opc != ARM::tADDhirr)  in emitThumbRegPlusImmInReg()
175   if (DestReg == ARM::SP || isSub)  in emitThumbRegPlusImmInReg()
219   if (DestReg == ARM::SP) {  in emitThumbRegPlusImmediate()
220     if (BaseReg == ARM::SP) {  in emitThumbRegPlusImmediate()
225       CopyOpc = ARM::tMOVr;  in emitThumbRegPlusImmediate()
228     ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;  in emitThumbRegPlusImmediate()
232     if (BaseReg == ARM::SP) {  in emitThumbRegPlusImmediate()
235       CopyOpc = ARM::tADDrSPi;  in emitThumbRegPlusImmediate()
243       CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;  in emitThumbRegPlusImmediate()
248       CopyOpc = ARM::tMOVr;  in emitThumbRegPlusImmediate()
251     ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;  in emitThumbRegPlusImmediate()
260       CopyOpc = ARM::tMOVr;  in emitThumbRegPlusImmediate()
274     CopyOpc = ARM::tMOVr;  in emitThumbRegPlusImmediate()
297   unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;  in emitThumbRegPlusImmediate()
316     if (CopyOpc != ARM::tMOVr) {  in emitThumbRegPlusImmediate()
349   case ARM::tLDRspi:  in convertToNonSPOpcode()
350     return ARM::tLDRi;  in convertToNonSPOpcode()
352   case ARM::tSTRspi:  in convertToNonSPOpcode()
353     return ARM::tSTRi;  in convertToNonSPOpcode()
373   if (Opcode == ARM::tADDframe) {  in rewriteFrameIndex()
387     unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;  in rewriteFrameIndex()
406       if (NewOpc != Opcode && FrameReg != ARM::SP)  in rewriteFrameIndex()
417     if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {  in rewriteFrameIndex()
468   BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))  in saveScavengerRegister()
469       .addReg(ARM::R12, RegState::Define)  in saveScavengerRegister()
483       if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {  in saveScavengerRegister()
491       if (MO.getReg() == ARM::R12) {  in saveScavengerRegister()
499   BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr))  in saveScavengerRegister()
501       .addReg(ARM::R12, RegState::Kill)  in saveScavengerRegister()
533   if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){  in eliminateFrameIndex()
572     if (Opcode == ARM::tLDRspi) {  in eliminateFrameIndex()
573       if (FrameReg == ARM::SP || STI.genExecuteOnly())  in eliminateFrameIndex()
585     MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));  in eliminateFrameIndex()
593       VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);  in eliminateFrameIndex()
596       if (Opcode == ARM::tSTRspi) {  in eliminateFrameIndex()
597         if (FrameReg == ARM::SP || STI.genExecuteOnly())  in eliminateFrameIndex()
607       MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));  in eliminateFrameIndex()