Lines Matching refs:ARM
108 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
418 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1122 (LHSR && LHSR->getReg() == ARM::SP)) { in SelectThumbAddrModeSP()
1365 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1369 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1373 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1380 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1381 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1386 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1392 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1396 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
1399 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; in tryARMIndexedLoad()
1405 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) { in tryARMIndexedLoad()
1451 SDNode *New = CurDAG->getMachineNode(ARM::tLDR_postidx, SDLoc(N), MVT::i32, in tryT1IndexedLoad()
1473 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; in tryT2IndexedLoad()
1477 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; in tryT2IndexedLoad()
1479 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; in tryT2IndexedLoad()
1484 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; in tryT2IndexedLoad()
1486 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; in tryT2IndexedLoad()
1513 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32); in createGPRPairNode()
1514 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode()
1515 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode()
1524 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32); in createSRegPairNode()
1525 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode()
1526 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode()
1534 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode()
1536 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode()
1537 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode()
1545 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode()
1547 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode()
1548 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode()
1558 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32); in createQuadSRegsNode()
1559 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createQuadSRegsNode()
1560 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode()
1561 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); in createQuadSRegsNode()
1562 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32); in createQuadSRegsNode()
1572 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode()
1574 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createQuadDRegsNode()
1575 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createQuadDRegsNode()
1576 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); in createQuadDRegsNode()
1577 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32); in createQuadDRegsNode()
1587 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode()
1589 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQuadQRegsNode()
1590 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQuadQRegsNode()
1591 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); in createQuadQRegsNode()
1592 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32); in createQuadQRegsNode()
1624 case ARM::VLD1d8wb_fixed : return true; in isVLDfixed()
1625 case ARM::VLD1d16wb_fixed : return true; in isVLDfixed()
1626 case ARM::VLD1d64Qwb_fixed : return true; in isVLDfixed()
1627 case ARM::VLD1d32wb_fixed : return true; in isVLDfixed()
1628 case ARM::VLD1d64wb_fixed : return true; in isVLDfixed()
1629 case ARM::VLD1d64TPseudoWB_fixed : return true; in isVLDfixed()
1630 case ARM::VLD1d64QPseudoWB_fixed : return true; in isVLDfixed()
1631 case ARM::VLD1q8wb_fixed : return true; in isVLDfixed()
1632 case ARM::VLD1q16wb_fixed : return true; in isVLDfixed()
1633 case ARM::VLD1q32wb_fixed : return true; in isVLDfixed()
1634 case ARM::VLD1q64wb_fixed : return true; in isVLDfixed()
1635 case ARM::VLD1DUPd8wb_fixed : return true; in isVLDfixed()
1636 case ARM::VLD1DUPd16wb_fixed : return true; in isVLDfixed()
1637 case ARM::VLD1DUPd32wb_fixed : return true; in isVLDfixed()
1638 case ARM::VLD1DUPq8wb_fixed : return true; in isVLDfixed()
1639 case ARM::VLD1DUPq16wb_fixed : return true; in isVLDfixed()
1640 case ARM::VLD1DUPq32wb_fixed : return true; in isVLDfixed()
1641 case ARM::VLD2d8wb_fixed : return true; in isVLDfixed()
1642 case ARM::VLD2d16wb_fixed : return true; in isVLDfixed()
1643 case ARM::VLD2d32wb_fixed : return true; in isVLDfixed()
1644 case ARM::VLD2q8PseudoWB_fixed : return true; in isVLDfixed()
1645 case ARM::VLD2q16PseudoWB_fixed : return true; in isVLDfixed()
1646 case ARM::VLD2q32PseudoWB_fixed : return true; in isVLDfixed()
1647 case ARM::VLD2DUPd8wb_fixed : return true; in isVLDfixed()
1648 case ARM::VLD2DUPd16wb_fixed : return true; in isVLDfixed()
1649 case ARM::VLD2DUPd32wb_fixed : return true; in isVLDfixed()
1657 case ARM::VST1d8wb_fixed : return true; in isVSTfixed()
1658 case ARM::VST1d16wb_fixed : return true; in isVSTfixed()
1659 case ARM::VST1d32wb_fixed : return true; in isVSTfixed()
1660 case ARM::VST1d64wb_fixed : return true; in isVSTfixed()
1661 case ARM::VST1q8wb_fixed : return true; in isVSTfixed()
1662 case ARM::VST1q16wb_fixed : return true; in isVSTfixed()
1663 case ARM::VST1q32wb_fixed : return true; in isVSTfixed()
1664 case ARM::VST1q64wb_fixed : return true; in isVSTfixed()
1665 case ARM::VST1d64TPseudoWB_fixed : return true; in isVSTfixed()
1666 case ARM::VST1d64QPseudoWB_fixed : return true; in isVSTfixed()
1667 case ARM::VST2d8wb_fixed : return true; in isVSTfixed()
1668 case ARM::VST2d16wb_fixed : return true; in isVSTfixed()
1669 case ARM::VST2d32wb_fixed : return true; in isVSTfixed()
1670 case ARM::VST2q8PseudoWB_fixed : return true; in isVSTfixed()
1671 case ARM::VST2q16PseudoWB_fixed : return true; in isVSTfixed()
1672 case ARM::VST2q32PseudoWB_fixed : return true; in isVSTfixed()
1683 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register; in getVLDSTRegisterUpdateOpcode()
1684 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register; in getVLDSTRegisterUpdateOpcode()
1685 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register; in getVLDSTRegisterUpdateOpcode()
1686 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register; in getVLDSTRegisterUpdateOpcode()
1687 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register; in getVLDSTRegisterUpdateOpcode()
1688 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register; in getVLDSTRegisterUpdateOpcode()
1689 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register; in getVLDSTRegisterUpdateOpcode()
1690 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register; in getVLDSTRegisterUpdateOpcode()
1691 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register; in getVLDSTRegisterUpdateOpcode()
1692 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register; in getVLDSTRegisterUpdateOpcode()
1693 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1694 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1695 case ARM::VLD1DUPd8wb_fixed : return ARM::VLD1DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
1696 case ARM::VLD1DUPd16wb_fixed : return ARM::VLD1DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
1697 case ARM::VLD1DUPd32wb_fixed : return ARM::VLD1DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
1698 case ARM::VLD1DUPq8wb_fixed : return ARM::VLD1DUPq8wb_register; in getVLDSTRegisterUpdateOpcode()
1699 case ARM::VLD1DUPq16wb_fixed : return ARM::VLD1DUPq16wb_register; in getVLDSTRegisterUpdateOpcode()
1700 case ARM::VLD1DUPq32wb_fixed : return ARM::VLD1DUPq32wb_register; in getVLDSTRegisterUpdateOpcode()
1702 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register; in getVLDSTRegisterUpdateOpcode()
1703 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register; in getVLDSTRegisterUpdateOpcode()
1704 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register; in getVLDSTRegisterUpdateOpcode()
1705 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register; in getVLDSTRegisterUpdateOpcode()
1706 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register; in getVLDSTRegisterUpdateOpcode()
1707 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register; in getVLDSTRegisterUpdateOpcode()
1708 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register; in getVLDSTRegisterUpdateOpcode()
1709 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register; in getVLDSTRegisterUpdateOpcode()
1710 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1711 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1713 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register; in getVLDSTRegisterUpdateOpcode()
1714 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register; in getVLDSTRegisterUpdateOpcode()
1715 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register; in getVLDSTRegisterUpdateOpcode()
1716 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1717 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1718 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1720 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register; in getVLDSTRegisterUpdateOpcode()
1721 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register; in getVLDSTRegisterUpdateOpcode()
1722 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register; in getVLDSTRegisterUpdateOpcode()
1723 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1724 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1725 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
1727 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
1728 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
1729 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
1868 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLD()
1869 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLD()
1871 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2144 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLDSTLane()
2145 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLDSTLane()
2147 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()
2273 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering"); in SelectVLDDup()
2274 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDDup()
2291 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) in tryV6T2BitfieldExtractOp()
2292 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); in tryV6T2BitfieldExtractOp()
2323 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri; in tryV6T2BitfieldExtractOp()
2338 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
2454 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; in tryABSOp()
2467 Opcode = ARM::CMP_SWAP_8; in SelectCMP_SWAP()
2469 Opcode = ARM::CMP_SWAP_16; in SelectCMP_SWAP()
2471 Opcode = ARM::CMP_SWAP_32; in SelectCMP_SWAP()
2531 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
2537 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ()
2546 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
2550 NewN = EmitShift(ARM::tLSRri, X, Range->second); in SelectCMPZ()
2555 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
2562 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
2563 NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0), in SelectCMPZ()
2614 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other, in Select()
2624 ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, in Select()
2655 CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI, in Select()
2660 ARM::t2ADDri : ARM::ADDri); in Select()
2693 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
2698 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
2712 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
2717 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
2754 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select()
2757 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops)); in Select()
2764 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops)); in Select()
2779 ? ARM::t2MOVTi16 in Select()
2780 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); in Select()
2809 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
2823 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
2831 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
2842 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
2850 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
2879 unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS; in Select()
2912 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; in Select()
2977 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops); in Select()
2979 unsigned Opc = (Addend < 1<<3) ? ARM::tADDi3 : ARM::tADDi8; in Select()
2980 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select()
3032 case MVT::v8i8: Opc = ARM::VZIPd8; break; in Select()
3034 case MVT::v4i16: Opc = ARM::VZIPd16; break; in Select()
3037 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
3038 case MVT::v16i8: Opc = ARM::VZIPq8; break; in Select()
3040 case MVT::v8i16: Opc = ARM::VZIPq16; break; in Select()
3042 case MVT::v4i32: Opc = ARM::VZIPq32; break; in Select()
3055 case MVT::v8i8: Opc = ARM::VUZPd8; break; in Select()
3057 case MVT::v4i16: Opc = ARM::VUZPd16; break; in Select()
3060 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
3061 case MVT::v16i8: Opc = ARM::VUZPq8; break; in Select()
3063 case MVT::v8i16: Opc = ARM::VUZPq16; break; in Select()
3065 case MVT::v4i32: Opc = ARM::VUZPq32; break; in Select()
3078 case MVT::v8i8: Opc = ARM::VTRNd8; break; in Select()
3080 case MVT::v4i16: Opc = ARM::VTRNd16; break; in Select()
3082 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
3083 case MVT::v16i8: Opc = ARM::VTRNq8; break; in Select()
3085 case MVT::v8i16: Opc = ARM::VTRNq16; break; in Select()
3087 case MVT::v4i32: Opc = ARM::VTRNq32; break; in Select()
3119 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8, ARM::VLD1DUPd16, in Select()
3120 ARM::VLD1DUPd32 }; in Select()
3121 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8, ARM::VLD1DUPq16, in Select()
3122 ARM::VLD1DUPq32 }; in Select()
3128 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
3129 ARM::VLD2DUPd32 }; in Select()
3135 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
3136 ARM::VLD3DUPd16Pseudo, in Select()
3137 ARM::VLD3DUPd32Pseudo }; in Select()
3143 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
3144 ARM::VLD4DUPd16Pseudo, in Select()
3145 ARM::VLD4DUPd32Pseudo }; in Select()
3151 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8wb_fixed, in Select()
3152 ARM::VLD1DUPd16wb_fixed, in Select()
3153 ARM::VLD1DUPd32wb_fixed }; in Select()
3154 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8wb_fixed, in Select()
3155 ARM::VLD1DUPq16wb_fixed, in Select()
3156 ARM::VLD1DUPq32wb_fixed }; in Select()
3162 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed, in Select()
3163 ARM::VLD2DUPd16wb_fixed, in Select()
3164 ARM::VLD2DUPd32wb_fixed }; in Select()
3170 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, in Select()
3171 ARM::VLD3DUPd16Pseudo_UPD, in Select()
3172 ARM::VLD3DUPd32Pseudo_UPD }; in Select()
3178 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, in Select()
3179 ARM::VLD4DUPd16Pseudo_UPD, in Select()
3180 ARM::VLD4DUPd32Pseudo_UPD }; in Select()
3186 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed, in Select()
3187 ARM::VLD1d16wb_fixed, in Select()
3188 ARM::VLD1d32wb_fixed, in Select()
3189 ARM::VLD1d64wb_fixed }; in Select()
3190 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed, in Select()
3191 ARM::VLD1q16wb_fixed, in Select()
3192 ARM::VLD1q32wb_fixed, in Select()
3193 ARM::VLD1q64wb_fixed }; in Select()
3199 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed, in Select()
3200 ARM::VLD2d16wb_fixed, in Select()
3201 ARM::VLD2d32wb_fixed, in Select()
3202 ARM::VLD1q64wb_fixed}; in Select()
3203 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed, in Select()
3204 ARM::VLD2q16PseudoWB_fixed, in Select()
3205 ARM::VLD2q32PseudoWB_fixed }; in Select()
3211 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, in Select()
3212 ARM::VLD3d16Pseudo_UPD, in Select()
3213 ARM::VLD3d32Pseudo_UPD, in Select()
3214 ARM::VLD1d64TPseudoWB_fixed}; in Select()
3215 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
3216 ARM::VLD3q16Pseudo_UPD, in Select()
3217 ARM::VLD3q32Pseudo_UPD }; in Select()
3218 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD, in Select()
3219 ARM::VLD3q16oddPseudo_UPD, in Select()
3220 ARM::VLD3q32oddPseudo_UPD }; in Select()
3226 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, in Select()
3227 ARM::VLD4d16Pseudo_UPD, in Select()
3228 ARM::VLD4d32Pseudo_UPD, in Select()
3229 ARM::VLD1d64QPseudoWB_fixed}; in Select()
3230 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, in Select()
3231 ARM::VLD4q16Pseudo_UPD, in Select()
3232 ARM::VLD4q32Pseudo_UPD }; in Select()
3233 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD, in Select()
3234 ARM::VLD4q16oddPseudo_UPD, in Select()
3235 ARM::VLD4q32oddPseudo_UPD }; in Select()
3241 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, in Select()
3242 ARM::VLD2LNd16Pseudo_UPD, in Select()
3243 ARM::VLD2LNd32Pseudo_UPD }; in Select()
3244 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD, in Select()
3245 ARM::VLD2LNq32Pseudo_UPD }; in Select()
3251 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, in Select()
3252 ARM::VLD3LNd16Pseudo_UPD, in Select()
3253 ARM::VLD3LNd32Pseudo_UPD }; in Select()
3254 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD, in Select()
3255 ARM::VLD3LNq32Pseudo_UPD }; in Select()
3261 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, in Select()
3262 ARM::VLD4LNd16Pseudo_UPD, in Select()
3263 ARM::VLD4LNd32Pseudo_UPD }; in Select()
3264 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD, in Select()
3265 ARM::VLD4LNq32Pseudo_UPD }; in Select()
3271 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed, in Select()
3272 ARM::VST1d16wb_fixed, in Select()
3273 ARM::VST1d32wb_fixed, in Select()
3274 ARM::VST1d64wb_fixed }; in Select()
3275 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed, in Select()
3276 ARM::VST1q16wb_fixed, in Select()
3277 ARM::VST1q32wb_fixed, in Select()
3278 ARM::VST1q64wb_fixed }; in Select()
3284 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed, in Select()
3285 ARM::VST2d16wb_fixed, in Select()
3286 ARM::VST2d32wb_fixed, in Select()
3287 ARM::VST1q64wb_fixed}; in Select()
3288 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed, in Select()
3289 ARM::VST2q16PseudoWB_fixed, in Select()
3290 ARM::VST2q32PseudoWB_fixed }; in Select()
3296 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD, in Select()
3297 ARM::VST3d16Pseudo_UPD, in Select()
3298 ARM::VST3d32Pseudo_UPD, in Select()
3299 ARM::VST1d64TPseudoWB_fixed}; in Select()
3300 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
3301 ARM::VST3q16Pseudo_UPD, in Select()
3302 ARM::VST3q32Pseudo_UPD }; in Select()
3303 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD, in Select()
3304 ARM::VST3q16oddPseudo_UPD, in Select()
3305 ARM::VST3q32oddPseudo_UPD }; in Select()
3311 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD, in Select()
3312 ARM::VST4d16Pseudo_UPD, in Select()
3313 ARM::VST4d32Pseudo_UPD, in Select()
3314 ARM::VST1d64QPseudoWB_fixed}; in Select()
3315 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, in Select()
3316 ARM::VST4q16Pseudo_UPD, in Select()
3317 ARM::VST4q32Pseudo_UPD }; in Select()
3318 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD, in Select()
3319 ARM::VST4q16oddPseudo_UPD, in Select()
3320 ARM::VST4q32oddPseudo_UPD }; in Select()
3326 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, in Select()
3327 ARM::VST2LNd16Pseudo_UPD, in Select()
3328 ARM::VST2LNd32Pseudo_UPD }; in Select()
3329 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD, in Select()
3330 ARM::VST2LNq32Pseudo_UPD }; in Select()
3336 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, in Select()
3337 ARM::VST3LNd16Pseudo_UPD, in Select()
3338 ARM::VST3LNd32Pseudo_UPD }; in Select()
3339 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD, in Select()
3340 ARM::VST3LNq32Pseudo_UPD }; in Select()
3346 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, in Select()
3347 ARM::VST4LNd16Pseudo_UPD, in Select()
3348 ARM::VST4LNd32Pseudo_UPD }; in Select()
3349 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD, in Select()
3350 ARM::VST4LNq32Pseudo_UPD }; in Select()
3369 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2); in Select()
3371 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2); in Select()
3381 if (Opc != ARM::MRRC2) { in Select()
3402 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD) in Select()
3403 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD); in Select()
3430 CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in Select()
3443 CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in Select()
3481 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD) in Select()
3482 : (IsRelease ? ARM::STLEXD : ARM::STREXD); in Select()
3494 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, in Select()
3495 ARM::VLD1d32, ARM::VLD1d64 }; in Select()
3496 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
3497 ARM::VLD1q32, ARM::VLD1q64}; in Select()
3503 static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
3504 ARM::VLD1q32, ARM::VLD1q64 }; in Select()
3505 static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
3506 ARM::VLD1d16QPseudo, in Select()
3507 ARM::VLD1d32QPseudo, in Select()
3508 ARM::VLD1d64QPseudo }; in Select()
3514 static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo, in Select()
3515 ARM::VLD1d16TPseudo, in Select()
3516 ARM::VLD1d32TPseudo, in Select()
3517 ARM::VLD1d64TPseudo }; in Select()
3518 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD, in Select()
3519 ARM::VLD1q16LowTPseudo_UPD, in Select()
3520 ARM::VLD1q32LowTPseudo_UPD, in Select()
3521 ARM::VLD1q64LowTPseudo_UPD }; in Select()
3522 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo, in Select()
3523 ARM::VLD1q16HighTPseudo, in Select()
3524 ARM::VLD1q32HighTPseudo, in Select()
3525 ARM::VLD1q64HighTPseudo }; in Select()
3531 static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
3532 ARM::VLD1d16QPseudo, in Select()
3533 ARM::VLD1d32QPseudo, in Select()
3534 ARM::VLD1d64QPseudo }; in Select()
3535 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD, in Select()
3536 ARM::VLD1q16LowQPseudo_UPD, in Select()
3537 ARM::VLD1q32LowQPseudo_UPD, in Select()
3538 ARM::VLD1q64LowQPseudo_UPD }; in Select()
3539 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo, in Select()
3540 ARM::VLD1q16HighQPseudo, in Select()
3541 ARM::VLD1q32HighQPseudo, in Select()
3542 ARM::VLD1q64HighQPseudo }; in Select()
3548 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16, in Select()
3549 ARM::VLD2d32, ARM::VLD1q64 }; in Select()
3550 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, in Select()
3551 ARM::VLD2q32Pseudo }; in Select()
3557 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo, in Select()
3558 ARM::VLD3d16Pseudo, in Select()
3559 ARM::VLD3d32Pseudo, in Select()
3560 ARM::VLD1d64TPseudo }; in Select()
3561 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
3562 ARM::VLD3q16Pseudo_UPD, in Select()
3563 ARM::VLD3q32Pseudo_UPD }; in Select()
3564 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo, in Select()
3565 ARM::VLD3q16oddPseudo, in Select()
3566 ARM::VLD3q32oddPseudo }; in Select()
3572 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo, in Select()
3573 ARM::VLD4d16Pseudo, in Select()
3574 ARM::VLD4d32Pseudo, in Select()
3575 ARM::VLD1d64QPseudo }; in Select()
3576 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, in Select()
3577 ARM::VLD4q16Pseudo_UPD, in Select()
3578 ARM::VLD4q32Pseudo_UPD }; in Select()
3579 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo, in Select()
3580 ARM::VLD4q16oddPseudo, in Select()
3581 ARM::VLD4q32oddPseudo }; in Select()
3587 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
3588 ARM::VLD2DUPd32, ARM::VLD1q64 }; in Select()
3589 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo, in Select()
3590 ARM::VLD2DUPq16EvenPseudo, in Select()
3591 ARM::VLD2DUPq32EvenPseudo }; in Select()
3592 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudo, in Select()
3593 ARM::VLD2DUPq16OddPseudo, in Select()
3594 ARM::VLD2DUPq32OddPseudo }; in Select()
3601 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
3602 ARM::VLD3DUPd16Pseudo, in Select()
3603 ARM::VLD3DUPd32Pseudo, in Select()
3604 ARM::VLD1d64TPseudo }; in Select()
3605 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo, in Select()
3606 ARM::VLD3DUPq16EvenPseudo, in Select()
3607 ARM::VLD3DUPq32EvenPseudo }; in Select()
3608 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo, in Select()
3609 ARM::VLD3DUPq16OddPseudo, in Select()
3610 ARM::VLD3DUPq32OddPseudo }; in Select()
3617 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
3618 ARM::VLD4DUPd16Pseudo, in Select()
3619 ARM::VLD4DUPd32Pseudo, in Select()
3620 ARM::VLD1d64QPseudo }; in Select()
3621 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo, in Select()
3622 ARM::VLD4DUPq16EvenPseudo, in Select()
3623 ARM::VLD4DUPq32EvenPseudo }; in Select()
3624 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo, in Select()
3625 ARM::VLD4DUPq16OddPseudo, in Select()
3626 ARM::VLD4DUPq32OddPseudo }; in Select()
3633 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo, in Select()
3634 ARM::VLD2LNd16Pseudo, in Select()
3635 ARM::VLD2LNd32Pseudo }; in Select()
3636 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo, in Select()
3637 ARM::VLD2LNq32Pseudo }; in Select()
3643 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo, in Select()
3644 ARM::VLD3LNd16Pseudo, in Select()
3645 ARM::VLD3LNd32Pseudo }; in Select()
3646 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo, in Select()
3647 ARM::VLD3LNq32Pseudo }; in Select()
3653 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo, in Select()
3654 ARM::VLD4LNd16Pseudo, in Select()
3655 ARM::VLD4LNd32Pseudo }; in Select()
3656 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo, in Select()
3657 ARM::VLD4LNq32Pseudo }; in Select()
3663 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, in Select()
3664 ARM::VST1d32, ARM::VST1d64 }; in Select()
3665 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
3666 ARM::VST1q32, ARM::VST1q64 }; in Select()
3672 static const uint16_t DOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
3673 ARM::VST1q32, ARM::VST1q64 }; in Select()
3674 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudo, in Select()
3675 ARM::VST1d16QPseudo, in Select()
3676 ARM::VST1d32QPseudo, in Select()
3677 ARM::VST1d64QPseudo }; in Select()
3683 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudo, in Select()
3684 ARM::VST1d16TPseudo, in Select()
3685 ARM::VST1d32TPseudo, in Select()
3686 ARM::VST1d64TPseudo }; in Select()
3687 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD, in Select()
3688 ARM::VST1q16LowTPseudo_UPD, in Select()
3689 ARM::VST1q32LowTPseudo_UPD, in Select()
3690 ARM::VST1q64LowTPseudo_UPD }; in Select()
3691 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo, in Select()
3692 ARM::VST1q16HighTPseudo, in Select()
3693 ARM::VST1q32HighTPseudo, in Select()
3694 ARM::VST1q64HighTPseudo }; in Select()
3700 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudo, in Select()
3701 ARM::VST1d16QPseudo, in Select()
3702 ARM::VST1d32QPseudo, in Select()
3703 ARM::VST1d64QPseudo }; in Select()
3704 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD, in Select()
3705 ARM::VST1q16LowQPseudo_UPD, in Select()
3706 ARM::VST1q32LowQPseudo_UPD, in Select()
3707 ARM::VST1q64LowQPseudo_UPD }; in Select()
3708 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo, in Select()
3709 ARM::VST1q16HighQPseudo, in Select()
3710 ARM::VST1q32HighQPseudo, in Select()
3711 ARM::VST1q64HighQPseudo }; in Select()
3717 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16, in Select()
3718 ARM::VST2d32, ARM::VST1q64 }; in Select()
3719 static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo, in Select()
3720 ARM::VST2q32Pseudo }; in Select()
3726 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo, in Select()
3727 ARM::VST3d16Pseudo, in Select()
3728 ARM::VST3d32Pseudo, in Select()
3729 ARM::VST1d64TPseudo }; in Select()
3730 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
3731 ARM::VST3q16Pseudo_UPD, in Select()
3732 ARM::VST3q32Pseudo_UPD }; in Select()
3733 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo, in Select()
3734 ARM::VST3q16oddPseudo, in Select()
3735 ARM::VST3q32oddPseudo }; in Select()
3741 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo, in Select()
3742 ARM::VST4d16Pseudo, in Select()
3743 ARM::VST4d32Pseudo, in Select()
3744 ARM::VST1d64QPseudo }; in Select()
3745 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, in Select()
3746 ARM::VST4q16Pseudo_UPD, in Select()
3747 ARM::VST4q32Pseudo_UPD }; in Select()
3748 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo, in Select()
3749 ARM::VST4q16oddPseudo, in Select()
3750 ARM::VST4q32oddPseudo }; in Select()
3756 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo, in Select()
3757 ARM::VST2LNd16Pseudo, in Select()
3758 ARM::VST2LNd32Pseudo }; in Select()
3759 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo, in Select()
3760 ARM::VST2LNq32Pseudo }; in Select()
3766 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo, in Select()
3767 ARM::VST3LNd16Pseudo, in Select()
3768 ARM::VST3LNd32Pseudo }; in Select()
3769 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo, in Select()
3770 ARM::VST3LNq32Pseudo }; in Select()
3776 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo, in Select()
3777 ARM::VST4LNd16Pseudo, in Select()
3778 ARM::VST4LNd32Pseudo }; in Select()
3779 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo, in Select()
3780 ARM::VST4LNq32Pseudo }; in Select()
3937 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
3942 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in tryReadRegister()
3961 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in tryReadRegister()
3970 .Case("fpscr", ARM::VMRS) in tryReadRegister()
3971 .Case("fpexc", ARM::VMRS_FPEXC) in tryReadRegister()
3972 .Case("fpsid", ARM::VMRS_FPSID) in tryReadRegister()
3973 .Case("mvfr0", ARM::VMRS_MVFR0) in tryReadRegister()
3974 .Case("mvfr1", ARM::VMRS_MVFR1) in tryReadRegister()
3975 .Case("mvfr2", ARM::VMRS_MVFR2) in tryReadRegister()
3976 .Case("fpinst", ARM::VMRS_FPINST) in tryReadRegister()
3977 .Case("fpinst2", ARM::VMRS_FPINST2) in tryReadRegister()
3984 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8()) in tryReadRegister()
4006 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
4015 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
4024 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL, in tryReadRegister()
4051 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
4056 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in tryWriteRegister()
4076 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in tryWriteRegister()
4085 .Case("fpscr", ARM::VMSR) in tryWriteRegister()
4086 .Case("fpexc", ARM::VMSR_FPEXC) in tryWriteRegister()
4087 .Case("fpsid", ARM::VMSR_FPSID) in tryWriteRegister()
4088 .Case("fpinst", ARM::VMSR_FPINST) in tryWriteRegister()
4089 .Case("fpinst2", ARM::VMSR_FPINST2) in tryWriteRegister()
4116 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops)); in tryWriteRegister()
4128 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR, in tryWriteRegister()
4208 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID)) in tryInlineAsm()
4225 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
4234 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
4236 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
4261 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
4277 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID); in tryInlineAsm()