Lines Matching refs:ARM
156 if ((MI.getOpcode() == ARM::LDR_POST_IMM || in isCSRestore()
157 MI.getOpcode() == ARM::LDR_POST_REG || in isCSRestore()
158 MI.getOpcode() == ARM::t2LDR_POST) && in isCSRestore()
160 MI.getOperand(1).getReg() == ARM::SP) in isCSRestore()
185 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
192 case ARM::VSTMDDB_UPD: in sizeOfSPAdjustment()
195 case ARM::STMDB_UPD: in sizeOfSPAdjustment()
196 case ARM::t2STMDB_UPD: in sizeOfSPAdjustment()
199 case ARM::t2STR_PRE: in sizeOfSPAdjustment()
200 case ARM::STR_PRE_IMM: in sizeOfSPAdjustment()
303 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
308 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
318 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
323 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
333 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
415 case ARM::R8: in emitPrologue()
416 case ARM::R9: in emitPrologue()
417 case ARM::R10: in emitPrologue()
418 case ARM::R11: in emitPrologue()
419 case ARM::R12: in emitPrologue()
425 case ARM::R0: in emitPrologue()
426 case ARM::R1: in emitPrologue()
427 case ARM::R2: in emitPrologue()
428 case ARM::R3: in emitPrologue()
429 case ARM::R4: in emitPrologue()
430 case ARM::R5: in emitPrologue()
431 case ARM::R6: in emitPrologue()
432 case ARM::R7: in emitPrologue()
433 case ARM::LR: in emitPrologue()
440 if (Reg == ARM::D8) in emitPrologue()
442 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) in emitPrologue()
497 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) { in emitPrologue()
518 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
523 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
533 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
536 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
540 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
544 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
546 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
547 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
552 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP) in emitPrologue()
553 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
554 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
594 dl, TII, FramePtr, ARM::SP, in emitPrologue()
624 case ARM::R8: in emitPrologue()
625 case ARM::R9: in emitPrologue()
626 case ARM::R10: in emitPrologue()
627 case ARM::R11: in emitPrologue()
628 case ARM::R12: in emitPrologue()
632 case ARM::R0: in emitPrologue()
633 case ARM::R1: in emitPrologue()
634 case ARM::R2: in emitPrologue()
635 case ARM::R3: in emitPrologue()
636 case ARM::R4: in emitPrologue()
637 case ARM::R5: in emitPrologue()
638 case ARM::R6: in emitPrologue()
639 case ARM::R7: in emitPrologue()
640 case ARM::LR: in emitPrologue()
657 case ARM::R8: in emitPrologue()
658 case ARM::R9: in emitPrologue()
659 case ARM::R10: in emitPrologue()
660 case ARM::R11: in emitPrologue()
661 case ARM::R12: in emitPrologue()
683 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && in emitPrologue()
684 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { in emitPrologue()
719 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
729 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
730 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
732 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
734 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
735 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
749 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
750 .addReg(ARM::SP) in emitPrologue()
754 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
755 .addReg(ARM::SP) in emitPrologue()
817 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, in emitEpilogue()
827 assert(!MFI.getPristineRegs(MF).test(ARM::R4) && in emitEpilogue()
829 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
831 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
832 .addReg(ARM::R4) in emitEpilogue()
838 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
843 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
856 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD) in emitEpilogue()
895 FrameReg = ARM::SP; in ResolveFrameIndexReference()
987 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPushInst()
1016 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
1017 .addReg(ARM::SP) in emitPushInst()
1023 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) in emitPushInst()
1025 .addReg(ARM::SP) in emitPushInst()
1058 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri); in emitPopInst()
1060 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR; in emitPopInst()
1062 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl || in emitPopInst()
1063 RetOpcode == ARM::tTRAP; in emitPopInst()
1077 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPopInst()
1080 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && in emitPopInst()
1083 Reg = ARM::PC; in emitPopInst()
1086 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; in emitPopInst()
1091 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; in emitPopInst()
1112 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1113 .addReg(ARM::SP) in emitPopInst()
1127 if (Regs[0] == ARM::PC) in emitPopInst()
1128 Regs[0] = ARM::LR; in emitPopInst()
1131 .addReg(ARM::SP, RegState::Define) in emitPopInst()
1132 .addReg(ARM::SP); in emitPopInst()
1135 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { in emitPopInst()
1169 unsigned DNum = CSI[i].getReg() - ARM::D8; in emitAlignedDPRCS2Spills()
1200 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; in emitAlignedDPRCS2Spills()
1201 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1202 .addReg(ARM::SP) in emitAlignedDPRCS2Spills()
1213 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1219 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; in emitAlignedDPRCS2Spills()
1220 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1221 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1228 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills()
1233 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1234 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1236 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4) in emitAlignedDPRCS2Spills()
1237 .addReg(ARM::R4, RegState::Kill) in emitAlignedDPRCS2Spills()
1252 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1253 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1255 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1256 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1267 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1268 &ARM::QPRRegClass); in emitAlignedDPRCS2Spills()
1270 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1271 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1283 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1285 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1291 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Spills()
1318 assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); in skipAlignedDPRCS2Spills()
1340 if (CSI[i].getReg() == ARM::D8) { in emitAlignedDPRCS2Restores()
1353 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in emitAlignedDPRCS2Restores()
1354 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1361 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Restores()
1365 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1366 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1367 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1368 .addReg(ARM::R4, RegState::Define) in emitAlignedDPRCS2Restores()
1369 .addReg(ARM::R4, RegState::Kill) in emitAlignedDPRCS2Restores()
1383 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1384 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1385 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1386 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1396 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1397 &ARM::QPRRegClass); in emitAlignedDPRCS2Restores()
1398 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1399 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1408 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1409 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1414 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Restores()
1427 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; in spillCalleeSavedRegisters()
1429 ARM::t2STR_PRE : ARM::STR_PRE_IMM; in spillCalleeSavedRegisters()
1430 unsigned FltOpc = ARM::VSTMDDB_UPD; in spillCalleeSavedRegisters()
1465 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; in restoreCalleeSavedRegisters()
1466 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; in restoreCalleeSavedRegisters()
1467 unsigned FltOpc = ARM::VLDMDIA_UPD; in restoreCalleeSavedRegisters()
1505 if (MI.getOpcode() == ARM::ADDri) { in estimateRSStackSizeLimit()
1576 if (!SavedRegs.test(ARM::D8 + NumSpills)) in checkNumAlignedDPRCS2Regs()
1587 SavedRegs.set(ARM::R4); in checkNumAlignedDPRCS2Regs()
1623 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1632 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1633 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1639 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1649 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1670 if (!ARM::GPRRegClass.contains(Reg)) { in determineCalleeSaves()
1672 if (ARM::SPRRegClass.contains(Reg)) in determineCalleeSaves()
1674 else if (ARM::DPRRegClass.contains(Reg)) in determineCalleeSaves()
1676 else if (ARM::QPRRegClass.contains(Reg)) in determineCalleeSaves()
1686 if (Reg == ARM::LR) in determineCalleeSaves()
1694 case ARM::LR: in determineCalleeSaves()
1697 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1698 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1699 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1700 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1713 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1714 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1715 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1716 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1717 case ARM::LR: in determineCalleeSaves()
1790 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1793 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR); in determineCalleeSaves()
1801 if (FramePtr == ARM::R7) in determineCalleeSaves()
1825 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { in determineCalleeSaves()
1846 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
1863 if (SavedRegs.test(ARM::R7)) { in determineCalleeSaves()
1868 AvailableRegs.push_back(ARM::R7); in determineCalleeSaves()
1876 for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { in determineCalleeSaves()
1889 !(MF.getRegInfo().isLiveIn(ARM::LR) && in determineCalleeSaves()
1891 if (SavedRegs.test(ARM::LR)) { in determineCalleeSaves()
1896 AvailableRegs.push_back(ARM::LR); in determineCalleeSaves()
1918 if (Reg == ARM::LR) in determineCalleeSaves()
1932 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1935 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR); in determineCalleeSaves()
1940 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR)) in determineCalleeSaves()
1956 (STI.isTargetWindows() && Reg == ARM::R11) || in determineCalleeSaves()
1958 (Reg == ARM::LR && !ExpensiveLRRestore)) { in determineCalleeSaves()
1992 Reg == ARM::LR)) { in determineCalleeSaves()
2019 const TargetRegisterClass &RC = ARM::GPRRegClass; in determineCalleeSaves()
2028 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2063 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
2067 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
2172 unsigned ScratchReg0 = ARM::R4; in adjustForSegmentedStacks()
2173 unsigned ScratchReg1 = ARM::R5; in adjustForSegmentedStacks()
2240 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
2245 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2246 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2247 .addReg(ARM::SP) in adjustForSegmentedStacks()
2270 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
2271 .addReg(ARM::SP) in adjustForSegmentedStacks()
2274 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
2275 .addReg(ARM::SP) in adjustForSegmentedStacks()
2282 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1) in adjustForSegmentedStacks()
2288 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
2289 .addReg(ARM::SP) in adjustForSegmentedStacks()
2303 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
2308 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
2315 BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0) in adjustForSegmentedStacks()
2329 BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0) in adjustForSegmentedStacks()
2337 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr; in adjustForSegmentedStacks()
2344 Opcode = Thumb ? ARM::tBcc : ARM::Bcc; in adjustForSegmentedStacks()
2347 .addReg(ARM::CPSR); in adjustForSegmentedStacks()
2357 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0) in adjustForSegmentedStacks()
2362 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
2370 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1) in adjustForSegmentedStacks()
2375 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
2383 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
2385 .addReg(ARM::LR); in adjustForSegmentedStacks()
2387 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2388 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2389 .addReg(ARM::SP) in adjustForSegmentedStacks()
2391 .addReg(ARM::LR); in adjustForSegmentedStacks()
2401 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); in adjustForSegmentedStacks()
2407 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
2411 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
2418 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2421 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
2425 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
2426 .addReg(ARM::LR, RegState::Define) in adjustForSegmentedStacks()
2427 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2428 .addReg(ARM::SP) in adjustForSegmentedStacks()
2433 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2434 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2435 .addReg(ARM::SP) in adjustForSegmentedStacks()
2437 .addReg(ARM::LR); in adjustForSegmentedStacks()
2445 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2450 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2451 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2452 .addReg(ARM::SP) in adjustForSegmentedStacks()
2469 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2474 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2475 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2476 .addReg(ARM::SP) in adjustForSegmentedStacks()