Lines Matching refs:ARM
206 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
217 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
221 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
222 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
223 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
224 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
228 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
229 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
254 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
258 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
259 case ARM_AM::da: return ARM::LDMDA; in getLoadStoreMultipleOpcode()
260 case ARM_AM::db: return ARM::LDMDB; in getLoadStoreMultipleOpcode()
261 case ARM_AM::ib: return ARM::LDMIB; in getLoadStoreMultipleOpcode()
263 case ARM::STRi12: in getLoadStoreMultipleOpcode()
267 case ARM_AM::ia: return ARM::STMIA; in getLoadStoreMultipleOpcode()
268 case ARM_AM::da: return ARM::STMDA; in getLoadStoreMultipleOpcode()
269 case ARM_AM::db: return ARM::STMDB; in getLoadStoreMultipleOpcode()
270 case ARM_AM::ib: return ARM::STMIB; in getLoadStoreMultipleOpcode()
272 case ARM::tLDRi: in getLoadStoreMultipleOpcode()
273 case ARM::tLDRspi: in getLoadStoreMultipleOpcode()
279 case ARM_AM::ia: return ARM::tLDMIA; in getLoadStoreMultipleOpcode()
281 case ARM::tSTRi: in getLoadStoreMultipleOpcode()
282 case ARM::tSTRspi: in getLoadStoreMultipleOpcode()
287 case ARM_AM::ia: return ARM::tSTMIA_UPD; in getLoadStoreMultipleOpcode()
289 case ARM::t2LDRi8: in getLoadStoreMultipleOpcode()
290 case ARM::t2LDRi12: in getLoadStoreMultipleOpcode()
294 case ARM_AM::ia: return ARM::t2LDMIA; in getLoadStoreMultipleOpcode()
295 case ARM_AM::db: return ARM::t2LDMDB; in getLoadStoreMultipleOpcode()
297 case ARM::t2STRi8: in getLoadStoreMultipleOpcode()
298 case ARM::t2STRi12: in getLoadStoreMultipleOpcode()
302 case ARM_AM::ia: return ARM::t2STMIA; in getLoadStoreMultipleOpcode()
303 case ARM_AM::db: return ARM::t2STMDB; in getLoadStoreMultipleOpcode()
305 case ARM::VLDRS: in getLoadStoreMultipleOpcode()
309 case ARM_AM::ia: return ARM::VLDMSIA; in getLoadStoreMultipleOpcode()
312 case ARM::VSTRS: in getLoadStoreMultipleOpcode()
316 case ARM_AM::ia: return ARM::VSTMSIA; in getLoadStoreMultipleOpcode()
319 case ARM::VLDRD: in getLoadStoreMultipleOpcode()
323 case ARM_AM::ia: return ARM::VLDMDIA; in getLoadStoreMultipleOpcode()
326 case ARM::VSTRD: in getLoadStoreMultipleOpcode()
330 case ARM_AM::ia: return ARM::VSTMDIA; in getLoadStoreMultipleOpcode()
339 case ARM::LDMIA_RET: in getLoadStoreMultipleSubMode()
340 case ARM::LDMIA: in getLoadStoreMultipleSubMode()
341 case ARM::LDMIA_UPD: in getLoadStoreMultipleSubMode()
342 case ARM::STMIA: in getLoadStoreMultipleSubMode()
343 case ARM::STMIA_UPD: in getLoadStoreMultipleSubMode()
344 case ARM::tLDMIA: in getLoadStoreMultipleSubMode()
345 case ARM::tLDMIA_UPD: in getLoadStoreMultipleSubMode()
346 case ARM::tSTMIA_UPD: in getLoadStoreMultipleSubMode()
347 case ARM::t2LDMIA_RET: in getLoadStoreMultipleSubMode()
348 case ARM::t2LDMIA: in getLoadStoreMultipleSubMode()
349 case ARM::t2LDMIA_UPD: in getLoadStoreMultipleSubMode()
350 case ARM::t2STMIA: in getLoadStoreMultipleSubMode()
351 case ARM::t2STMIA_UPD: in getLoadStoreMultipleSubMode()
352 case ARM::VLDMSIA: in getLoadStoreMultipleSubMode()
353 case ARM::VLDMSIA_UPD: in getLoadStoreMultipleSubMode()
354 case ARM::VSTMSIA: in getLoadStoreMultipleSubMode()
355 case ARM::VSTMSIA_UPD: in getLoadStoreMultipleSubMode()
356 case ARM::VLDMDIA: in getLoadStoreMultipleSubMode()
357 case ARM::VLDMDIA_UPD: in getLoadStoreMultipleSubMode()
358 case ARM::VSTMDIA: in getLoadStoreMultipleSubMode()
359 case ARM::VSTMDIA_UPD: in getLoadStoreMultipleSubMode()
362 case ARM::LDMDA: in getLoadStoreMultipleSubMode()
363 case ARM::LDMDA_UPD: in getLoadStoreMultipleSubMode()
364 case ARM::STMDA: in getLoadStoreMultipleSubMode()
365 case ARM::STMDA_UPD: in getLoadStoreMultipleSubMode()
368 case ARM::LDMDB: in getLoadStoreMultipleSubMode()
369 case ARM::LDMDB_UPD: in getLoadStoreMultipleSubMode()
370 case ARM::STMDB: in getLoadStoreMultipleSubMode()
371 case ARM::STMDB_UPD: in getLoadStoreMultipleSubMode()
372 case ARM::t2LDMDB: in getLoadStoreMultipleSubMode()
373 case ARM::t2LDMDB_UPD: in getLoadStoreMultipleSubMode()
374 case ARM::t2STMDB: in getLoadStoreMultipleSubMode()
375 case ARM::t2STMDB_UPD: in getLoadStoreMultipleSubMode()
376 case ARM::VLDMSDB_UPD: in getLoadStoreMultipleSubMode()
377 case ARM::VSTMSDB_UPD: in getLoadStoreMultipleSubMode()
378 case ARM::VLDMDDB_UPD: in getLoadStoreMultipleSubMode()
379 case ARM::VSTMDDB_UPD: in getLoadStoreMultipleSubMode()
382 case ARM::LDMIB: in getLoadStoreMultipleSubMode()
383 case ARM::LDMIB_UPD: in getLoadStoreMultipleSubMode()
384 case ARM::STMIB: in getLoadStoreMultipleSubMode()
385 case ARM::STMIB_UPD: in getLoadStoreMultipleSubMode()
391 return Opc == ARM::tLDRi || Opc == ARM::tLDRspi; in isT1i32Load()
395 return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8; in isT2i32Load()
399 return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ; in isi32Load()
403 return Opc == ARM::tSTRi || Opc == ARM::tSTRspi; in isT1i32Store()
407 return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8; in isT2i32Store()
411 return Opc == ARM::STRi12 || isT1i32Store(Opc) || isT2i32Store(Opc); in isi32Store()
415 return isi32Load(Opc) || Opc == ARM::VLDRS || Opc == ARM::VLDRD; in isLoadSingle()
421 case ARM::tLDRi: in getImmScale()
422 case ARM::tSTRi: in getImmScale()
423 case ARM::tLDRspi: in getImmScale()
424 case ARM::tSTRspi: in getImmScale()
426 case ARM::tLDRHi: in getImmScale()
427 case ARM::tSTRHi: in getImmScale()
429 case ARM::tLDRBi: in getImmScale()
430 case ARM::tSTRBi: in getImmScale()
438 case ARM::LDRi12: in getLSMultipleTransferSize()
439 case ARM::STRi12: in getLSMultipleTransferSize()
440 case ARM::tLDRi: in getLSMultipleTransferSize()
441 case ARM::tSTRi: in getLSMultipleTransferSize()
442 case ARM::tLDRspi: in getLSMultipleTransferSize()
443 case ARM::tSTRspi: in getLSMultipleTransferSize()
444 case ARM::t2LDRi8: in getLSMultipleTransferSize()
445 case ARM::t2LDRi12: in getLSMultipleTransferSize()
446 case ARM::t2STRi8: in getLSMultipleTransferSize()
447 case ARM::t2STRi12: in getLSMultipleTransferSize()
448 case ARM::VLDRS: in getLSMultipleTransferSize()
449 case ARM::VSTRS: in getLSMultipleTransferSize()
451 case ARM::VLDRD: in getLSMultipleTransferSize()
452 case ARM::VSTRD: in getLSMultipleTransferSize()
454 case ARM::LDMIA: in getLSMultipleTransferSize()
455 case ARM::LDMDA: in getLSMultipleTransferSize()
456 case ARM::LDMDB: in getLSMultipleTransferSize()
457 case ARM::LDMIB: in getLSMultipleTransferSize()
458 case ARM::STMIA: in getLSMultipleTransferSize()
459 case ARM::STMDA: in getLSMultipleTransferSize()
460 case ARM::STMDB: in getLSMultipleTransferSize()
461 case ARM::STMIB: in getLSMultipleTransferSize()
462 case ARM::tLDMIA: in getLSMultipleTransferSize()
463 case ARM::tLDMIA_UPD: in getLSMultipleTransferSize()
464 case ARM::tSTMIA_UPD: in getLSMultipleTransferSize()
465 case ARM::t2LDMIA: in getLSMultipleTransferSize()
466 case ARM::t2LDMDB: in getLSMultipleTransferSize()
467 case ARM::t2STMIA: in getLSMultipleTransferSize()
468 case ARM::t2STMDB: in getLSMultipleTransferSize()
469 case ARM::VLDMSIA: in getLSMultipleTransferSize()
470 case ARM::VSTMSIA: in getLSMultipleTransferSize()
472 case ARM::VLDMDIA: in getLSMultipleTransferSize()
473 case ARM::VSTMDIA: in getLSMultipleTransferSize()
496 Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; in UpdateBaseRegUses()
498 Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi; in UpdateBaseRegUses()
517 } else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) && in UpdateBaseRegUses()
524 Offset = (Opc == ARM::tSUBi8) ? in UpdateBaseRegUses()
549 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
570 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
633 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) == in CreateLoadStoreMulti()
642 assert(Base != ARM::SP && "Thumb1 does not allow SP in register list"); in CreateLoadStoreMulti()
643 if (Opcode == ARM::tLDRi) in CreateLoadStoreMulti()
645 else if (Opcode == ARM::tSTRi) in CreateLoadStoreMulti()
661 } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) { in CreateLoadStoreMulti()
692 NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass); in CreateLoadStoreMulti()
698 isThumb2 ? ARM::t2ADDri : in CreateLoadStoreMulti()
699 (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi : in CreateLoadStoreMulti()
700 (isThumb1 && Offset < 8) ? ARM::tADDi3 : in CreateLoadStoreMulti()
701 isThumb1 ? ARM::tADDi8 : ARM::ADDri; in CreateLoadStoreMulti()
706 isThumb2 ? ARM::t2SUBri : in CreateLoadStoreMulti()
707 (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 : in CreateLoadStoreMulti()
708 isThumb1 ? ARM::tSUBi8 : ARM::SUBri; in CreateLoadStoreMulti()
727 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
734 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase) in CreateLoadStoreMulti()
737 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase) in CreateLoadStoreMulti()
745 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
791 if (Opcode == ARM::tLDMIA) { in CreateLoadStoreMulti()
794 Opcode = ARM::tLDMIA_UPD; in CreateLoadStoreMulti()
828 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8; in CreateLoadStoreDouble()
947 assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD); in MergeOpsUpdate()
981 if (getLoadStoreBaseOp(MI).getReg() == ARM::SP && in mayCombineMisaligned()
1023 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
1036 case ARM::VLDRD: in FormCandidates()
1037 case ARM::VSTRD: in FormCandidates()
1049 if (Reg == ARM::SP || Reg == ARM::PC) in FormCandidates()
1108 case ARM::LDMIA: in getUpdatingLSMultipleOpcode()
1109 case ARM::LDMDA: in getUpdatingLSMultipleOpcode()
1110 case ARM::LDMDB: in getUpdatingLSMultipleOpcode()
1111 case ARM::LDMIB: in getUpdatingLSMultipleOpcode()
1114 case ARM_AM::ia: return ARM::LDMIA_UPD; in getUpdatingLSMultipleOpcode()
1115 case ARM_AM::ib: return ARM::LDMIB_UPD; in getUpdatingLSMultipleOpcode()
1116 case ARM_AM::da: return ARM::LDMDA_UPD; in getUpdatingLSMultipleOpcode()
1117 case ARM_AM::db: return ARM::LDMDB_UPD; in getUpdatingLSMultipleOpcode()
1119 case ARM::STMIA: in getUpdatingLSMultipleOpcode()
1120 case ARM::STMDA: in getUpdatingLSMultipleOpcode()
1121 case ARM::STMDB: in getUpdatingLSMultipleOpcode()
1122 case ARM::STMIB: in getUpdatingLSMultipleOpcode()
1125 case ARM_AM::ia: return ARM::STMIA_UPD; in getUpdatingLSMultipleOpcode()
1126 case ARM_AM::ib: return ARM::STMIB_UPD; in getUpdatingLSMultipleOpcode()
1127 case ARM_AM::da: return ARM::STMDA_UPD; in getUpdatingLSMultipleOpcode()
1128 case ARM_AM::db: return ARM::STMDB_UPD; in getUpdatingLSMultipleOpcode()
1130 case ARM::t2LDMIA: in getUpdatingLSMultipleOpcode()
1131 case ARM::t2LDMDB: in getUpdatingLSMultipleOpcode()
1134 case ARM_AM::ia: return ARM::t2LDMIA_UPD; in getUpdatingLSMultipleOpcode()
1135 case ARM_AM::db: return ARM::t2LDMDB_UPD; in getUpdatingLSMultipleOpcode()
1137 case ARM::t2STMIA: in getUpdatingLSMultipleOpcode()
1138 case ARM::t2STMDB: in getUpdatingLSMultipleOpcode()
1141 case ARM_AM::ia: return ARM::t2STMIA_UPD; in getUpdatingLSMultipleOpcode()
1142 case ARM_AM::db: return ARM::t2STMDB_UPD; in getUpdatingLSMultipleOpcode()
1144 case ARM::VLDMSIA: in getUpdatingLSMultipleOpcode()
1147 case ARM_AM::ia: return ARM::VLDMSIA_UPD; in getUpdatingLSMultipleOpcode()
1148 case ARM_AM::db: return ARM::VLDMSDB_UPD; in getUpdatingLSMultipleOpcode()
1150 case ARM::VLDMDIA: in getUpdatingLSMultipleOpcode()
1153 case ARM_AM::ia: return ARM::VLDMDIA_UPD; in getUpdatingLSMultipleOpcode()
1154 case ARM_AM::db: return ARM::VLDMDDB_UPD; in getUpdatingLSMultipleOpcode()
1156 case ARM::VSTMSIA: in getUpdatingLSMultipleOpcode()
1159 case ARM_AM::ia: return ARM::VSTMSIA_UPD; in getUpdatingLSMultipleOpcode()
1160 case ARM_AM::db: return ARM::VSTMSDB_UPD; in getUpdatingLSMultipleOpcode()
1162 case ARM::VSTMDIA: in getUpdatingLSMultipleOpcode()
1165 case ARM_AM::ia: return ARM::VSTMDIA_UPD; in getUpdatingLSMultipleOpcode()
1166 case ARM_AM::db: return ARM::VSTMDDB_UPD; in getUpdatingLSMultipleOpcode()
1179 case ARM::tADDi8: Scale = 4; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1180 case ARM::tSUBi8: Scale = -4; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1181 case ARM::t2SUBri: in isIncrementOrDecrement()
1182 case ARM::SUBri: Scale = -1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1183 case ARM::t2ADDri: in isIncrementOrDecrement()
1184 case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1185 case ARM::tADDspi: Scale = 4; CheckCPSRDef = false; break; in isIncrementOrDecrement()
1186 case ARM::tSUBspi: Scale = -4; CheckCPSRDef = false; break; in isIncrementOrDecrement()
1295 if (MI->getOperand(i).getReg() >= ARM::R8) { in MergeBaseUpdateLSMultiple()
1329 case ARM::LDRi12: in getPreIndexedLoadStoreOpcode()
1330 return ARM::LDR_PRE_IMM; in getPreIndexedLoadStoreOpcode()
1331 case ARM::STRi12: in getPreIndexedLoadStoreOpcode()
1332 return ARM::STR_PRE_IMM; in getPreIndexedLoadStoreOpcode()
1333 case ARM::VLDRS: in getPreIndexedLoadStoreOpcode()
1334 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; in getPreIndexedLoadStoreOpcode()
1335 case ARM::VLDRD: in getPreIndexedLoadStoreOpcode()
1336 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; in getPreIndexedLoadStoreOpcode()
1337 case ARM::VSTRS: in getPreIndexedLoadStoreOpcode()
1338 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; in getPreIndexedLoadStoreOpcode()
1339 case ARM::VSTRD: in getPreIndexedLoadStoreOpcode()
1340 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; in getPreIndexedLoadStoreOpcode()
1341 case ARM::t2LDRi8: in getPreIndexedLoadStoreOpcode()
1342 case ARM::t2LDRi12: in getPreIndexedLoadStoreOpcode()
1343 return ARM::t2LDR_PRE; in getPreIndexedLoadStoreOpcode()
1344 case ARM::t2STRi8: in getPreIndexedLoadStoreOpcode()
1345 case ARM::t2STRi12: in getPreIndexedLoadStoreOpcode()
1346 return ARM::t2STR_PRE; in getPreIndexedLoadStoreOpcode()
1354 case ARM::LDRi12: in getPostIndexedLoadStoreOpcode()
1355 return ARM::LDR_POST_IMM; in getPostIndexedLoadStoreOpcode()
1356 case ARM::STRi12: in getPostIndexedLoadStoreOpcode()
1357 return ARM::STR_POST_IMM; in getPostIndexedLoadStoreOpcode()
1358 case ARM::VLDRS: in getPostIndexedLoadStoreOpcode()
1359 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; in getPostIndexedLoadStoreOpcode()
1360 case ARM::VLDRD: in getPostIndexedLoadStoreOpcode()
1361 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; in getPostIndexedLoadStoreOpcode()
1362 case ARM::VSTRS: in getPostIndexedLoadStoreOpcode()
1363 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; in getPostIndexedLoadStoreOpcode()
1364 case ARM::VSTRD: in getPostIndexedLoadStoreOpcode()
1365 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; in getPostIndexedLoadStoreOpcode()
1366 case ARM::t2LDRi8: in getPostIndexedLoadStoreOpcode()
1367 case ARM::t2LDRi12: in getPostIndexedLoadStoreOpcode()
1368 return ARM::t2LDR_POST; in getPostIndexedLoadStoreOpcode()
1369 case ARM::t2STRi8: in getPostIndexedLoadStoreOpcode()
1370 case ARM::t2STRi12: in getPostIndexedLoadStoreOpcode()
1371 return ARM::t2STR_POST; in getPostIndexedLoadStoreOpcode()
1387 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS || in MergeBaseUpdateLoadStore()
1388 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS); in MergeBaseUpdateLoadStore()
1389 bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12); in MergeBaseUpdateLoadStore()
1443 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1469 if (isAM2 && NewOpc == ARM::STR_POST_IMM) { in MergeBaseUpdateLoadStore()
1494 assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) && in MergeBaseUpdateLSDouble()
1517 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1521 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1529 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble()
1532 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble()
1555 case ARM::VLDRS: in isMemoryOp()
1556 case ARM::VSTRS: in isMemoryOp()
1557 case ARM::VLDRD: in isMemoryOp()
1558 case ARM::VSTRD: in isMemoryOp()
1559 case ARM::LDRi12: in isMemoryOp()
1560 case ARM::STRi12: in isMemoryOp()
1561 case ARM::tLDRi: in isMemoryOp()
1562 case ARM::tSTRi: in isMemoryOp()
1563 case ARM::tLDRspi: in isMemoryOp()
1564 case ARM::tSTRspi: in isMemoryOp()
1565 case ARM::t2LDRi8: in isMemoryOp()
1566 case ARM::t2LDRi12: in isMemoryOp()
1567 case ARM::t2STRi8: in isMemoryOp()
1568 case ARM::t2STRi12: in isMemoryOp()
1632 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1645 (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3(); in FixInvalidRegPairOp()
1647 bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) && in FixInvalidRegPairOp()
1653 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; in FixInvalidRegPairOp()
1654 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp()
1663 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) && in FixInvalidRegPairOp()
1673 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA) in FixInvalidRegPairOp()
1674 : (isT2 ? ARM::t2STMIA : ARM::STMIA); in FixInvalidRegPairOp()
1695 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1696 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1700 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1701 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1826 } else if (MBBI->getOpcode() == ARM::t2LDRDi8 || in LoadStoreMultipleOpti()
1827 MBBI->getOpcode() == ARM::t2STRDi8) { in LoadStoreMultipleOpti()
1862 if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8) in LoadStoreMultipleOpti()
1904 (MBBI->getOpcode() == ARM::BX_RET || in MergeReturnIntoLDM()
1905 MBBI->getOpcode() == ARM::tBX_RET || in MergeReturnIntoLDM()
1906 MBBI->getOpcode() == ARM::MOVPCLR)) { in MergeReturnIntoLDM()
1913 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD || in MergeReturnIntoLDM()
1914 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD || in MergeReturnIntoLDM()
1915 Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in MergeReturnIntoLDM()
1917 if (MO.getReg() != ARM::LR) in MergeReturnIntoLDM()
1919 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM()
1920 assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) || in MergeReturnIntoLDM()
1921 Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!"); in MergeReturnIntoLDM()
1923 MO.setReg(ARM::PC); in MergeReturnIntoLDM()
1932 if (Info.getReg() == ARM::LR) { in MergeReturnIntoLDM()
1946 MBBI->getOpcode() != ARM::tBX_RET) in CombineMovBx()
1951 if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR)) in CombineMovBx()
1957 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX)) in CombineMovBx()
2123 if (Opcode == ARM::LDRi12) { in CanFormLdStDWord()
2124 NewOpc = ARM::LDRD; in CanFormLdStDWord()
2125 } else if (Opcode == ARM::STRi12) { in CanFormLdStDWord()
2126 NewOpc = ARM::STRD; in CanFormLdStDWord()
2127 } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) { in CanFormLdStDWord()
2128 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord()
2131 } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) { in CanFormLdStDWord()
2132 NewOpc = ARM::t2STRDi8; in CanFormLdStDWord()