Lines Matching refs:ARM
174 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
198 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
201 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
293 if (!ARM::DPRRegClass.contains(*SR)) in PrintAsmOperand()
295 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
320 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
322 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
324 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
384 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
392 ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
414 if (!ARM::QPRRegClass.contains(Reg)) in PrintAsmOperand()
418 ARM::dsub_0 : ARM::dsub_1); in PrintAsmOperand()
433 if(!ARM::GPRPairRegClass.contains(Reg)) in PrintAsmOperand()
435 Reg = TRI->getSubReg(Reg, ARM::gsub_1); in PrintAsmOperand()
472 return STI.getFeatureBits()[ARM::ModeThumb]; in isThumb()
1007 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B) in EmitJumpTableInsts()
1083 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) { in EmitUnwindingInstruction()
1089 SrcReg = DstReg = ARM::SP; in EmitUnwindingInstruction()
1098 assert(DstReg == ARM::SP && in EmitUnwindingInstruction()
1113 case ARM::tPUSH: in EmitUnwindingInstruction()
1117 case ARM::STMDB_UPD: in EmitUnwindingInstruction()
1118 case ARM::t2STMDB_UPD: in EmitUnwindingInstruction()
1119 case ARM::VSTMDDB_UPD: in EmitUnwindingInstruction()
1120 assert(SrcReg == ARM::SP && in EmitUnwindingInstruction()
1144 case ARM::STR_PRE_IMM: in EmitUnwindingInstruction()
1145 case ARM::STR_PRE_REG: in EmitUnwindingInstruction()
1146 case ARM::t2STR_PRE: in EmitUnwindingInstruction()
1147 assert(MI->getOperand(2).getReg() == ARM::SP && in EmitUnwindingInstruction()
1152 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1153 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
1160 if (SrcReg == ARM::SP) { in EmitUnwindingInstruction()
1166 case ARM::MOVr: in EmitUnwindingInstruction()
1167 case ARM::tMOVr: in EmitUnwindingInstruction()
1170 case ARM::ADDri: in EmitUnwindingInstruction()
1171 case ARM::t2ADDri: in EmitUnwindingInstruction()
1174 case ARM::SUBri: in EmitUnwindingInstruction()
1175 case ARM::t2SUBri: in EmitUnwindingInstruction()
1178 case ARM::tSUBspi: in EmitUnwindingInstruction()
1181 case ARM::tADDspi: in EmitUnwindingInstruction()
1182 case ARM::tADDrSPi: in EmitUnwindingInstruction()
1185 case ARM::tLDRpci: { in EmitUnwindingInstruction()
1203 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1204 if (DstReg == FramePtr && FramePtr != ARM::SP) in EmitUnwindingInstruction()
1207 ATS.emitSetFP(FramePtr, ARM::SP, -Offset); in EmitUnwindingInstruction()
1208 else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1218 } else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1240 unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11; in EmitInstruction()
1243 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) { in EmitInstruction()
1263 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass"); in EmitInstruction()
1264 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing"); in EmitInstruction()
1265 case ARM::LEApcrel: in EmitInstruction()
1266 case ARM::tLEApcrel: in EmitInstruction()
1267 case ARM::t2LEApcrel: { in EmitInstruction()
1271 ARM::t2LEApcrel ? ARM::t2ADR in EmitInstruction()
1272 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR in EmitInstruction()
1273 : ARM::ADR)) in EmitInstruction()
1281 case ARM::LEApcrelJT: in EmitInstruction()
1282 case ARM::tLEApcrelJT: in EmitInstruction()
1283 case ARM::t2LEApcrelJT: { in EmitInstruction()
1287 ARM::t2LEApcrelJT ? ARM::t2ADR in EmitInstruction()
1288 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR in EmitInstruction()
1289 : ARM::ADR)) in EmitInstruction()
1299 case ARM::BX_CALL: { in EmitInstruction()
1300 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in EmitInstruction()
1301 .addReg(ARM::LR) in EmitInstruction()
1302 .addReg(ARM::PC) in EmitInstruction()
1310 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in EmitInstruction()
1314 case ARM::tBX_CALL: { in EmitInstruction()
1339 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL) in EmitInstruction()
1345 case ARM::BMOVPCRX_CALL: { in EmitInstruction()
1346 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in EmitInstruction()
1347 .addReg(ARM::LR) in EmitInstruction()
1348 .addReg(ARM::PC) in EmitInstruction()
1355 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in EmitInstruction()
1356 .addReg(ARM::PC) in EmitInstruction()
1365 case ARM::BMOVPCB_CALL: { in EmitInstruction()
1366 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in EmitInstruction()
1367 .addReg(ARM::LR) in EmitInstruction()
1368 .addReg(ARM::PC) in EmitInstruction()
1380 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc) in EmitInstruction()
1387 case ARM::MOVi16_ga_pcrel: in EmitInstruction()
1388 case ARM::t2MOVi16_ga_pcrel: { in EmitInstruction()
1390 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in EmitInstruction()
1402 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4; in EmitInstruction()
1418 case ARM::MOVTi16_ga_pcrel: in EmitInstruction()
1419 case ARM::t2MOVTi16_ga_pcrel: { in EmitInstruction()
1421 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in EmitInstruction()
1422 ? ARM::MOVTi16 : ARM::t2MOVTi16); in EmitInstruction()
1435 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4; in EmitInstruction()
1450 case ARM::tPICADD: { in EmitInstruction()
1462 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in EmitInstruction()
1465 .addReg(ARM::PC) in EmitInstruction()
1471 case ARM::PICADD: { in EmitInstruction()
1483 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in EmitInstruction()
1485 .addReg(ARM::PC) in EmitInstruction()
1494 case ARM::PICSTR: in EmitInstruction()
1495 case ARM::PICSTRB: in EmitInstruction()
1496 case ARM::PICSTRH: in EmitInstruction()
1497 case ARM::PICLDR: in EmitInstruction()
1498 case ARM::PICLDRB: in EmitInstruction()
1499 case ARM::PICLDRH: in EmitInstruction()
1500 case ARM::PICLDRSB: in EmitInstruction()
1501 case ARM::PICLDRSH: { in EmitInstruction()
1518 case ARM::PICSTR: Opcode = ARM::STRrs; break; in EmitInstruction()
1519 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; in EmitInstruction()
1520 case ARM::PICSTRH: Opcode = ARM::STRH; break; in EmitInstruction()
1521 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in EmitInstruction()
1522 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; in EmitInstruction()
1523 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in EmitInstruction()
1524 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in EmitInstruction()
1525 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in EmitInstruction()
1529 .addReg(ARM::PC) in EmitInstruction()
1538 case ARM::CONSTPOOL_ENTRY: { in EmitInstruction()
1565 case ARM::JUMPTABLE_ADDRS: in EmitInstruction()
1568 case ARM::JUMPTABLE_INSTS: in EmitInstruction()
1571 case ARM::JUMPTABLE_TBB: in EmitInstruction()
1572 case ARM::JUMPTABLE_TBH: in EmitInstruction()
1573 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); in EmitInstruction()
1575 case ARM::t2BR_JT: { in EmitInstruction()
1576 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in EmitInstruction()
1577 .addReg(ARM::PC) in EmitInstruction()
1584 case ARM::t2TBB_JT: in EmitInstruction()
1585 case ARM::t2TBH_JT: { in EmitInstruction()
1586 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in EmitInstruction()
1597 case ARM::tTBB_JT: in EmitInstruction()
1598 case ARM::tTBH_JT: { in EmitInstruction()
1600 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT; in EmitInstruction()
1607 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in EmitInstruction()
1609 .addReg(ARM::CPSR) in EmitInstruction()
1616 if (Base == ARM::PC) { in EmitInstruction()
1631 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in EmitInstruction()
1639 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi; in EmitInstruction()
1653 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr; in EmitInstruction()
1663 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in EmitInstruction()
1665 .addReg(ARM::CPSR) in EmitInstruction()
1673 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in EmitInstruction()
1674 .addReg(ARM::PC) in EmitInstruction()
1675 .addReg(ARM::PC) in EmitInstruction()
1682 case ARM::tBR_JTr: in EmitInstruction()
1683 case ARM::BR_JTr: { in EmitInstruction()
1686 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? in EmitInstruction()
1687 ARM::MOVr : ARM::tMOVr; in EmitInstruction()
1689 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in EmitInstruction()
1695 if (Opc == ARM::MOVr) in EmitInstruction()
1700 case ARM::BR_JTm_i12: { in EmitInstruction()
1703 TmpInst.setOpcode(ARM::LDRi12); in EmitInstruction()
1704 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in EmitInstruction()
1713 case ARM::BR_JTm_rs: { in EmitInstruction()
1716 TmpInst.setOpcode(ARM::LDRrs); in EmitInstruction()
1717 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in EmitInstruction()
1727 case ARM::BR_JTadd: { in EmitInstruction()
1729 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in EmitInstruction()
1730 .addReg(ARM::PC) in EmitInstruction()
1740 case ARM::SPACE: in EmitInstruction()
1743 case ARM::TRAP: { in EmitInstruction()
1754 case ARM::TRAPNaCl: { in EmitInstruction()
1760 case ARM::tTRAP: { in EmitInstruction()
1771 case ARM::t2Int_eh_sjlj_setjmp: in EmitInstruction()
1772 case ARM::t2Int_eh_sjlj_setjmp_nofp: in EmitInstruction()
1773 case ARM::tInt_eh_sjlj_setjmp: { in EmitInstruction()
1786 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in EmitInstruction()
1788 .addReg(ARM::PC) in EmitInstruction()
1793 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3) in EmitInstruction()
1796 .addReg(ARM::CPSR) in EmitInstruction()
1803 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi) in EmitInstruction()
1813 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in EmitInstruction()
1814 .addReg(ARM::R0) in EmitInstruction()
1815 .addReg(ARM::CPSR) in EmitInstruction()
1822 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB) in EmitInstruction()
1828 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in EmitInstruction()
1829 .addReg(ARM::R0) in EmitInstruction()
1830 .addReg(ARM::CPSR) in EmitInstruction()
1840 case ARM::Int_eh_sjlj_setjmp_nofp: in EmitInstruction()
1841 case ARM::Int_eh_sjlj_setjmp: { in EmitInstruction()
1852 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in EmitInstruction()
1854 .addReg(ARM::PC) in EmitInstruction()
1862 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12) in EmitInstruction()
1870 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in EmitInstruction()
1871 .addReg(ARM::R0) in EmitInstruction()
1879 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in EmitInstruction()
1880 .addReg(ARM::PC) in EmitInstruction()
1881 .addReg(ARM::PC) in EmitInstruction()
1890 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in EmitInstruction()
1891 .addReg(ARM::R0) in EmitInstruction()
1900 case ARM::Int_eh_sjlj_longjmp: { in EmitInstruction()
1907 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in EmitInstruction()
1908 .addReg(ARM::SP) in EmitInstruction()
1915 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in EmitInstruction()
1925 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in EmitInstruction()
1935 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in EmitInstruction()
1936 .addReg(ARM::R7) in EmitInstruction()
1942 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in EmitInstruction()
1943 .addReg(ARM::R11) in EmitInstruction()
1952 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in EmitInstruction()
1959 case ARM::tInt_eh_sjlj_longjmp: { in EmitInstruction()
1968 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in EmitInstruction()
1978 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in EmitInstruction()
1979 .addReg(ARM::SP) in EmitInstruction()
1985 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in EmitInstruction()
1995 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in EmitInstruction()
2005 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in EmitInstruction()
2006 .addReg(ARM::R7) in EmitInstruction()
2012 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in EmitInstruction()
2013 .addReg(ARM::R11) in EmitInstruction()
2021 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in EmitInstruction()
2028 case ARM::tInt_WIN_eh_sjlj_longjmp: { in EmitInstruction()
2035 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in EmitInstruction()
2036 .addReg(ARM::R11) in EmitInstruction()
2042 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in EmitInstruction()
2043 .addReg(ARM::SP) in EmitInstruction()
2049 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in EmitInstruction()
2050 .addReg(ARM::PC) in EmitInstruction()
2058 case ARM::PATCHABLE_FUNCTION_ENTER: in EmitInstruction()
2061 case ARM::PATCHABLE_FUNCTION_EXIT: in EmitInstruction()
2064 case ARM::PATCHABLE_TAIL_CALL: in EmitInstruction()