164   assert((RegBank->getID() == ARM::GPRRegBankID ||  in guessRegClass()
165           RegBank->getID() == ARM::FPRRegBankID) &&  in guessRegClass()
168   if (RegBank->getID() == ARM::FPRRegBankID) {  in guessRegClass()
170       return &ARM::SPRRegClass;  in guessRegClass()
172       return &ARM::DPRRegClass;  in guessRegClass()
174       return &ARM::QPRRegClass;  in guessRegClass()
179   return &ARM::GPRRegClass;  in guessRegClass()
214          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&  in selectMergeValues()
219          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&  in selectMergeValues()
224          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&  in selectMergeValues()
227   MIB->setDesc(TII.get(ARM::VMOVDRR));  in selectMergeValues()
245          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&  in selectUnmergeValues()
250          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&  in selectUnmergeValues()
255          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&  in selectUnmergeValues()
258   MIB->setDesc(TII.get(ARM::VMOVRRD));  in selectUnmergeValues()
269 #define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC  in OpcodeCache()
283   STORE16 = isThumb ? ARM::t2STRHi12 : ARM::STRH;  in OpcodeCache()
284   LOAD16 = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;  in OpcodeCache()
312   if (RegBank == ARM::GPRRegBankID) {  in selectLoadStoreOpCode()
326   if (RegBank == ARM::FPRRegBankID) {  in selectLoadStoreOpCode()
329       return isStore ? ARM::VSTRS : ARM::VLDRS;  in selectLoadStoreOpCode()
331       return isStore ? ARM::VSTRD : ARM::VLDRD;  in selectLoadStoreOpCode()
442   (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVi))  in putConstant()
480   if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))  in selectCmp()
498   auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);  in selectCmp()
508     auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);  in selectCmp()
536   if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {  in insertComparison()
545   auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVCCi))  in insertComparison()
549                    .add(predOps(Cond, ARM::CPSR));  in insertComparison()
580     assert(MIB->getOpcode() == ARM::LDRi12 && "Unsupported instruction");  in selectGlobal()
603             ? (Indirect ? ARM::MOV_ga_pcrel_ldr : ARM::MOV_ga_pcrel)  in selectGlobal()
604             : (Indirect ? ARM::LDRLIT_ga_pcrel_ldr : ARM::LDRLIT_ga_pcrel);  in selectGlobal()
624     unsigned Opc = UseMovt ? ARM::MOV_ga_pcrel : ARM::LDRLIT_ga_pcrel;  in selectGlobal()
629     auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);  in selectGlobal()
633                           TII.get(ARM::MOVi32imm), Offset);  in selectGlobal()
638           BuildMI(MBB, *MIB, MIB->getDebugLoc(), TII.get(ARM::LDRi12), Offset);  in selectGlobal()
645     MIB->setDesc(TII.get(ARM::ADDrr));  in selectGlobal()
647     MIB.addReg(ARM::R9) // FIXME: don't hardcode R9  in selectGlobal()
657       MIB->setDesc(TII.get(ARM::MOVi32imm));  in selectGlobal()
660       MIB->setDesc(TII.get(ARM::LDRi12));  in selectGlobal()
666       MIB->setDesc(TII.get(ARM::MOVi32imm));  in selectGlobal()
668       MIB->setDesc(TII.get(ARM::LDRLIT_ga_abs));  in selectGlobal()
685   assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&  in selectSelect()
687   auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::CMPri))  in selectSelect()
699   assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&  in selectSelect()
700          validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&  in selectSelect()
702   auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVCCr))  in selectSelect()
706                    .add(predOps(ARMCC::EQ, ARM::CPSR));  in selectSelect()
716   MIB->setDesc(TII.get(ARM::MOVsr));  in selectShift()
770         unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);  in select()
811     if (SrcRegBank.getID() == ARM::FPRRegBankID) {  in select()
816       assert(DstRegBank.getID() == ARM::GPRRegBankID &&  in select()
821       unsigned IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);  in select()
824           BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD))  in select()
842     if (SrcRegBank.getID() != ARM::GPRRegBankID) {  in select()
872     I.setDesc(TII.get(ARM::MOVi));  in select()
891     if (SrcRegBank.getID() != ARM::GPRRegBankID) {  in select()
903     CmpConstants Helper(ARM::CMPrr, ARM::INSTRUCTION_LIST_END,  in select()
904                         ARM::GPRRegBankID, 32);  in select()
922     CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,  in select()
923                         ARM::FPRRegBankID, Size);  in select()
934     I.setDesc(TII.get(ARM::ADDrr));  in select()
940     I.setDesc(TII.get(ARM::ADDri));  in select()
968     if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)  in select()
985     if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {  in select()
991     auto Test = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::TSTri))  in select()
999     auto Branch = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::Bcc))  in select()
1001                       .add(predOps(ARMCC::NE, ARM::CPSR));  in select()