Home
last modified time | relevance | path

Searched refs:TII (Results 1 – 25 of 490) sorted by relevance

12345678910>>...20

/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp106 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16, in ExpandMI()
109 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i32, in ExpandMI()
126 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i16, in ExpandMI()
129 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i32, in ExpandMI()
171 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false); in ExpandMI()
185 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in ExpandMI()
187 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in ExpandMI()
189 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in ExpandMI()
192 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true); in ExpandMI()
194 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true); in ExpandMI()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
120 Def->setDesc(TII.get(NE_I64)); in runOnMachineFunction()
124 Def->setDesc(TII.get(EQ_I64)); in runOnMachineFunction()
160 Def->setDesc(TII.get(NE_F32)); in runOnMachineFunction()
164 Def->setDesc(TII.get(EQ_F32)); in runOnMachineFunction()
168 Def->setDesc(TII.get(NE_F64)); in runOnMachineFunction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp31 const R600InstrInfo *TII = nullptr; member in __anonf909da6f0111::R600ExpandSpecialInstrsPass
65 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
68 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
74 TII = ST.getInstrInfo(); in runOnMachineFunction()
85 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
113 TII->addFlag(*PredSet, 0, MO_FLAG_MASK); in runOnMachineFunction()
139 TII->addFlag(*BMI, 0, MO_FLAG_MASK); in runOnMachineFunction()
142 TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST); in runOnMachineFunction()
164 bool IsVector = TII->isVector(MI); in runOnMachineFunction()
165 bool IsCube = TII->isCubeOp(MI.getOpcode()); in runOnMachineFunction()
[all …]
H A DSIPeepholeSDWA.cpp49 const SIInstrInfo *TII; member in __anona3dad2400111::SIPeepholeSDWA
505 if (!TII->isFoldableCopy(*DefInst)) in foldToImm()
705 if (!TII->isSDWA(*Op1Inst)) in matchSDWAOperand()
755 if (!TII->isSDWA(*OtherInst)) in matchSDWAOperand()
860 if (!TII->canShrink(MI, *MRI)) in pseudoOpConvertToVOP2()
872 if (!TII->canShrink(MISucc, *MRI)) in pseudoOpConvertToVOP2()
920 if (TII->isSDWA(Opc)) in isConvertibleToSDWA()
933 if (TII->isVOPC(Opc)) { in isConvertibleToSDWA()
958 if (TII->pseudoToMCOpcode(Opc) == -1) in isConvertibleToSDWA()
986 if (TII->isSDWA(Opcode)) { in convertToSDWA()
[all …]
H A DGCNDPPCombine.cpp56 const SIInstrInfo *TII; member in __anon5b1b117c0111::GCNDPPCombine
119 if (!TII->isVOP3(Op)) { in isShrinkable()
122 if (!TII->hasVALU32BitEncoding(Op)) { in isShrinkable()
215 !(TII->isVOPC(DPPOp) || in createDPPInst()
216 (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && TII->isVOPC(OrigOpE32))) && in createDPPInst()
250 } else if (TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && in createDPPInst()
634 ((TII->isVOP3P(OrigOp) || TII->isVOPC(OrigOp) || in combineDPPMov()
635 TII->isVOP3(OrigOp)) && in combineDPPMov()
637 TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) { in combineDPPMov()
678 if (TII->commuteInstruction(*NewMI)) { in combineDPPMov()
[all …]
H A DR600Packetizer.cpp52 const R600InstrInfo *TII; member in __anon53b130fd0111::R600PacketizerList
79 if (TII->isPredicated(*BI)) in getPreviousVector()
145 TII(ST.getInstrInfo()), in R600PacketizerList()
146 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
164 if (TII->isVector(MI)) in isSoloInstruction()
166 if (!TII->isALUInstr(MI.getOpcode())) in isSoloInstruction()
172 return TII->isLDSInstr(MI.getOpcode()); in isSoloInstruction()
203 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
205 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
225 isTransSlot = TII->isTransOnly(MI); in isBundlableWithCurrentPMI()
[all …]
H A DAMDGPUIGroupLP.cpp146 B, E, [this, TII](MachineInstr &MI) { return canAddMI(MI, TII); }); in canAddSU()
157 return TII->isMFMA(MI); in isMFMASGMember()
161 return TII->isVALU(MI) && !TII->isMFMA(MI); in isVALUSGMember()
165 return TII->isSALU(MI); in isSALUSGMember()
169 return TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI)); in isVMEMSGMember()
174 (TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI))); in isVMEMReadSGMember()
179 (TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI))); in isVMEMWriteSGMember()
192 const SIInstrInfo *TII; member in __anona5db2d930111::IGroupLPDAGMutation
205 const SIInstrInfo *TII; member in __anona5db2d930111::SchedBarrierDAGMutation
259 TII = ST.getInstrInfo(); in apply()
[all …]
H A DSIFoldOperands.cpp82 const SIInstrInfo *TII; member in __anonab0293a00111::SIFoldOperands
158 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
161 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
342 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
348 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
434 if (TII->isSALU(MI->getOpcode())) { in tryAddToFoldList()
639 if (TII->isMUBUF(*UseMI)) { in foldOperand()
718 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
1344 if (TII->getClampMask(*Def) != TII->getClampMask(MI)) in tryFoldClamp()
1703 TII = ST->getInstrInfo(); in runOnMachineFunction()
[all …]
H A DSIModeRegister.cpp147 const SIInstrInfo *TII, Status InstrMode);
166 if (TII->usesFPDPRounding(MI) || in getInstructionMode()
178 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
184 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
248 Status InstrMode = getInstructionMode(MI, TII); in processBlockPhase1()
304 insertSetreg(MBB, InsertionPoint, TII, in processBlockPhase1()
411 insertSetreg(MBB, &MBB.instr_front(), TII, Delta); in processBlockPhase3()
418 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
425 processBlockPhase1(BB, TII); in runOnMachineFunction()
433 processBlockPhase2(*Phase2List.front(), TII); in runOnMachineFunction()
[all …]
H A DR600EmitClauseMarkers.cpp34 const R600InstrInfo *TII = nullptr; member in __anon222f234c0111::R600EmitClauseMarkers
52 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
55 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
56 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
71 if (TII->isALUInstr(MI.getOpcode())) in isALU()
73 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
123 TII->getSrcs(MI); in SubstituteKCacheBank()
204 if (AluInstCount >= TII->getMaxAlusPerClause()) in canClauseLocalKillFitInClause()
238 if (AluInstCount > TII->getMaxAlusPerClause()) in MakeALUClause()
261 if (TII->mustBeLastInClause(I->getOpcode())) { in MakeALUClause()
[all …]
H A DR600ClauseMergePass.cpp39 const R600InstrInfo *TII; member in __anon8ac98d6f0111::R600ClauseMergePass
115 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
139 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
141 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
170 RootCFAlu.setDesc(TII->get(LatrCFAlu.getOpcode())); in mergeIfPossible()
179 TII = ST.getInstrInfo(); in runOnMachineFunction()
186 if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) || in runOnMachineFunction()
[all …]
H A DSILoadStoreOptimizer.cpp313 if (TII.isMUBUF(Opc)) { in getOpcodeWidth()
317 if (TII.isMIMG(MI)) { in getOpcodeWidth()
322 if (TII.isMTBUF(Opc)) { in getOpcodeWidth()
395 if (TII.isMIMG(Opc)) { in getInstClass()
404 if (TII.get(Opc).mayStore() || !TII.get(Opc).mayLoad() || in getInstClass()
478 if (TII.isMUBUF(Opc)) in getInstSubclass()
480 if (TII.isMIMG(Opc)) { in getInstSubclass()
485 if (TII.isMTBUF(Opc)) in getInstSubclass()
554 if (TII.isMUBUF(Opc)) { in getRegs()
565 if (TII.isMIMG(Opc)) { in getRegs()
[all …]
H A DSIShrinkInstructions.cpp31 const SIInstrInfo *TII; member in __anonb5245ce30111::SIShrinkInstructions
89 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
135 TII->commuteInstruction(MI); in foldImmediates()
332 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
352 if (TII->hasAnyModifiersSet(MI)) in shrinkMadFma()
430 TII->removeModOperands(MI); in shrinkMadFma()
490 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
733 TII = ST->getInstrInfo(); in runOnMachineFunction()
734 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
849 if (!TII->isVOP3(MI)) in runOnMachineFunction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp61 const MipsInstrInfo &TII; member in __anon1fe89efa0111::MipsInstructionSelector
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
350 I.setDesc(TII.get(COPY)); in select()
391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
435 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
605 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
620 if (!PairF64.constrainAllUses(TII, TRI, RBI)) in select()
814 if (!MIB.constrainAllUses(TII, TRI, RBI)) in select()
[all …]
H A DMipsBranchExpansion.cpp172 const MipsInstrInfo *TII; member in __anon32acd99a0111::MipsBranchExpansion
304 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); in initMBBInfo()
343 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
357 if (!TII->isBranchWithImm(Br->getOpcode())) in replaceBranch()
473 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
537 TII->insertNop(*BalTgtMBB, Pos, DL); in expandToLongBranch()
596 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)) in expandToLongBranch()
737 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
789 return TII->SafeInForbiddenSlot(IInSlot); in handleForbiddenSlot()
812 return TII->SafeInLoadDelaySlot(IInSlot, I); in handleLoadDelaySlot()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp33 const RISCVInstrInfo *TII; member in __anond5297ed10111::RISCVExpandAtomicPseudo
250 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
335 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doMaskedAtomicBinOpExpansion()
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
453 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
461 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
494 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)) in expandAtomicMinMaxOp()
549 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)) in expandAtomicCmpXchg()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp57 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
140 const AVRInstrInfo &TII = *STI.getInstrInfo(); in restoreStatusRegister() local
146 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr)) in restoreStatusRegister()
263 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr)) in spillCalleeSavedRegisters()
323 MI.setDesc(TII.get(STOpc)); in fixStackStores()
340 int Amount = TII.getFrameSize(*MI); in eliminateCallFramePseudoInstr()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = in emitPrologue() local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) in emitPrologue()
109 const MSP430InstrInfo &TII = in emitEpilogue() local
160 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
196 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
215 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), I.getReg()); in restoreCalleeSavedRegisters()
223 const MSP430InstrInfo &TII = in eliminateCallFramePseudoInstr() local
231 uint64_t Amount = TII.getFrameSize(Old); in eliminateCallFramePseudoInstr()
239 if (Old.getOpcode() == TII.getCallFrameSetupOpcode()) { in eliminateCallFramePseudoInstr()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
269 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in emitPrologue()
271 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0); in emitPrologue()
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode)) in emitPrologue()
309 EmitDefCfaRegister(MBB, MBBI, dl, TII, MF, in emitPrologue()
321 EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset); in emitPrologue()
333 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
336 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
[all …]
H A DXCoreRegisterInfo.cpp62 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
189 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertSPConstInst()
263 const XCoreInstrInfo &TII = in eliminateFrameIndex() local
309 InsertSPImmInst(II, TII, Reg, Offset); in eliminateFrameIndex()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp142 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologueInsns() local
152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
190 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitEpilogueInsns() local
232 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitSPAdjustment() local
277 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitSPExtend() local
313 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anona0e575c80111::ARMInstructionSelector
256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
677 MIB->setDesc(TII.get(Opc)); in selectGlobal()
715 MIB->setDesc(TII.get(Opc)); in selectGlobal()
807 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
902 I.setDesc(TII.get(NewOpc)); in select()
958 I.setDesc(TII.get(COPY)); in select()
984 I.setDesc(TII.get(ARM::MOVi)); in select()
1030 I.setDesc(TII.get(COPY)); in select()
1099 I.setDesc(TII.get(NewOpc)); in select()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DXRayInstrumentation.cpp70 const TargetInstrInfo *TII,
82 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII, in replaceRetWithPatchableRet() argument
103 if (TII->isTailCall(T) && op.HandleTailcall) { in replaceRetWithPatchableRet()
125 MachineFunction &MF, const TargetInstrInfo *TII, in prependRetWithPatchableExit() argument
134 if (TII->isTailCall(T) && op.HandleTailcall) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
207 auto *TII = MF.getSubtarget().getInstrInfo(); in runOnMachineFunction() local
238 prependRetWithPatchableExit(MF, TII, op); in runOnMachineFunction()
246 replaceRetWithPatchableRet(MF, TII, op); in runOnMachineFunction()
[all …]
H A DMachineCopyPropagation.cpp95 return TII.isCopyInstr(MI); in isCopyInstr()
141 isCopyInstr(*MI, TII, UseCopyInstr); in invalidateRegister()
170 isCopyInstr(*MI, TII, UseCopyInstr); in clobberRegister()
240 isCopyInstr(*AvailCopy, TII, UseCopyInstr); in findAvailBackwardCopy()
270 isCopyInstr(*AvailCopy, TII, UseCopyInstr); in findAvailCopy()
295 const TargetInstrInfo *TII; member in __anone7b60f380111::MachineCopyPropagation
591 isCopyInstr(*Copy, *TII, UseCopyInstr); in forwardUses()
617 if (isCopyInstr(MI, *TII, UseCopyInstr) && in forwardUses()
891 isCopyInstr(*Copy, *TII, UseCopyInstr); in propagateDefs()
991 isCopyInstr(*Copy, *TII, UseCopyInstr); in BackwardCopyPropagateBlock()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp42 const SPIRVInstrInfo &TII; member in __anonead1b6700111::SPIRVInstructionSelector
405 .constrainAllUses(TII, TRI, RBI); in selectUnOpWithSrc()
532 .constrainAllUses(TII, TRI, RBI); in selectAtomicRMW()
546 .constrainAllUses(TII, TRI, RBI); in selectFence()
789 .constrainAllUses(TII, TRI, RBI); in selectBitreverse()
835 .constrainAllUses(TII, TRI, RBI); in selectCmp()
942 .constrainAllUses(TII, TRI, RBI); in selectSelect()
991 .constrainAllUses(TII, TRI, RBI); in selectIntToBool()
997 .constrainAllUses(TII, TRI, RBI); in selectIntToBool()
1050 .constrainAllUses(TII, TRI, RBI); in selectOpUndef()
[all …]

12345678910>>...20