Lines Matching refs:TII
82 const SIInstrInfo *TII; member in __anonab0293a00111::SIFoldOperands
151 static bool frameIndexMayFold(const SIInstrInfo *TII, in frameIndexMayFold() argument
158 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
161 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
179 const SIInstrInfo &TII, in updateOperand() argument
211 switch (TII.get(Opcode).OpInfo[OpNo].OperandType) { in updateOperand()
255 MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32); in updateOperand()
258 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg()) in updateOperand()
271 MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
274 TII.commuteInstruction(*Inst32, false); in updateOperand()
285 MI->setDesc(TII.get(NewMFMAOpc)); in updateOperand()
334 const SIInstrInfo *TII) { in tryAddToFoldList() argument
335 if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) { in tryAddToFoldList()
342 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
343 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII); in tryAddToFoldList()
348 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
359 MI->setDesc(TII->get(ImmOpc)); in tryAddToFoldList()
377 bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
396 !TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1)) in tryAddToFoldList()
399 if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) { in tryAddToFoldList()
411 !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg())) in tryAddToFoldList()
424 TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
434 if (TII->isSALU(MI->getOpcode())) { in tryAddToFoldList()
437 const SIRegisterInfo &SRI = TII->getRegisterInfo(); in tryAddToFoldList()
440 if (TII->isLiteralConstantLike(*OpToFold, OpInfo)) { in tryAddToFoldList()
442 !TII->isInlineConstant(*OpToFold, OpInfo)) { in tryAddToFoldList()
447 TII->isLiteralConstantLike(Op, OpInfo)) { in tryAddToFoldList()
461 static bool isUseSafeToFold(const SIInstrInfo *TII, in isUseSafeToFold() argument
464 if (UseMO.isUndef() || TII->isSDWA(MI)) in isUseSafeToFold()
487 const SIInstrInfo *TII, const MachineRegisterInfo &MRI) { in getRegSeqInit() argument
498 !Sub->getSubReg() && TII->isFoldableCopy(*SubDef); in getRegSeqInit()
502 if (TII->isInlineConstant(*Op, OpTy)) in getRegSeqInit()
517 static bool tryToFoldACImm(const SIInstrInfo *TII, in tryToFoldACImm() argument
534 if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) && in tryToFoldACImm()
535 TII->isOperandLegal(*UseMI, UseOpIdx, &OpToFold)) { in tryToFoldACImm()
555 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
557 if (DefOp.isImm() && TII->isInlineConstant(DefOp, OpTy) && in tryToFoldACImm()
558 TII->isOperandLegal(*UseMI, UseOpIdx, &DefOp)) { in tryToFoldACImm()
565 if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI)) in tryToFoldACImm()
577 if (!TII->isInlineConstant(*Op, OpTy) || in tryToFoldACImm()
578 !TII->isOperandLegal(*UseMI, UseOpIdx, Op)) in tryToFoldACImm()
599 if (!isUseSafeToFold(TII, *UseMI, UseOp)) in foldOperand()
618 if (tryToFoldACImm(TII, UseMI->getOperand(0), RSUseMI, in foldOperand()
632 if (tryToFoldACImm(TII, OpToFold, UseMI, UseOpIdx, FoldList)) in foldOperand()
635 if (frameIndexMayFold(TII, *UseMI, UseOpIdx, OpToFold)) { in foldOperand()
639 if (TII->isMUBUF(*UseMI)) { in foldOperand()
640 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() != in foldOperand()
647 *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset); in foldOperand()
656 if (TII->isFLATScratch(*UseMI) && in foldOperand()
662 UseMI->setDesc(TII->get(NewOpc)); in foldOperand()
703 TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
704 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
714 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
718 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
732 unsigned Size = TII->getOpSize(*UseMI, 1); in foldOperand()
746 getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32, TII, in foldOperand()
751 UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE)); in foldOperand()
762 TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
767 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), Tmp).addImm(Imm); in foldOperand()
793 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def); in foldOperand()
804 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def); in foldOperand()
809 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), Tmp).addReg(Vgpr); in foldOperand()
823 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
826 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64)); in foldOperand()
830 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_MOV_B32)); in foldOperand()
850 UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32)); in foldOperand()
871 UseMI->setDesc(TII->get(AMDGPU::COPY)); in foldOperand()
907 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII); in foldOperand()
937 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII); in foldOperand()
943 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII); in foldOperand()
1055 static bool tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII, in tryConstantFoldOp() argument
1068 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32))); in tryConstantFoldOp()
1088 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in tryConstantFoldOp()
1095 mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR))); in tryConstantFoldOp()
1114 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
1118 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32))); in tryConstantFoldOp()
1131 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32))); in tryConstantFoldOp()
1135 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
1149 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
1164 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryFoldCndMask()
1165 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask()
1183 TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false)); in tryFoldCndMask()
1239 if (tryConstantFoldOp(*MRI, TII, &UseMI)) { in foldInstOperand()
1272 if (updateOperand(Fold, *TII, *TRI, *ST)) { in foldInstOperand()
1286 TII->commuteInstruction(*Fold.UseMI, false); in foldInstOperand()
1301 if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) in isClamp()
1305 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp()
1306 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
1314 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isClamp()
1318 = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm(); in isClamp()
1320 = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm(); in isClamp()
1344 if (TII->getClampMask(*Def) != TII->getClampMask(MI)) in tryFoldClamp()
1347 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp); in tryFoldClamp()
1361 if (TII->convertToThreeAddress(*Def, nullptr, nullptr)) in tryFoldClamp()
1428 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod()
1429 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1441 TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) || in isOMod()
1442 TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) || in isOMod()
1443 TII->hasModifiersSet(MI, AMDGPU::OpName::omod) || in isOMod()
1444 TII->hasModifiersSet(MI, AMDGPU::OpName::clamp)) in isOMod()
1459 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod()
1460 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1464 !TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) && in isOMod()
1465 !TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) && in isOMod()
1466 !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) && in isOMod()
1467 !TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isOMod()
1488 MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod); in tryFoldOMod()
1494 if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp)) in tryFoldOMod()
1506 if (TII->convertToThreeAddress(*Def, nullptr, nullptr)) in tryFoldOMod()
1523 if (!getRegSeqInit(Defs, Reg, MCOI::OPERAND_REGISTER, TII, *MRI)) in tryFoldRegSequence()
1556 TII->getRegClass(InstDesc, OpIdx, TRI, *MI.getMF()); in tryFoldRegSequence()
1563 TII->get(AMDGPU::REG_SEQUENCE), Dst); in tryFoldRegSequence()
1579 if (!TII->isOperandLegal(*UseMI, OpIdx, Op)) { in tryFoldRegSequence()
1634 TII->get(AMDGPU::COPY), PhiOut) in tryFoldLCSSAPhi()
1682 if (!TII->isOperandLegal(MI, 0, &Def)) { in tryFoldLoad()
1703 TII = ST->getInstrInfo(); in runOnMachineFunction()
1704 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
1740 if (!TII->isFoldableCopy(MI)) { in runOnMachineFunction()
1807 if (!InstToErase || !TII->isFoldableCopy(*InstToErase)) in runOnMachineFunction()