Lines Matching refs:TII
195 const SIInstrInfo *TII = nullptr; member in __anonb64536af0111::SILoadStoreOptimizer
205 const SIInstrInfo &TII,
310 static unsigned getOpcodeWidth(const MachineInstr &MI, const SIInstrInfo &TII) { in getOpcodeWidth() argument
313 if (TII.isMUBUF(Opc)) { in getOpcodeWidth()
317 if (TII.isMIMG(MI)) { in getOpcodeWidth()
319 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
322 if (TII.isMTBUF(Opc)) { in getOpcodeWidth()
376 static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) { in getInstClass() argument
379 if (TII.isMUBUF(Opc)) { in getInstClass()
395 if (TII.isMIMG(Opc)) { in getInstClass()
404 if (TII.get(Opc).mayStore() || !TII.get(Opc).mayLoad() || in getInstClass()
405 TII.isGather4(Opc)) in getInstClass()
409 if (TII.isMTBUF(Opc)) { in getInstClass()
475 static unsigned getInstSubclass(unsigned Opc, const SIInstrInfo &TII) { in getInstSubclass() argument
478 if (TII.isMUBUF(Opc)) in getInstSubclass()
480 if (TII.isMIMG(Opc)) { in getInstSubclass()
485 if (TII.isMTBUF(Opc)) in getInstSubclass()
551 static AddressRegs getRegs(unsigned Opc, const SIInstrInfo &TII) { in getRegs() argument
554 if (TII.isMUBUF(Opc)) { in getRegs()
565 if (TII.isMIMG(Opc)) { in getRegs()
580 if (TII.isMTBUF(Opc)) { in getRegs()
645 InstClass = getInstClass(Opc, *LSO.TII); in setMI()
672 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
681 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
683 Width = getOpcodeWidth(*I, *LSO.TII); in setMI()
688 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
691 AddressRegs Regs = getRegs(Opc, *LSO.TII); in setMI()
795 const SIInstrInfo &TII, in dmasksCanBeCombined() argument
800 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
801 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
997 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
1000 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
1003 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
1006 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
1009 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) { in getDataRegClass()
1026 if (getInstSubclass(CI.I->getOpcode(), *TII) != in checkAndPrepareMerge()
1027 getInstSubclass(Paired.I->getOpcode(), *TII)) in checkAndPrepareMerge()
1033 if (!dmasksCanBeCombined(CI, *TII, Paired)) in checkAndPrepareMerge()
1091 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
1093 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1094 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1113 const MCInstrDesc &Read2Desc = TII->get(Opc); in mergeRead2Pair()
1125 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1131 TII->getAddNoCarry(*MBB, InsertBefore, DL, BaseReg) in mergeRead2Pair()
1148 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeRead2Pair()
1189 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1191 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1193 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1209 const MCInstrDesc &Write2Desc = TII->get(Opc); in mergeWrite2Pair()
1217 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1223 TII->getAddNoCarry(*MBB, InsertBefore, DL, BaseReg) in mergeWrite2Pair()
1261 auto MIB = BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode), DestReg); in mergeImagePair()
1280 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeImagePair()
1281 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair()
1282 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeImagePair()
1314 BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode), DestReg) in mergeSBufferLoadImmPair()
1315 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) in mergeSBufferLoadImmPair()
1325 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeSBufferLoadImmPair()
1326 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1327 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1355 auto MIB = BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode), DestReg); in mergeBufferLoadPair()
1357 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair()
1360 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
1368 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
1369 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1381 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeBufferLoadPair()
1382 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1383 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1411 auto MIB = BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode), DestReg); in mergeTBufferLoadPair()
1413 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair()
1416 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferLoadPair()
1427 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair()
1428 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1441 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeTBufferLoadPair()
1442 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1443 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1473 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1474 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1476 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeTBufferStorePair()
1482 auto MIB = BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode)) in mergeTBufferStorePair()
1485 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferStorePair()
1488 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferStorePair()
1499 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair()
1500 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1524 auto MIB = BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode), DestReg); in mergeFlatLoadPair()
1526 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatLoadPair()
1530 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatLoadPair()
1540 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeFlatLoadPair()
1541 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeFlatLoadPair()
1542 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeFlatLoadPair()
1572 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeFlatStorePair()
1573 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeFlatStorePair()
1575 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeFlatStorePair()
1581 auto MIB = BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode)) in mergeFlatStorePair()
1582 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatStorePair()
1585 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatStorePair()
1771 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1772 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1774 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeBufferStorePair()
1780 auto MIB = BuildMI(*MBB, InsertBefore, DL, TII->get(Opcode)) in mergeBufferStorePair()
1783 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferStorePair()
1786 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1795 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1796 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1811 if (TII->isInlineConstant(V)) in createRegOrImm()
1817 TII->get(AMDGPU::S_MOV_B32), Reg) in createRegOrImm()
1851 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
1860 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1871 BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::REG_SEQUENCE), FullDestReg) in computeBase()
1886 auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in updateBaseAndOffset()
1889 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); in updateBaseAndOffset()
1940 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1941 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1952 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1953 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1984 TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != nullptr) in promoteConstantOffsetToImm()
1992 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { in promoteConstantOffsetToImm()
1998 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2057 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) in promoteConstantOffsetToImm()
2061 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2164 const InstClassEnum InstClass = getInstClass(MI.getOpcode(), *TII); in collectMergeableInsts()
2358 TII = STM->getInstrInfo(); in runOnMachineFunction()
2359 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()