Lines Matching refs:TII
138 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
140 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
142 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
144 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
147 const SIInstrInfo *TII, Status InstrMode);
165 const SIInstrInfo *TII) { in getInstructionMode() argument
166 if (TII->usesFPDPRounding(MI) || in getInstructionMode()
178 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
184 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
201 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg() argument
206 BuildMI(MBB, MI, nullptr, TII->get(AMDGPU::S_SETREG_IMM32_B32)) in insertSetreg()
237 const SIInstrInfo *TII) { in processBlockPhase1() argument
248 Status InstrMode = getInstructionMode(MI, TII); in processBlockPhase1()
256 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
270 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); in processBlockPhase1()
278 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); in processBlockPhase1()
304 insertSetreg(MBB, InsertionPoint, TII, in processBlockPhase1()
328 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); in processBlockPhase1()
339 const SIInstrInfo *TII) { in processBlockPhase2() argument
403 const SIInstrInfo *TII) { in processBlockPhase3() argument
409 insertSetreg(MBB, BlockInfo[ThisBlock]->FirstInsertionPoint, TII, Delta); in processBlockPhase3()
411 insertSetreg(MBB, &MBB.instr_front(), TII, Delta); in processBlockPhase3()
418 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
425 processBlockPhase1(BB, TII); in runOnMachineFunction()
433 processBlockPhase2(*Phase2List.front(), TII); in runOnMachineFunction()
440 processBlockPhase3(BB, TII); in runOnMachineFunction()