56   const SIInstrInfo *TII;  member in __anon5b1b117c0111::GCNDPPCombine
119   if (!TII->isVOP3(Op)) {  in isShrinkable()
122   if (!TII->hasVALU32BitEncoding(Op)) {  in isShrinkable()
126   if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {  in isShrinkable()
152   if (DPP32 != -1 && TII->pseudoToMCOpcode(DPP32) != -1)  in getDPPOp()
157   if (DPP64 != -1 && TII->pseudoToMCOpcode(DPP64) != -1)  in getDPPOp()
207   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);  in createDPPInst()
209   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);  in createDPPInst()
215          !(TII->isVOPC(DPPOp) ||  in createDPPInst()
216            (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && TII->isVOPC(OrigOpE32))) &&  in createDPPInst()
220                          OrigMI.getDebugLoc(), TII->get(DPPOp))  in createDPPInst()
226     if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) {  in createDPPInst()
230     if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) {  in createDPPInst()
231       if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) {  in createDPPInst()
244               TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()),  in createDPPInst()
250     } else if (TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 &&  in createDPPInst()
251                                       TII->isVOPC(OrigOpE32))) {  in createDPPInst()
262     if (auto *Mod0 = TII->getNamedOperand(OrigMI,  in createDPPInst()
275     auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in createDPPInst()
277     if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {  in createDPPInst()
286     if (auto *Mod1 = TII->getNamedOperand(OrigMI,  in createDPPInst()
299     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
301       if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {  in createDPPInst()
310             TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers)) {  in createDPPInst()
318     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);  in createDPPInst()
320       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||  in createDPPInst()
321           !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {  in createDPPInst()
330       auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp);  in createDPPInst()
335       auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in);  in createDPPInst()
340       auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod);  in createDPPInst()
348               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) {  in createDPPInst()
359               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) {  in createDPPInst()
372       auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo);  in createDPPInst()
377       auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi);  in createDPPInst()
383     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));  in createDPPInst()
384     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));  in createDPPInst()
385     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));  in createDPPInst()
454     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
464     auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in createDPPInst()
478   auto *Imm = TII->getNamedOperand(MI, OpndName);  in hasNoImmOrEqual()
492   auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in combineDPPMov()
507     auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl);  in combineDPPMov()
517   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);  in combineDPPMov()
519   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);  in combineDPPMov()
524   auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);  in combineDPPMov()
528   auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);  in combineDPPMov()
529   auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in combineDPPMov()
583                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);  in combineDPPMov()
634           ((TII->isVOP3P(OrigOp) || TII->isVOPC(OrigOp) ||  in combineDPPMov()
635             TII->isVOP3(OrigOp)) &&  in combineDPPMov()
637           TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) {  in combineDPPMov()
646     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);  in combineDPPMov()
647     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in combineDPPMov()
653     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);  in combineDPPMov()
678       if (TII->commuteInstruction(*NewMI)) {  in combineDPPMov()
720   TII = ST->getInstrInfo();  in runOnMachineFunction()
734           auto Split = TII->expandMovDPP64(MI);  in runOnMachineFunction()