31   const SIInstrInfo *TII;  member in __anonb5245ce30111::SIShrinkInstructions
89   assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI));  in foldImmediates()
103         if (TII->isOperandLegal(MI, Src0Idx, &MovSrc)) {  in foldImmediates()
130     if (TII->commuteInstruction(MI)) {  in foldImmediates()
135       TII->commuteInstruction(MI);  in foldImmediates()
144     !TII->isInlineConstant(*Src.getParent(),  in isKImmOperand()
150     !TII->isInlineConstant(*Src.getParent(),  in isKUImmOperand()
158     return !TII->isInlineConstant(Src);  in isKImmOrKUImmOperand()
163     return !TII->isInlineConstant(Src);  in isKImmOrKUImmOperand()
173   if (!isInt<32>(Src.getImm()) || TII->isInlineConstant(Src))  in isReverseInlineImm()
199     TII->commuteInstruction(MI, false, 0, 1);  in shrinkScalarCompare()
224       MI.setDesc(TII->get(SOPKOpc));  in shrinkScalarCompare()
230   const MCInstrDesc &NewDesc = TII->get(SOPKOpc);  in shrinkScalarCompare()
232   if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(Src1)) ||  in shrinkScalarCompare()
233       (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(Src1))) {  in shrinkScalarCompare()
332   MI.setDesc(TII->get(NewOpcode));  in shrinkMIMG()
352   if (TII->hasAnyModifiersSet(MI))  in shrinkMadFma()
356   MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0);  in shrinkMadFma()
357   MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1);  in shrinkMadFma()
358   MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2);  in shrinkMadFma()
364   if (Src2.isImm() && !TII->isInlineConstant(Src2)) {  in shrinkMadFma()
392     if (Src1.isImm() && !TII->isInlineConstant(Src1))  in shrinkMadFma()
394     else if (Src0.isImm() && !TII->isInlineConstant(Src0))  in shrinkMadFma()
422     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(NewOpcode),  in shrinkMadFma()
430     TII->removeModOperands(MI);  in shrinkMadFma()
431     MI.setDesc(TII->get(NewOpcode));  in shrinkMadFma()
490       MI.setDesc(TII->get(Opc));  in shrinkScalarLogicOp()
563             TII->get(AMDGPU::IMPLICIT_DEF), Op.getReg());  in dropInstructionKeepingImpDefs()
601   unsigned Size = TII->getOpSize(MovT, 0) / 4;  in matchSwap()
678                          TII->get(AMDGPU::V_SWAP_B32))  in matchSwap()
716   MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);  in tryReplaceDeadSDST()
733   TII = ST->getInstrInfo();  in runOnMachineFunction()
734   TRI = &TII->getRegisterInfo();  in runOnMachineFunction()
762             MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));  in runOnMachineFunction()
785           if (TII->commuteInstruction(MI, false, 1, 2))  in runOnMachineFunction()
803             MI.setDesc(TII->get(Opc));  in runOnMachineFunction()
810       if (MI.isCompare() && TII->isSOPC(MI)) {  in runOnMachineFunction()
823             MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));  in runOnMachineFunction()
825             MI.setDesc(TII->get(AMDGPU::S_BREV_B32));  in runOnMachineFunction()
841       if (TII->isMIMG(MI.getOpcode()) &&  in runOnMachineFunction()
849       if (!TII->isVOP3(MI))  in runOnMachineFunction()
860       if (!TII->hasVALU32BitEncoding(MI.getOpcode())) {  in runOnMachineFunction()
867       if (!TII->canShrink(MI, *MRI)) {  in runOnMachineFunction()
870         if (!MI.isCommutable() || !TII->commuteInstruction(MI) ||  in runOnMachineFunction()
871             !TII->canShrink(MI, *MRI)) {  in runOnMachineFunction()
879       if (TII->isVOPC(Op32)) {  in runOnMachineFunction()
907             TII->getNamedOperand(MI, AMDGPU::OpName::src2);  in runOnMachineFunction()
920       const MachineOperand *SDst = TII->getNamedOperand(MI,  in runOnMachineFunction()
934         const MachineOperand *Src2 = TII->getNamedOperand(MI,  in runOnMachineFunction()
949       MachineInstr *Inst32 = TII->buildShrunkInst(MI, Op32);  in runOnMachineFunction()