Lines Matching refs:TII
62 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaRegister() argument
66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
72 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaOffset() argument
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaOffset()
83 const TargetInstrInfo &TII, unsigned DRegNum, in EmitCfiOffset() argument
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitCfiOffset()
100 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededExtSP() argument
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
123 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededLDAWSP() argument
129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm); in IfNeededLDAWSP()
192 const DebugLoc &dl, const TargetInstrInfo &TII, in RestoreSpillList() argument
199 IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj); in RestoreSpillList()
202 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg) in RestoreSpillList()
230 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo(); in emitPrologue() local
242 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0); in emitPrologue()
264 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)); in emitPrologue()
269 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in emitPrologue()
271 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0); in emitPrologue()
284 IfNeededExtSP(MBB, MBBI, dl, TII, OffsetFromTop, Adjusted, FrameSize, in emitPrologue()
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode)) in emitPrologue()
296 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset); in emitPrologue()
301 IfNeededExtSP(MBB, MBBI, dl, TII, FrameSize, Adjusted, FrameSize, in emitPrologue()
307 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0); in emitPrologue()
309 EmitDefCfaRegister(MBB, MBBI, dl, TII, MF, in emitPrologue()
321 EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset); in emitPrologue()
333 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
336 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
347 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo(); in emitEpilogue() local
367 RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList); in emitEpilogue()
372 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg); in emitEpilogue()
373 BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg); in emitEpilogue()
386 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr); in emitEpilogue()
391 RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList); in emitEpilogue()
395 IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj); in emitEpilogue()
401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)) in emitEpilogue()
409 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj); in emitEpilogue()
422 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); in spillCalleeSavedRegisters() local
438 TII.storeRegToStackSlot(MBB, MI, Reg, true, I.getFrameIdx(), RC, TRI); in spillCalleeSavedRegisters()
452 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); in restoreCalleeSavedRegisters() local
463 TII.loadRegFromStackSlot(MBB, MI, Reg, CSR.getFrameIdx(), RC, TRI); in restoreCalleeSavedRegisters()
483 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo(); in eliminateCallFramePseudoInstr() local
511 New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode)).addImm(Amount); in eliminateCallFramePseudoInstr()
515 New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode), XCore::SP) in eliminateCallFramePseudoInstr()