130   bool canAddSU(SUnit &SU, const SIInstrInfo *TII) {  in canAddSU()  argument
136       return canAddMI(MI, TII);  in canAddSU()
146         B, E, [this, TII](MachineInstr &MI) { return canAddMI(MI, TII); });  in canAddSU()
156 bool isMFMASGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isMFMASGMember()  argument
157   return TII->isMFMA(MI);  in isMFMASGMember()
160 bool isVALUSGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isVALUSGMember()  argument
161   return TII->isVALU(MI) && !TII->isMFMA(MI);  in isVALUSGMember()
164 bool isSALUSGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isSALUSGMember()  argument
165   return TII->isSALU(MI);  in isSALUSGMember()
168 bool isVMEMSGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isVMEMSGMember()  argument
169   return TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI));  in isVMEMSGMember()
172 bool isVMEMReadSGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isVMEMReadSGMember()  argument
174          (TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI)));  in isVMEMReadSGMember()
177 bool isVMEMWriteSGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isVMEMWriteSGMember()  argument
179          (TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI)));  in isVMEMWriteSGMember()
182 bool isDSWriteSGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isDSWriteSGMember()  argument
183   return MI.mayStore() && TII->isDS(MI);  in isDSWriteSGMember()
186 bool isDSReadSGMember(const MachineInstr &MI, const SIInstrInfo *TII) {  in isDSReadSGMember()  argument
187   return MI.mayLoad() && TII->isDS(MI);  in isDSReadSGMember()
192   const SIInstrInfo *TII;  member in __anona5db2d930111::IGroupLPDAGMutation
205   const SIInstrInfo *TII;  member in __anona5db2d930111::SchedBarrierDAGMutation
259   TII = ST.getInstrInfo();  in apply()
280       if (SG.canAddSU(SU, TII))  in apply()
301   TII = ST.getInstrInfo();  in apply()
409     if (SG->canAddSU(SU, TII))  in initSchedGroup()