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Searched refs:Mips (Results 1 – 25 of 170) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
505 case Mips::BEQ: return Mips::BNE; in getOppositeBranchOpc()
507 case Mips::BNE: return Mips::BEQ; in getOppositeBranchOpc()
509 case Mips::BGTZ: return Mips::BLEZ; in getOppositeBranchOpc()
510 case Mips::BGEZ: return Mips::BLTZ; in getOppositeBranchOpc()
511 case Mips::BLTZ: return Mips::BGEZ; in getOppositeBranchOpc()
512 case Mips::BLEZ: return Mips::BGTZ; in getOppositeBranchOpc()
523 case Mips::BC1T: return Mips::BC1F; in getOppositeBranchOpc()
524 case Mips::BC1F: return Mips::BC1T; in getOppositeBranchOpc()
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H A DMipsInstrInfo.cpp302 case Mips::BEQ: case Mips::BEQ64: in isBranchOffsetInRange()
304 case Mips::BGEZ: case Mips::BGEZ64: in isBranchOffsetInRange()
308 case Mips::BGTZ: case Mips::BGTZ64: in isBranchOffsetInRange()
310 case Mips::BLEZ: case Mips::BLEZ64: in isBranchOffsetInRange()
312 case Mips::BLTZ: case Mips::BLTZ64: in isBranchOffsetInRange()
316 case Mips::BNE: case Mips::BNE64: in isBranchOffsetInRange()
353 case Mips::BEQC: case Mips::BEQC64: in isBranchOffsetInRange()
354 case Mips::BNEC: case Mips::BNEC64: in isBranchOffsetInRange()
355 case Mips::BGEC: case Mips::BGEC64: in isBranchOffsetInRange()
356 case Mips::BGEUC: case Mips::BGEUC64: in isBranchOffsetInRange()
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H A DMipsExpandPseudo.cpp88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
91 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
92 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
224 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwap()
227 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicCmpSwap()
235 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; in expandAtomicCmpSwap()
236 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicCmpSwap()
603 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicBinOp()
606 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicBinOp()
619 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; in expandAtomicBinOp()
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H A DMips16InstrInfo.cpp160 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16; in getOppositeBranchOpc()
161 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16; in getOppositeBranchOpc()
162 case Mips::BeqzRxImm16: return Mips::BnezRxImm16; in getOppositeBranchOpc()
163 case Mips::BnezRxImm16: return Mips::BeqzRxImm16; in getOppositeBranchOpc()
164 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16; in getOppositeBranchOpc()
167 case Mips::Btnez16: return Mips::Bteqz16; in getOppositeBranchOpc()
168 case Mips::BtnezX16: return Mips::BteqzX16; in getOppositeBranchOpc()
172 case Mips::Bteqz16: return Mips::Btnez16; in getOppositeBranchOpc()
173 case Mips::BteqzX16: return Mips::BtnezX16; in getOppositeBranchOpc()
250 Mips::Restore16:Mips::RestoreX16; in restoreFrame()
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H A DMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
152 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP in getReservedRegs()
156 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 in getReservedRegs()
177 Reserved.set(Mips::GP); in getReservedRegs()
282 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; in getFrameRegister()
284 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : in getFrameRegister()
285 (IsN64 ? Mips::SP_64 : Mips::SP); in getFrameRegister()
300 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64; in canRealignStack()
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H A DMicroMipsSizeReduction.cpp380 {Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, in ConsecutiveRegisters()
381 Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, in ConsecutiveRegisters()
382 Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in ConsecutiveRegisters()
383 Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, in ConsecutiveRegisters()
384 Mips::SP, Mips::FP, Mips::RA}}; in ConsecutiveRegisters()
575 if (Reg == Mips::ZERO || Reg == Mips::V0 || Reg == Mips::V1 || in IsMovepSrcRegister()
576 Reg == Mips::S0 || Reg == Mips::S1 || Reg == Mips::S2 || in IsMovepSrcRegister()
577 Reg == Mips::S3 || Reg == Mips::S4) in IsMovepSrcRegister()
587 if (Reg == Mips::A0 || Reg == Mips::A1 || Reg == Mips::A2 || in IsMovepDestinationReg()
588 Reg == Mips::A3 || Reg == Mips::S5 || Reg == Mips::S6) in IsMovepDestinationReg()
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H A DMipsSERegisterInfo.cpp68 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
69 case Mips::ST_B: in getLoadStoreOffsetSizeInBits()
71 case Mips::LD_H: in getLoadStoreOffsetSizeInBits()
72 case Mips::ST_H: in getLoadStoreOffsetSizeInBits()
74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
80 case Mips::LL: in getLoadStoreOffsetSizeInBits()
82 case Mips::LLD: in getLoadStoreOffsetSizeInBits()
83 case Mips::LLE: in getLoadStoreOffsetSizeInBits()
84 case Mips::SC: in getLoadStoreOffsetSizeInBits()
86 case Mips::SCD: in getLoadStoreOffsetSizeInBits()
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H A DMipsRegisterBankInfo.cpp26 namespace Mips { namespace
402 return &Mips::ValueMappings[Mips::MSAIdx]; in getMSAMapping()
406 return Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx] in getFprbMapping()
407 : &Mips::ValueMappings[Mips::DPRIdx]; in getFprbMapping()
417 return &Mips::ValueMappings[Mips::GPRIdx]; in getGprbOrCustomMapping()
420 return &Mips::ValueMappings[Mips::DPRIdx]; in getGprbOrCustomMapping()
484 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; in getInstrMapping()
493 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; in getInstrMapping()
656 &Mips::ValueMappings[Mips::GPRIdx]}); in getInstrMapping()
661 &Mips::ValueMappings[Mips::GPRIdx], in getInstrMapping()
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H A DMipsInstructionSelector.cpp150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
213 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu; in selectLoadStoreOpCode()
228 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
231 return isStore ? Mips::SDC164 : Mips::LDC164; in selectLoadStoreOpCode()
232 return isStore ? Mips::SDC1 : Mips::LDC1; in selectLoadStoreOpCode()
241 return isStore ? Mips::ST_B : Mips::LD_B; in selectLoadStoreOpCode()
243 return isStore ? Mips::ST_H : Mips::LD_H; in selectLoadStoreOpCode()
245 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
247 return isStore ? Mips::ST_D : Mips::LD_D; in selectLoadStoreOpCode()
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H A DMips16ISelLowering.cpp186 return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB); in EmitInstrWithCustomInserter()
188 return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB); in EmitInstrWithCustomInserter()
192 return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB); in EmitInstrWithCustomInserter()
214 Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
216 Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); in EmitInstrWithCustomInserter()
218 Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
220 Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
222 Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); in EmitInstrWithCustomInserter()
224 Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
231 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); in EmitInstrWithCustomInserter()
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H A DMipsBranchExpansion.cpp385 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR; in buildProperJumpMI()
386 unsigned JIC = ABI.IsN64() ? Mips::JIC64 : Mips::JIC; in buildProperJumpMI()
387 unsigned JR_HB = ABI.IsN64() ? Mips::JR_HB64 : Mips::JR_HB; in buildProperJumpMI()
399 unsigned ATReg = ABI.IsN64() ? Mips::AT_64 : Mips::AT; in buildProperJumpMI()
435 ? STI->inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC in expandToLongBranch()
470 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
516 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
519 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
630 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64) in expandToLongBranch()
737 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
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H A DMipsSEFrameLowering.cpp134 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4); in expandInstr()
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
419 unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND; in emitPrologue()
422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
813 Reg == Mips::HI0 || Reg == Mips::HI0_64); in spillCalleeSavedRegisters()
820 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
823 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; in spillCalleeSavedRegisters()
865 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; in determineCalleeSaves()
867 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7; in determineCalleeSaves()
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H A DMipsAsmPrinter.cpp928 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE); in EmitSwapFPIntParams()
932 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); in EmitSwapFPIntParams()
935 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
938 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
939 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); in EmitSwapFPIntParams()
942 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
961 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
964 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
967 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
968 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE); in EmitSwapFPIntRetval()
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H A DMipsFastISel.cpp303 Opc = Mips::OR; in emitLogicalOp()
368 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
710 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
714 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
718 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32; in emitCmp()
722 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32; in emitCmp()
726 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32; in emitCmp()
730 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32; in emitCmp()
739 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
1325 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2, in fastLowerArguments()
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H A DMipsSEISelDAGToDAG.cpp93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
142 .addDef(Mips::AT) in emitMCountABI()
147 .addDef(Mips::SP) in emitMCountABI()
163 case Mips::RDDSP: in processFunctionAfterISel()
166 case Mips::WRDSP: in processFunctionAfterISel()
181 case Mips::JAL: in processFunctionAfterISel()
182 case Mips::JAL_MM: in processFunctionAfterISel()
194 case Mips::JALR: in processFunctionAfterISel()
965 Opc = (Subtarget->isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32); in trySelect()
1146 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu; in trySelect()
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H A DMipsMachineFunction.cpp43 return Mips::CPU16RegsRegClass; in getGlobalBaseRegClass()
46 return Mips::GPRMM16RegClass; in getGlobalBaseRegClass()
49 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
51 return Mips::GPR32RegClass; in getGlobalBaseRegClass()
81 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
88 MBB.addLiveIn(Mips::T9_64); in initGlobalBaseReg()
97 .addReg(Mips::T9_64); in initGlobalBaseReg()
116 MBB.addLiveIn(Mips::T9); in initGlobalBaseReg()
125 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
151 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp48 case Mips::fixup_Mips_LO16: in adjustFixupValue()
49 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
63 case Mips::fixup_MIPS_PCLO16: in adjustFixupValue()
73 case Mips::fixup_Mips_SUB: in adjustFixupValue()
76 case Mips::fixup_Mips_PC16: in adjustFixupValue()
96 case Mips::fixup_Mips_26: in adjustFixupValue()
102 case Mips::fixup_Mips_HI16: in adjustFixupValue()
103 case Mips::fixup_Mips_GOT: in adjustFixupValue()
108 case Mips::fixup_MIPS_PCHI16: in adjustFixupValue()
264 case Mips::fixup_Mips_16: in applyFixup()
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H A DMipsABIInfo.cpp27 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
30 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
31 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
76 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
80 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
84 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
88 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
112 return ArePtrs64bit() ? Mips::AND64 : Mips::AND; in GetPtrAndOp()
116 return ArePtrs64bit() ? Mips::OR64 : Mips::OR; in GetGPRMoveOp()
121 Mips::A0, Mips::A1, Mips::A2, Mips::A3 in GetEhDataReg()
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H A DMipsNaClELFStreamer.cpp220 case Mips::LB: in isBasePlusOffsetMemoryAccess()
221 case Mips::LBu: in isBasePlusOffsetMemoryAccess()
222 case Mips::LH: in isBasePlusOffsetMemoryAccess()
223 case Mips::LHu: in isBasePlusOffsetMemoryAccess()
224 case Mips::LW: in isBasePlusOffsetMemoryAccess()
227 case Mips::LL: in isBasePlusOffsetMemoryAccess()
235 case Mips::SB: in isBasePlusOffsetMemoryAccess()
236 case Mips::SH: in isBasePlusOffsetMemoryAccess()
237 case Mips::SW: in isBasePlusOffsetMemoryAccess()
248 case Mips::SC: in isBasePlusOffsetMemoryAccess()
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H A DMipsMCCodeEmitter.cpp74 case Mips::DSLL: in LowerLargeShift()
77 case Mips::DSRL: in LowerLargeShift()
80 case Mips::DSRA: in LowerLargeShift()
83 case Mips::DROTR: in LowerLargeShift()
162 case Mips::DSLL: in encodeInstruction()
163 case Mips::DSRL: in encodeInstruction()
164 case Mips::DSRA: in encodeInstruction()
169 case Mips::BEQC: in encodeInstruction()
187 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && in encodeInstruction()
203 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
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H A DMipsInstPrinter.cpp36 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
84 case Mips::RDHWR: in printInst()
89 case Mips::Save16: in printInst()
120 case Mips::RDHWR: in printInst()
270 case Mips::BEQ: in printAlias()
282 case Mips::BNE: in printAlias()
295 case Mips::BC1T: in printAlias()
299 case Mips::BC1F: in printAlias()
303 case Mips::JALR: in printAlias()
317 case Mips::NOR: in printAlias()
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H A DMipsELFObjectWriter.cpp233 case Mips::fixup_Mips_16: in getRelocType()
236 case Mips::fixup_Mips_32: in getRelocType()
239 case Mips::fixup_Mips_64: in getRelocType()
249 case Mips::fixup_Mips_PC16: in getRelocType()
297 case Mips::fixup_Mips_26: in getRelocType()
301 case Mips::fixup_Mips_GOT: in getRelocType()
303 case Mips::fixup_Mips_HI16: in getRelocType()
305 case Mips::fixup_Mips_LO16: in getRelocType()
307 case Mips::fixup_Mips_TLSGD: in getRelocType()
341 case Mips::fixup_Mips_SUB: in getRelocType()
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H A DMipsABIFlagsSection.h32 Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
34 Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
36 Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
38 Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
127 GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setGPRSizeFromPredicates()
135 CPR1Size = Mips::AFL_REG_128; in setCPR1SizeFromPredicates()
137 CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setCPR1SizeFromPredicates()
154 ASESet |= Mips::AFL_ASE_DSP; in setASESetFromPredicates()
158 ASESet |= Mips::AFL_ASE_MSA; in setASESetFromPredicates()
164 ASESet |= Mips::AFL_ASE_MT; in setASESetFromPredicates()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp123 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
124 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
128 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
129 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
130 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
2564 case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64: in tryExpandInstruction()
2565 case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64: in tryExpandInstruction()
2566 case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64: in tryExpandInstruction()
4055 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4062 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1643 case Mips::LD_B: in DecodeMSA128Mem()
1644 case Mips::ST_B: in DecodeMSA128Mem()
1647 case Mips::LD_H: in DecodeMSA128Mem()
1648 case Mips::ST_H: in DecodeMSA128Mem()
1651 case Mips::LD_W: in DecodeMSA128Mem()
1652 case Mips::ST_W: in DecodeMSA128Mem()
1655 case Mips::LD_D: in DecodeMSA128Mem()
1656 case Mips::ST_D: in DecodeMSA128Mem()
2300 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in DecodeRegListOperand()
2301 Mips::S6, Mips::S7, Mips::FP}; in DecodeRegListOperand()
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