[NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D119846

[WebAssembly] Support single-floating-point immediate value

As mentioned in TODO comment, casting double to float causes NaNs to change bits.
To avoid the change, this patch adds support for single-

[WebAssembly] Support single-floating-point immediate value

As mentioned in TODO comment, casting double to float causes NaNs to change bits.
To avoid the change, this patch adds support for single-floating-point immediate value on MachineCode.

Patch by Yuta Saito.

Differential Revision: https://reviews.llvm.org/D77384

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[Mips] Error if a non-immediate operand is used while an immediate is expected

The 32-bit type relocation (R_MIPS_32) cannot be used for instructions below:

ori $4, $4, start
ori $4, $4, (start - .

[Mips] Error if a non-immediate operand is used while an immediate is expected

The 32-bit type relocation (R_MIPS_32) cannot be used for instructions below:

ori $4, $4, start
ori $4, $4, (start - .)

We should print an error instead.

Reviewed By: atanasyan, MaskRay

Differential Revision: https://reviews.llvm.org/D81908

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[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*

[mips] Split long lines in the code. NFC

[mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructions

llvm-svn: 373591

Delete dead stores

llvm-svn: 365903

Reapply: [mips] Handle MipsMCExpr sub-expression for the MEK_DTPREL tag

This reapplies commit r351987 with a failed test fix. Now the test
accepts both DW_OP_GNU_push_tls_address and DW_OP_form_tls_

Reapply: [mips] Handle MipsMCExpr sub-expression for the MEK_DTPREL tag

This reapplies commit r351987 with a failed test fix. Now the test
accepts both DW_OP_GNU_push_tls_address and DW_OP_form_tls_address
opcode.

Original commit message:
```
This is a fix for a regression introduced by the rL348194 commit. In
that change new type (MEK_DTPREL) of MipsMCExpr expression was added,
but in some places of the code this type of expression considered as
unexpected.

This change fixes the bug. The MEK_DTPREL type of expression is used for
marking TLS DIEExpr only and contains a regular sub-expression. Where we
need to handle the expression, we retrieve the sub-expression and
handle it in a common way.
```

llvm-svn: 352034

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Revert "[mips] Handle MipsMCExpr sub-expression for the MEK_DTPREL tag"

This reverts commit r351987 as it broke some bots.

llvm-svn: 351998

[mips] Handle MipsMCExpr sub-expression for the MEK_DTPREL tag

This is a fix for a regression introduced by the rL348194 commit. In
that change new type (MEK_DTPREL) of MipsMCExpr expression was add

[mips] Handle MipsMCExpr sub-expression for the MEK_DTPREL tag

This is a fix for a regression introduced by the rL348194 commit. In
that change new type (MEK_DTPREL) of MipsMCExpr expression was added,
but in some places of the code this type of expression considered as
unexpected.

This change fixes the bug. The MEK_DTPREL type of expression is used for
marking TLS DIEExpr only and contains a regular sub-expression. Where we
need to handle the expression, we retrieve the sub-expression and
handle it in a common way.

llvm-svn: 351987

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Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[mips] Fix TestDWARF32Version5Addr8AllForms test failure on MIPS hosts

The `DIEExpr` is used in debug information entries for either TLS variables
or call sites. For now the last case is unsupported

[mips] Fix TestDWARF32Version5Addr8AllForms test failure on MIPS hosts

The `DIEExpr` is used in debug information entries for either TLS variables
or call sites. For now the last case is unsupported for targets with delay
slots, for MIPS in particular.

The `DIEExpr::EmitValue` method calls a virtual `EmitDebugThreadLocal`
routine which, in case of MIPS, always emits either `.dtprelword` or
`.dtpreldword` directives. That is okay for "main" code, but in unit
tests `DIEExpr` instances can be created not for TLS variables only even
on MIPS hosts. That is a reason of the `TestDWARF32Version5Addr8AllForms`
failure because handling of the `R_MIPS_TLS_DTPREL` relocation writes
incorrect value into dwarf structures. And anyway unconditional emitting
of `.dtprelword` directives will be incorrect when/if debug information
entries for call sites become supported on MIPS.

The patch solves the problem by wrapping expression created in the
`MipsTargetObjectFile::getDebugThreadLocalSymbol` method in to the
`MipsMCExpr` expression with a new `MEK_DTPREL` tag. This tag is
recognized in the `MipsAsmPrinter::EmitDebugThreadLocal` method and
`.dtprelword` directives created in this case only. In other cases the
expression saved as a regular data.

Differential Revision: http://reviews.llvm.org/D54937

llvm-svn: 348194

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[mips][microMIPS] Fix the definition of MOVEP instruction

The patch fixes definition of MOVEP instruction. Two registers are used
instead of register pairs. This is necessary as machine verifier can

[mips][microMIPS] Fix the definition of MOVEP instruction

The patch fixes definition of MOVEP instruction. Two registers are used
instead of register pairs. This is necessary as machine verifier cannot
handle register pairs.

Patch by Milena Vujosevic Janicic.

Differential revision: https://reviews.llvm.org/D52035

llvm-svn: 342571

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[mips] Remove dead code. NFC

llvm-svn: 336777

[mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 relocations

Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and
R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16

[mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 relocations

Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and
R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16 chains of
relocations for %lo(%neg(%gp_rel())) and %hi(%neg(%gp_rel()))
expressions in case of microMIPS.

Differential Revision: http://reviews.llvm.org/D47220

llvm-svn: 333409

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[mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations

Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher()
and %highest() expressions in case of microMIPS. These reloca

[mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations

Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher()
and %highest() expressions in case of microMIPS. These relocations do
exactly the same things as R_MIPS_HIGHER / R_MIPS_HIGHEST, but for
consistency it's better to write microMIPS variants.

Differential Revision: http://reviews.llvm.org/D47219

llvm-svn: 333407

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[mips] Handle the emission of microMIPSr6 sll instruction when used as a nop.

This instruction is encoded as zero, so we have handle that case when checking
for unimplemented opcodes when producing

[mips] Handle the emission of microMIPSr6 sll instruction when used as a nop.

This instruction is encoded as zero, so we have handle that case when checking
for unimplemented opcodes when producing the encoding for an instruction.

llvm-svn: 321066

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[mips] Removal of microMIPS64R6

All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.

This is LLVM part of patch.

Differential Revision

[mips] Removal of microMIPS64R6

All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.

This is LLVM part of patch.

Differential Revision: https://reviews.llvm.org/D35625

llvm-svn: 320350

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[mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version

Previously, the 'movep' instruction was defined for microMIPS32r3 and
shared that definition with microMIPS32R6. 'movep' was re-encod

[mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version

Previously, the 'movep' instruction was defined for microMIPS32r3 and
shared that definition with microMIPS32R6. 'movep' was re-encoded for
microMIPS32r6, so this patch provides the correct encoding.

Secondly, correct the encoding of the 'rs' and 'rt' operands which have
an instruction specific encoding for the registers those operands accept.

Finally, correct the decoding of the 'dst_regs' operand which was extracting
the relevant field from the instruction, but was actually extracting the
field from the alreadly extracted field.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39495

llvm-svn: 317475

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[mips] Pick the right variant of DINS upfront and enable target instruction verification

This patch complements D16810 "[mips] Make isel select the correct DEXT variant
up front.". Now ISel picks th

[mips] Pick the right variant of DINS upfront and enable target instruction verification

This patch complements D16810 "[mips] Make isel select the correct DEXT variant
up front.". Now ISel picks the right variant of DINS, so now there is no need
to replace DINS with the appropriate variant during
MipsMCCodeEmitter::encodeInstruction().

This patch also enables target specific instruction verification for ins, dins,
dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that
are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these
constraints are not checked during instruction selection. Adding machine
verification should catch outstanding cases.

Finally, correct a bug that instruction verification uncovered, where the
position operand of a DINSU generated during lowering was being silently
and accidently corrected to the correct value.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D34809

llvm-svn: 313254

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Sort the remaining #include lines in include/... and lib/....

I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line

Sort the remaining #include lines in include/... and lib/....

I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.

I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.

This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.

Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).

llvm-svn: 304787

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[mips] Emit R_MICROMIPS_TLS_GOTTPREL relocation for %gottprel in case of microMIPS

In case of microMIPS mode %gottprel operator should emit microMIPS
relocation R_MICROMIPS_TLS_GOTTPREL, not R_MIPS_

[mips] Emit R_MICROMIPS_TLS_GOTTPREL relocation for %gottprel in case of microMIPS

In case of microMIPS mode %gottprel operator should emit microMIPS
relocation R_MICROMIPS_TLS_GOTTPREL, not R_MIPS_TLS_GOTTPREL.

Differential Revision: http://reviews.llvm.org/D32617

llvm-svn: 301763

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[Mips] Emit the correct DINS variant

This patch fixes emitting of correct variant of DINS instruction.

Differential Revision: https://reviews.llvm.org/D30988

llvm-svn: 298596

[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

llvm-svn: 293729

[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations
Differential Revision: https://reviews.llvm.org/D

[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations
Differential Revision: https://reviews.llvm.org/D22667

llvm-svn: 279429

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