Lines Matching refs:Mips
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
128 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
136 return &Mips::FGR32RegClass; in getRegClassForTypeOnBank()
137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank()
150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
199 return Mips::SW; in selectLoadStoreOpCode()
201 return Mips::SH; in selectLoadStoreOpCode()
203 return Mips::SB; in selectLoadStoreOpCode()
211 return Mips::LW; in selectLoadStoreOpCode()
213 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu; in selectLoadStoreOpCode()
215 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu; in selectLoadStoreOpCode()
228 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
231 return isStore ? Mips::SDC164 : Mips::LDC164; in selectLoadStoreOpCode()
232 return isStore ? Mips::SDC1 : Mips::LDC1; in selectLoadStoreOpCode()
241 return isStore ? Mips::ST_B : Mips::LD_B; in selectLoadStoreOpCode()
243 return isStore ? Mips::ST_H : Mips::LD_H; in selectLoadStoreOpCode()
245 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
247 return isStore ? Mips::ST_D : Mips::LD_D; in selectLoadStoreOpCode()
299 if (I.getOpcode() == Mips::G_MUL && in select()
301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
322 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
325 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
332 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
342 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
361 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)) in select()
363 .addUse(Mips::ZERO) in select()
373 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
374 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
381 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
382 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
389 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
401 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
403 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
413 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
422 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
471 if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO)) in select()
473 if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) in select()
480 Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
481 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
483 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
484 if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3, in select()
487 if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), in select()
512 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
518 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV)) in select()
526 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)) in select()
537 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) in select()
555 STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64; in select()
576 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
598 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
609 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
610 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
618 STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, in select()
630 Size == 32 ? Mips::FABS_S in select()
631 : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32; in select()
647 Opcode = Mips::TRUNC_W_S; in select()
649 Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32; in select()
650 Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass); in select()
657 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
669 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
689 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
693 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
702 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
704 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
712 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
725 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
735 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
749 if (Opcode == Mips::SLTiu || Opcode == Mips::XORi) in select()
757 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
765 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); in select()
766 Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1); in select()
769 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); in select()
770 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp); in select()
773 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS); in select()
776 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS); in select()
777 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
780 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS); in select()
783 Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS); in select()
784 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
787 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
790 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
791 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
794 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
797 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
798 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
828 MipsFCMPCondCode = Mips::FCOND_UN; in select()
833 MipsFCMPCondCode = Mips::FCOND_OEQ; in select()
838 MipsFCMPCondCode = Mips::FCOND_UEQ; in select()
843 MipsFCMPCondCode = Mips::FCOND_OLT; in select()
848 MipsFCMPCondCode = Mips::FCOND_ULT; in select()
853 MipsFCMPCondCode = Mips::FCOND_OLE; in select()
858 MipsFCMPCondCode = Mips::FCOND_ULE; in select()
869 unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I; in select()
871 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
872 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
874 .addUse(Mips::ZERO) in select()
879 Size == 32 ? Mips::FCMP_S32 in select()
880 : STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32; in select()
890 .addUse(Mips::ZERO) in select()
891 .addUse(Mips::FCC0) in select()
900 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); in select()
907 Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
909 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)) in select()
916 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) in select()