119     TmpInst0.setOpcode(Mips::JALR64);  in emitPseudoIndirectBranch()
124       TmpInst0.setOpcode(Mips::JRC16_MMR6);  in emitPseudoIndirectBranch()
126       TmpInst0.setOpcode(Mips::JALR);  in emitPseudoIndirectBranch()
131     TmpInst0.setOpcode(Mips::JR_MM);  in emitPseudoIndirectBranch()
134     TmpInst0.setOpcode(Mips::JR);  in emitPseudoIndirectBranch()
140     unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;  in emitPseudoIndirectBranch()
203   if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {  in emitInstruction()
207   if (Opc == Mips::CONSTPOOL_ENTRY) {  in emitInstruction()
235   case Mips::PATCHABLE_FUNCTION_ENTER:  in emitInstruction()
238   case Mips::PATCHABLE_FUNCTION_EXIT:  in emitInstruction()
241   case Mips::PATCHABLE_TAIL_CALL:  in emitInstruction()
263     if (I->getOpcode() == Mips::PseudoReturn ||  in emitInstruction()
264         I->getOpcode() == Mips::PseudoReturn64 ||  in emitInstruction()
265         I->getOpcode() == Mips::PseudoIndirectBranch ||  in emitInstruction()
266         I->getOpcode() == Mips::PseudoIndirectBranch64 ||  in emitInstruction()
267         I->getOpcode() == Mips::TAILCALLREG ||  in emitInstruction()
268         I->getOpcode() == Mips::TAILCALLREG64) {  in emitInstruction()
337   unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;  in printSavedRegsBitmask()
338   unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;  in printSavedRegsBitmask()
339   unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;  in printSavedRegsBitmask()
349     if (Mips::FGR32RegClass.contains(Reg)) {  in printSavedRegsBitmask()
352     } else if (Mips::AFGR64RegClass.contains(Reg)) {  in printSavedRegsBitmask()
356     } else if (Mips::GPR32RegClass.contains(Reg))  in printSavedRegsBitmask()
736   case Mips::SWM32_MM:  in printMemOperand()
737   case Mips::LWM32_MM:  in printMemOperand()
761   O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());  in printFCCOperand()
859   I.setOpcode(Mips::JAL);  in EmitJal()
882   if (Opcode == Mips::MTC1) {  in EmitInstrRegReg()
922   unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;  in EmitSwapFPIntParams()
925     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
928     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);  in EmitSwapFPIntParams()
931     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
932     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
935     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
938     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
939     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
942     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
943     EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);  in EmitSwapFPIntParams()
955   unsigned MovOpc = Mips::MFC1;  in EmitSwapFPIntRetval()
958     EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);  in EmitSwapFPIntRetval()
961     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
964     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
967     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
968     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);  in EmitSwapFPIntRetval()
1097   EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);  in EmitFPCallStub()
1112   EmitInstrReg(*STI, Mips::JR, Mips::S2);  in EmitFPCallStub()
1214   EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)  in EmitSled()
1215                                    .addReg(Mips::ZERO)  in EmitSled()
1216                                    .addReg(Mips::ZERO)  in EmitSled()
1220     EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)  in EmitSled()
1221                                      .addReg(Mips::ZERO)  in EmitSled()
1222                                      .addReg(Mips::ZERO)  in EmitSled()
1229                    MCInstBuilder(Mips::ADDiu)  in EmitSled()
1230                        .addReg(Mips::T9)  in EmitSled()
1231                        .addReg(Mips::T9)  in EmitSled()
1298   return (Opcode == Mips::LONG_BRANCH_LUi  in isLongBranchPseudo()
1299           || Opcode == Mips::LONG_BRANCH_LUi2Op  in isLongBranchPseudo()
1300           || Opcode == Mips::LONG_BRANCH_LUi2Op_64  in isLongBranchPseudo()
1301           || Opcode == Mips::LONG_BRANCH_ADDiu  in isLongBranchPseudo()
1302           || Opcode == Mips::LONG_BRANCH_ADDiu2Op  in isLongBranchPseudo()
1303           || Opcode == Mips::LONG_BRANCH_DADDiu  in isLongBranchPseudo()
1304           || Opcode == Mips::LONG_BRANCH_DADDiu2Op);  in isLongBranchPseudo()