Lines Matching refs:Mips

37 const unsigned IndirectBranchMaskReg = Mips::T6;
38 const unsigned LoadStoreStackMaskReg = Mips::T7;
59 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
63 return MI.getOperand(0).getReg() == Mips::ZERO; in isIndirectJump()
65 return MI.getOpcode() == Mips::JR; in isIndirectJump()
70 && MI.getOperand(0).getReg() == Mips::SP); in isStackPointerFirstOperand()
82 case Mips::JAL: in isCall()
83 case Mips::BAL: in isCall()
84 case Mips::BAL_BR: in isCall()
85 case Mips::BLTZAL: in isCall()
86 case Mips::BGEZAL: in isCall()
89 case Mips::JALR: in isCall()
93 if (MI.getOperand(0).getReg() == Mips::ZERO) in isCall()
104 MaskInst.setOpcode(Mips::AND); in emitMask()
137 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); in sandboxLoadStoreStackChange()
220 case Mips::LB: in isBasePlusOffsetMemoryAccess()
221 case Mips::LBu: in isBasePlusOffsetMemoryAccess()
222 case Mips::LH: in isBasePlusOffsetMemoryAccess()
223 case Mips::LHu: in isBasePlusOffsetMemoryAccess()
224 case Mips::LW: in isBasePlusOffsetMemoryAccess()
225 case Mips::LWC1: in isBasePlusOffsetMemoryAccess()
226 case Mips::LDC1: in isBasePlusOffsetMemoryAccess()
227 case Mips::LL: in isBasePlusOffsetMemoryAccess()
228 case Mips::LL_R6: in isBasePlusOffsetMemoryAccess()
229 case Mips::LWL: in isBasePlusOffsetMemoryAccess()
230 case Mips::LWR: in isBasePlusOffsetMemoryAccess()
235 case Mips::SB: in isBasePlusOffsetMemoryAccess()
236 case Mips::SH: in isBasePlusOffsetMemoryAccess()
237 case Mips::SW: in isBasePlusOffsetMemoryAccess()
238 case Mips::SWC1: in isBasePlusOffsetMemoryAccess()
239 case Mips::SDC1: in isBasePlusOffsetMemoryAccess()
240 case Mips::SWL: in isBasePlusOffsetMemoryAccess()
241 case Mips::SWR: in isBasePlusOffsetMemoryAccess()
248 case Mips::SC: in isBasePlusOffsetMemoryAccess()
249 case Mips::SC_R6: in isBasePlusOffsetMemoryAccess()
259 return Reg != Mips::SP && Reg != Mips::T8; in baseRegNeedsLoadStoreMask()