| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 114 case ISD::Constant: in getOperationName()
141 case ISD::INTRINSIC_WO_CHAIN: in getOperationName()
142 case ISD::INTRINSIC_VOID: in getOperationName()
143 case ISD::INTRINSIC_W_CHAIN: { in getOperationName()
156 case ISD::TargetConstant: in getOperationName()
413 case ISD::PSEUDO_PROBE: in getOperationName()
419 case ISD::PREALLOCATED_SETUP: in getOperationName()
421 case ISD::PREALLOCATED_ARG: in getOperationName()
443 case ISD::CONDCODE: in getOperationName()
489 case ISD::STACKMAP: in getOperationName()
[all …]
|
| H A D | LegalizeVectorOps.cpp | 315 case ISD::ADD: in LegalizeOp()
316 case ISD::SUB: in LegalizeOp()
317 case ISD::MUL: in LegalizeOp()
331 case ISD::AND: in LegalizeOp()
332 case ISD::OR: in LegalizeOp()
333 case ISD::XOR: in LegalizeOp()
334 case ISD::SHL: in LegalizeOp()
335 case ISD::SRA: in LegalizeOp()
336 case ISD::SRL: in LegalizeOp()
341 case ISD::ABS: in LegalizeOp()
[all …]
|
| H A D | LegalizeDAG.cpp | 749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
1711 ISD::ADD : ISD::SUB; in ExpandDYNAMIC_STACKALLOC()
2237 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3183 case ISD::SMAX: Pred = ISD::SETGT; break; in ExpandNode()
3184 case ISD::SMIN: Pred = ISD::SETLT; break; in ExpandNode()
3185 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
3186 case ISD::UMIN: Pred = ISD::SETULT; break; in ExpandNode()
3317 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI; in ExpandNode()
3332 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3460 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB; in ExpandNode()
[all …]
|
| H A D | LegalizeIntegerTypes.cpp | 924 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
1109 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_SADDSUBO()
1426 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_UADDSUBO()
2742 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; in ExpandShiftWithKnownAmountBit()
2744 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; in ExpandShiftWithKnownAmountBit()
2908 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY, in ExpandIntRes_ADDSUB()
3621 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT, in ExpandIntRes_LOAD()
4622 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
4648 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
4798 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
[all …]
|
| H A D | LegalizeFloatTypes.cpp | 2620 case ISD::FABS: in SoftPromoteHalfResult()
2623 case ISD::FCOS: in SoftPromoteHalfResult()
2624 case ISD::FEXP: in SoftPromoteHalfResult()
2627 case ISD::FLOG: in SoftPromoteHalfResult()
2631 case ISD::FNEG: in SoftPromoteHalfResult()
2636 case ISD::FSIN: in SoftPromoteHalfResult()
2642 case ISD::FADD: in SoftPromoteHalfResult()
2643 case ISD::FDIV: in SoftPromoteHalfResult()
2648 case ISD::FMUL: in SoftPromoteHalfResult()
2649 case ISD::FPOW: in SoftPromoteHalfResult()
[all …]
|
| H A D | LegalizeVectorTypes.cpp | 1061 case ISD::ADD: case ISD::VP_ADD: in SplitVectorResult()
1062 case ISD::SUB: case ISD::VP_SUB: in SplitVectorResult()
1063 case ISD::MUL: case ISD::VP_MUL: in SplitVectorResult()
1077 case ISD::AND: case ISD::VP_AND: in SplitVectorResult()
1078 case ISD::OR: case ISD::VP_OR: in SplitVectorResult()
1079 case ISD::XOR: case ISD::VP_XOR: in SplitVectorResult()
1080 case ISD::SHL: case ISD::VP_SHL: in SplitVectorResult()
1081 case ISD::SRA: case ISD::VP_ASHR: in SplitVectorResult()
1082 case ISD::SRL: case ISD::VP_LSHR: in SplitVectorResult()
1100 case ISD::FMA: case ISD::VP_FMA: in SplitVectorResult()
[all …]
|
| H A D | TargetLowering.cpp | 3993 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
4015 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; in simplifySetCCWithCTPOP()
4500 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; in SimplifySetCC()
4579 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
4599 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
4887 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; in SimplifySetCC()
7559 ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; in createSelectForFMINNUM_FMAXNUM()
9246 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in expandUADDSUBO()
9327 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in expandMULO()
9328 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; in expandMULO()
[all …]
|
| H A D | DAGCombiner.cpp | 1279 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteOperand()
1516 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteLoad()
5060 return CC == ISD::SETLT ? ISD::SMIN : (CC == ISD::SETGT ? ISD::SMAX : 0); in isSaturatingMinMax()
5075 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
6646 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
6651 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
6672 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { in isBSwapHWordElement()
11839 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
12781 ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD; in reduceLoadWidth()
16593 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
[all …]
|
| H A D | SelectionDAG.cpp | 476 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType()
479 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
491 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { in getSetCCSwappedOperands()
514 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, EVT Type) { in getSetCCInverse()
518 ISD::CondCode ISD::GlobalISel::getSetCCInverse(ISD::CondCode Op, in getSetCCInverse()
542 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
563 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
571 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
2350 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) in FoldSetCC()
8890 if (Opcode == ISD::FMUL || Opcode == ISD::FDIV) in simplifyFPBinop()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 241 if (ISD == ISD::MUL && in getArithmeticInstrCost()
253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
284 if (ISD == ISD::UDIV) in getArithmeticInstrCost()
814 ISD = ISD::MUL; in getArithmeticInstrCost()
1073 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || in getArithmeticInstrCost()
1074 ISD == ISD::UDIV || ISD == ISD::UREM)) { in getArithmeticInstrCost()
2593 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && in getCastInstrCost()
2610 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && in getCastInstrCost()
3327 ISD = ISD::ABS; in getTypeBasedIntrinsicInstrCost()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 296 setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS, in AMDGPUTargetLowering()
297 ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM, in AMDGPUTargetLowering()
334 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, VT, in AMDGPUTargetLowering()
360 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
368 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
396 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in AMDGPUTargetLowering()
397 ISD::FCEIL, ISD::FCOS, ISD::FDIV, ISD::FEXP2, in AMDGPUTargetLowering()
398 ISD::FEXP, ISD::FLOG2, ISD::FREM, ISD::FLOG, in AMDGPUTargetLowering()
399 ISD::FLOG10, ISD::FPOW, ISD::FFLOOR, ISD::FTRUNC, in AMDGPUTargetLowering()
400 ISD::FMUL, ISD::FMA, ISD::FRINT, ISD::FNEARBYINT, in AMDGPUTargetLowering()
[all …]
|
| H A D | R600ISelLowering.cpp | 49 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
57 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
60 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
86 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
87 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
88 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
91 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
103 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FRINT, ISD::FFLOOR}, in R600TargetLowering()
152 setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, MVT::i32, in R600TargetLowering()
186 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelDAGToDAG.cpp | 32 case ISD::SETEQ: in intCondCode2Icc()
34 case ISD::SETNE: in intCondCode2Icc()
36 case ISD::SETLT: in intCondCode2Icc()
38 case ISD::SETGT: in intCondCode2Icc()
40 case ISD::SETLE: in intCondCode2Icc()
42 case ISD::SETGE: in intCondCode2Icc()
62 case ISD::SETEQ: in fpCondCode2Fcc()
65 case ISD::SETNE: in fpCondCode2Fcc()
68 case ISD::SETLT: in fpCondCode2Fcc()
71 case ISD::SETGT: in fpCondCode2Fcc()
[all …]
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 84 namespace ISD {
1388 case ISD::LOAD:
1434 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||
1624 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1771 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1849 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
2495 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2639 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
3022 namespace ISD {
3096 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 599 if ((ISD == ISD::SIGN_EXTEND || ISD == ISD::ZERO_EXTEND) && in getCastInstrCost()
627 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 && in getCastInstrCost()
629 (ISD == ISD::FP_EXTEND && SrcTy.getScalarType() == MVT::f32 && in getCastInstrCost()
821 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
837 if (ISD == ISD::TRUNCATE && ST->hasMVEIntegerOps() && in getCastInstrCost()
919 if (CostKind == TTI::TCK_CodeSize && ISD == ISD::SELECT && in getCmpSelInstrCost()
1323 case ISD::AND: in getArithmeticInstrCost()
1324 case ISD::XOR: in getArithmeticInstrCost()
1326 case ISD::OR: in getArithmeticInstrCost()
1922 switch (ISD) { in maybeLoweredToCall()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 814 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
819 setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY, ISD::SETCCCARRY, in initActions()
824 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
829 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
862 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
863 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
864 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
865 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
887 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
888 ISD::FEXP2, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in initActions()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 342 case ISD::SRL: in LowerOperation()
979 case ISD::SHL: in LowerShifts()
984 case ISD::SRA: in LowerShifts()
985 case ISD::SRL: in LowerShifts()
1051 case ISD::SETEQ: in EmitCMP()
1058 case ISD::SETNE: in EmitCMP()
1065 case ISD::SETULE: in EmitCMP()
1093 case ISD::SETLE: in EmitCMP()
1096 case ISD::SETGE: in EmitCMP()
1107 case ISD::SETGT: in EmitCMP()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 389 setTargetDAGCombine({ISD::SPLAT_VECTOR, ISD::VSELECT}); in initializeHVXLowering()
1967 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
2068 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT || in LowerHvxConvertFpInt()
2069 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in LowerHvxConvertFpInt()
2072 if (Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT) { in LowerHvxConvertFpInt()
2151 uint64_t MemSize = (MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE) in SplitHvxMemOp()
2175 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
2413 case ISD::MUL: in LowerHvxOperation()
2422 case ISD::OR: in LowerHvxOperation()
2457 case ISD::SRA: in LowerHvxOperation()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 206 setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL}, in RISCVTargetLowering()
229 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, in RISCVTargetLowering()
311 ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in RISCVTargetLowering()
312 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, in RISCVTargetLowering()
313 ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO}; in RISCVTargetLowering()
316 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in RISCVTargetLowering()
641 ISD::SETO, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in RISCVTargetLowering()
642 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO, in RISCVTargetLowering()
643 ISD::SETGT, ISD::SETOGT, ISD::SETGE, ISD::SETOGE, in RISCVTargetLowering()
824 setOperationAction({ISD::ADD, ISD::MUL, ISD::SUB, ISD::AND, ISD::OR, in RISCVTargetLowering()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 85 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
98 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
104 for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) in M68kTargetLowering()
256 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
1760 case ISD::OR: in EmitTest()
1927 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1938 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2234 if (Opc != ISD::OR && Opc != ISD::AND) in isAndOrOfSetCCs()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 47 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT, in LoongArchTargetLowering()
68 static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE, in LoongArchTargetLowering()
123 case ISD::SHL: in LowerOperation()
124 case ISD::SRA: in LowerOperation()
125 case ISD::SRL: in LowerOperation()
294 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
328 case ISD::SHL: in getLoongArchWOpcode()
330 case ISD::SRA: in getLoongArchWOpcode()
332 case ISD::SRL: in getLoongArchWOpcode()
359 case ISD::SHL: in ReplaceNodeResults()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1480 case ISD::SETEQ: in FPCondCCodeToFCC()
1482 case ISD::SETNE: in FPCondCCodeToFCC()
1484 case ISD::SETLT: in FPCondCCodeToFCC()
1486 case ISD::SETGT: in FPCondCCodeToFCC()
2807 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
3016 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3018 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3168 case ISD::FABS: in LowerOperation()
3172 case ISD::ADDC: in LowerOperation()
3173 case ISD::ADDE: in LowerOperation()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 604 {ISD::SELECT, ISD::SELECT_CC, ISD::SETCC, in AArch64TargetLowering()
605 ISD::BR_CC, ISD::FADD, ISD::FSUB, in AArch64TargetLowering()
606 ISD::FMUL, ISD::FDIV, ISD::FMA, in AArch64TargetLowering()
875 setTargetDAGCombine({ISD::ADD, ISD::ABS, ISD::SUB, ISD::XOR, ISD::SINT_TO_FP, in AArch64TargetLowering()
955 ISD::FMUL, ISD::FDIV, ISD::FMA, in AArch64TargetLowering()
970 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP, in AArch64TargetLowering()
971 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1104 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1105 ISD::FROUND, ISD::FROUNDEVEN, ISD::STRICT_FFLOOR, in AArch64TargetLowering()
1517 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 141 setTargetDAGCombine({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR}); in LanaiTargetLowering()
174 case ISD::MUL: in LowerOperation()
176 case ISD::BR_CC: in LowerOperation()
188 case ISD::SETCC: in LowerOperation()
815 case ISD::SETEQ: in IntCondCCodeToICC()
863 case ISD::SETO: in IntCondCCodeToICC()
1479 case ISD::ADD: in PerformDAGCombine()
1480 case ISD::OR: in PerformDAGCombine()
1481 case ISD::XOR: in PerformDAGCombine()
1483 case ISD::AND: in PerformDAGCombine()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 61 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in AVRTargetLowering()
285 case ISD::SHL: in LowerShifts()
315 case ISD::SRA: in LowerShifts()
318 case ISD::ROTL: in LowerShifts()
322 case ISD::ROTR: in LowerShifts()
326 case ISD::SRL: in LowerShifts()
329 case ISD::SHL: in LowerShifts()
472 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
843 case ISD::SHL: in LowerOperation()
844 case ISD::SRA: in LowerOperation()
[all …]
|