Lines Matching refs:ISD
47 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT, in LoongArchTargetLowering()
51 setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom); in LoongArchTargetLowering()
52 setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom); in LoongArchTargetLowering()
53 setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom); in LoongArchTargetLowering()
54 setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom); in LoongArchTargetLowering()
56 setOperationAction({ISD::GlobalAddress, ISD::ConstantPool}, GRLenVT, Custom); in LoongArchTargetLowering()
59 setOperationAction(ISD::SHL, MVT::i32, Custom); in LoongArchTargetLowering()
60 setOperationAction(ISD::SRA, MVT::i32, Custom); in LoongArchTargetLowering()
61 setOperationAction(ISD::SRL, MVT::i32, Custom); in LoongArchTargetLowering()
62 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in LoongArchTargetLowering()
63 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in LoongArchTargetLowering()
65 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in LoongArchTargetLowering()
68 static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE, in LoongArchTargetLowering()
69 ISD::SETUGT, ISD::SETUGE}; in LoongArchTargetLowering()
73 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in LoongArchTargetLowering()
77 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in LoongArchTargetLowering()
78 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in LoongArchTargetLowering()
79 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in LoongArchTargetLowering()
82 setOperationAction(ISD::BR_CC, GRLenVT, Expand); in LoongArchTargetLowering()
83 setOperationAction(ISD::SELECT_CC, GRLenVT, Expand); in LoongArchTargetLowering()
84 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LoongArchTargetLowering()
85 setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, GRLenVT, Expand); in LoongArchTargetLowering()
89 setOperationAction(ISD::FP_TO_UINT, GRLenVT, Custom); in LoongArchTargetLowering()
90 setOperationAction(ISD::UINT_TO_FP, GRLenVT, Custom); in LoongArchTargetLowering()
105 setTargetDAGCombine(ISD::AND); in LoongArchTargetLowering()
106 setTargetDAGCombine(ISD::OR); in LoongArchTargetLowering()
107 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
115 case ISD::GlobalAddress: in LowerOperation()
117 case ISD::SHL_PARTS: in LowerOperation()
119 case ISD::SRA_PARTS: in LowerOperation()
121 case ISD::SRL_PARTS: in LowerOperation()
123 case ISD::SHL: in LowerOperation()
124 case ISD::SRA: in LowerOperation()
125 case ISD::SRL: in LowerOperation()
130 case ISD::ConstantPool: in LowerOperation()
132 case ISD::FP_TO_SINT: in LowerOperation()
134 case ISD::BITCAST: in LowerOperation()
136 case ISD::FP_TO_UINT: in LowerOperation()
138 case ISD::UINT_TO_FP: in LowerOperation()
150 if (Op1->getOpcode() == ISD::AssertZext || in lowerUINT_TO_FP()
151 Op1->getOpcode() == ISD::AssertSext) in lowerUINT_TO_FP()
153 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op.getOperand(0)); in lowerUINT_TO_FP()
154 SDValue Res = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f64, Trunc); in lowerUINT_TO_FP()
168 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in lowerBITCAST()
188 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Trunc); in lowerFP_TO_SINT()
249 SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen); in lowerShiftLeftParts()
250 SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1); in lowerShiftLeftParts()
252 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
253 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in lowerShiftLeftParts()
255 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt); in lowerShiftLeftParts()
256 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in lowerShiftLeftParts()
257 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); in lowerShiftLeftParts()
258 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusGRLen); in lowerShiftLeftParts()
260 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT); in lowerShiftLeftParts()
262 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); in lowerShiftLeftParts()
263 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in lowerShiftLeftParts()
294 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
300 SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen); in lowerShiftRightParts()
301 SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1); in lowerShiftRightParts()
303 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
304 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); in lowerShiftRightParts()
306 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, GRLenMinus1Shamt); in lowerShiftRightParts()
307 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi); in lowerShiftRightParts()
311 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, GRLenMinus1) : Zero; in lowerShiftRightParts()
313 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT); in lowerShiftRightParts()
315 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); in lowerShiftRightParts()
316 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in lowerShiftRightParts()
328 case ISD::SHL: in getLoongArchWOpcode()
330 case ISD::SRA: in getLoongArchWOpcode()
332 case ISD::SRL: in getLoongArchWOpcode()
343 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp()
350 return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); in customLegalizeToWOp()
359 case ISD::SHL: in ReplaceNodeResults()
360 case ISD::SRA: in ReplaceNodeResults()
361 case ISD::SRL: in ReplaceNodeResults()
364 if (N->getOperand(1).getOpcode() != ISD::Constant) { in ReplaceNodeResults()
369 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
375 Results.push_back(DAG.getNode(ISD::BITCAST, DL, N->getValueType(0), Dst)); in ReplaceNodeResults()
378 case ISD::BITCAST: { in ReplaceNodeResults()
386 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Dst)); in ReplaceNodeResults()
390 case ISD::FP_TO_UINT: { in ReplaceNodeResults()
396 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1)); in ReplaceNodeResults()
424 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
487 if (FirstOperand.getOpcode() != ISD::AND || in performSRLCombine()
531 if (N0.getOpcode() == ISD::AND && in performORCombine()
534 N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL && in performORCombine()
553 if (N0.getOpcode() == ISD::AND && in performORCombine()
556 N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::AND && in performORCombine()
576 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in performORCombine()
584 DAG.getNode(ISD::SRL, DL, N1->getValueType(0), N1, in performORCombine()
599 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::SHL && in performORCombine()
618 if (N0.getOpcode() == ISD::AND && in performORCombine()
642 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::AND && in performORCombine()
666 if (N1.getOpcode() == ISD::AND && in performORCombine()
669 N1.getOperand(0).getOpcode() == ISD::SHL && in performORCombine()
700 if (N1.getOpcode() == ISD::AND && in performORCombine()
707 DAG.getNode(ISD::SRL, DL, N1->getValueType(0), in performORCombine()
730 case ISD::AND: in PerformDAGCombine()
732 case ISD::OR: in PerformDAGCombine()
734 case ISD::SRL: in PerformDAGCombine()
850 CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins, in analyzeInputArgs()
864 CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs, in analyzeOutputArgs()
893 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
924 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
926 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
1045 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn()
1053 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()