Lines Matching refs:ISD
547 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
551 case ISD::ATOMIC_SWAP: { in getOUTLINE_ATOMIC()
555 case ISD::ATOMIC_LOAD_ADD: { in getOUTLINE_ATOMIC()
559 case ISD::ATOMIC_LOAD_OR: { in getOUTLINE_ATOMIC()
563 case ISD::ATOMIC_LOAD_CLR: { in getOUTLINE_ATOMIC()
567 case ISD::ATOMIC_LOAD_XOR: { in getOUTLINE_ATOMIC()
597 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) in getSYNC()
598 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
599 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) in getSYNC()
600 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) in getSYNC()
601 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) in getSYNC()
602 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) in getSYNC()
603 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) in getSYNC()
604 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) in getSYNC()
605 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) in getSYNC()
606 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) in getSYNC()
607 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) in getSYNC()
608 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) in getSYNC()
668 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { in InitCmpLibcallCCs()
669 std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID); in InitCmpLibcallCCs()
670 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
671 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
672 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
673 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
674 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
675 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
676 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
677 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
678 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
679 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
680 CCs[RTLIB::OGE_F128] = ISD::SETGE; in InitCmpLibcallCCs()
681 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; in InitCmpLibcallCCs()
682 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
683 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
684 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
685 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in InitCmpLibcallCCs()
686 CCs[RTLIB::OLE_F32] = ISD::SETLE; in InitCmpLibcallCCs()
687 CCs[RTLIB::OLE_F64] = ISD::SETLE; in InitCmpLibcallCCs()
688 CCs[RTLIB::OLE_F128] = ISD::SETLE; in InitCmpLibcallCCs()
689 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; in InitCmpLibcallCCs()
690 CCs[RTLIB::OGT_F32] = ISD::SETGT; in InitCmpLibcallCCs()
691 CCs[RTLIB::OGT_F64] = ISD::SETGT; in InitCmpLibcallCCs()
692 CCs[RTLIB::OGT_F128] = ISD::SETGT; in InitCmpLibcallCCs()
693 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; in InitCmpLibcallCCs()
694 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
695 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
696 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
697 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
749 for (ISD::NodeType NT : enum_seq(ISD::DELETED_NODE, ISD::BUILTIN_OP_END, in initActions()
757 setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand); in initActions()
758 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand); in initActions()
761 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
762 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { in initActions()
774 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); in initActions()
775 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
782 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
783 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { in initActions()
791 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
794 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
795 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
796 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, in initActions()
797 ISD::FMINIMUM, ISD::FMAXIMUM, in initActions()
798 ISD::FMAD, ISD::SMIN, in initActions()
799 ISD::SMAX, ISD::UMIN, in initActions()
800 ISD::UMAX, ISD::ABS, in initActions()
801 ISD::FSHL, ISD::FSHR, in initActions()
802 ISD::SADDSAT, ISD::UADDSAT, in initActions()
803 ISD::SSUBSAT, ISD::USUBSAT, in initActions()
804 ISD::SSHLSAT, ISD::USHLSAT, in initActions()
805 ISD::SMULFIX, ISD::SMULFIXSAT, in initActions()
806 ISD::UMULFIX, ISD::UMULFIXSAT, in initActions()
807 ISD::SDIVFIX, ISD::SDIVFIXSAT, in initActions()
808 ISD::UDIVFIX, ISD::UDIVFIXSAT, in initActions()
809 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
810 ISD::IS_FPCLASS}, in initActions()
814 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
815 ISD::SMULO, ISD::UMULO}, in initActions()
819 setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY, ISD::SETCCCARRY, in initActions()
820 ISD::SADDO_CARRY, ISD::SSUBO_CARRY}, in initActions()
824 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
829 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
833 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
836 setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in initActions()
839 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); in initActions()
842 setOperationAction({ISD::FROUND, ISD::FROUNDEVEN, ISD::FPOWI}, VT, Expand); in initActions()
846 setOperationAction({ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, in initActions()
847 ISD::ANY_EXTEND_VECTOR_INREG, in initActions()
848 ISD::SIGN_EXTEND_VECTOR_INREG, in initActions()
849 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR}, in initActions()
854 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); in initActions()
858 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); in initActions()
862 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
863 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
864 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
865 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
866 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL}, in initActions()
870 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
874 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); in initActions()
877 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); in initActions()
882 setOperationAction(ISD::ConstantFP, in initActions()
887 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
888 ISD::FEXP2, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in initActions()
889 ISD::FRINT, ISD::FTRUNC, ISD::LROUND, ISD::LLROUND, in initActions()
890 ISD::LRINT, ISD::LLRINT}, in initActions()
894 setOperationAction(ISD::TRAP, MVT::Other, Expand); in initActions()
898 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); in initActions()
900 setOperationAction(ISD::UBSANTRAP, MVT::Other, Expand); in initActions()
929 case ISD::SDIV: in canOpTrap()
930 case ISD::UDIV: in canOpTrap()
931 case ISD::SREM: in canOpTrap()
932 case ISD::UREM: in canOpTrap()
1655 SmallVectorImpl<ISD::OutputArg> &Outs, in GetReturnInfo()
1664 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in GetReturnInfo()
1667 ExtendKind = ISD::SIGN_EXTEND; in GetReturnInfo()
1669 ExtendKind = ISD::ZERO_EXTEND; in GetReturnInfo()
1675 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1687 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); in GetReturnInfo()
1698 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
1787 case FNeg: return ISD::FNEG; in InstructionOpcodeToISD()
1788 case Add: return ISD::ADD; in InstructionOpcodeToISD()
1789 case FAdd: return ISD::FADD; in InstructionOpcodeToISD()
1790 case Sub: return ISD::SUB; in InstructionOpcodeToISD()
1791 case FSub: return ISD::FSUB; in InstructionOpcodeToISD()
1792 case Mul: return ISD::MUL; in InstructionOpcodeToISD()
1793 case FMul: return ISD::FMUL; in InstructionOpcodeToISD()
1794 case UDiv: return ISD::UDIV; in InstructionOpcodeToISD()
1795 case SDiv: return ISD::SDIV; in InstructionOpcodeToISD()
1796 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
1797 case URem: return ISD::UREM; in InstructionOpcodeToISD()
1798 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
1799 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
1800 case Shl: return ISD::SHL; in InstructionOpcodeToISD()
1801 case LShr: return ISD::SRL; in InstructionOpcodeToISD()
1802 case AShr: return ISD::SRA; in InstructionOpcodeToISD()
1803 case And: return ISD::AND; in InstructionOpcodeToISD()
1804 case Or: return ISD::OR; in InstructionOpcodeToISD()
1805 case Xor: return ISD::XOR; in InstructionOpcodeToISD()
1807 case Load: return ISD::LOAD; in InstructionOpcodeToISD()
1808 case Store: return ISD::STORE; in InstructionOpcodeToISD()
1813 case Trunc: return ISD::TRUNCATE; in InstructionOpcodeToISD()
1814 case ZExt: return ISD::ZERO_EXTEND; in InstructionOpcodeToISD()
1815 case SExt: return ISD::SIGN_EXTEND; in InstructionOpcodeToISD()
1816 case FPToUI: return ISD::FP_TO_UINT; in InstructionOpcodeToISD()
1817 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()
1818 case UIToFP: return ISD::UINT_TO_FP; in InstructionOpcodeToISD()
1819 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
1820 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
1821 case FPExt: return ISD::FP_EXTEND; in InstructionOpcodeToISD()
1822 case PtrToInt: return ISD::BITCAST; in InstructionOpcodeToISD()
1823 case IntToPtr: return ISD::BITCAST; in InstructionOpcodeToISD()
1824 case BitCast: return ISD::BITCAST; in InstructionOpcodeToISD()
1825 case AddrSpaceCast: return ISD::ADDRSPACECAST; in InstructionOpcodeToISD()
1826 case ICmp: return ISD::SETCC; in InstructionOpcodeToISD()
1827 case FCmp: return ISD::SETCC; in InstructionOpcodeToISD()
1830 case Select: return ISD::SELECT; in InstructionOpcodeToISD()
1834 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; in InstructionOpcodeToISD()
1835 case InsertElement: return ISD::INSERT_VECTOR_ELT; in InstructionOpcodeToISD()
1836 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
1837 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1838 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1840 case Freeze: return ISD::FREEZE; in InstructionOpcodeToISD()