Lines Matching refs:ISD
52 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in AVRTargetLowering()
53 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); in AVRTargetLowering()
55 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in AVRTargetLowering()
56 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in AVRTargetLowering()
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); in AVRTargetLowering()
58 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); in AVRTargetLowering()
61 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in AVRTargetLowering()
70 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
71 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
72 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
73 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
78 setOperationAction(ISD::ADD, MVT::i32, Custom); in AVRTargetLowering()
79 setOperationAction(ISD::ADD, MVT::i64, Custom); in AVRTargetLowering()
83 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
84 setOperationAction(ISD::SHL, MVT::i8, Custom); in AVRTargetLowering()
85 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
86 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
87 setOperationAction(ISD::SHL, MVT::i16, Custom); in AVRTargetLowering()
88 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
89 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); in AVRTargetLowering()
90 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); in AVRTargetLowering()
91 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); in AVRTargetLowering()
93 setOperationAction(ISD::ROTL, MVT::i8, Custom); in AVRTargetLowering()
94 setOperationAction(ISD::ROTL, MVT::i16, Expand); in AVRTargetLowering()
95 setOperationAction(ISD::ROTR, MVT::i8, Custom); in AVRTargetLowering()
96 setOperationAction(ISD::ROTR, MVT::i16, Expand); in AVRTargetLowering()
98 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in AVRTargetLowering()
99 setOperationAction(ISD::BR_CC, MVT::i16, Custom); in AVRTargetLowering()
100 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AVRTargetLowering()
101 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AVRTargetLowering()
102 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in AVRTargetLowering()
104 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in AVRTargetLowering()
105 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in AVRTargetLowering()
106 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in AVRTargetLowering()
107 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AVRTargetLowering()
108 setOperationAction(ISD::SETCC, MVT::i8, Custom); in AVRTargetLowering()
109 setOperationAction(ISD::SETCC, MVT::i16, Custom); in AVRTargetLowering()
110 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AVRTargetLowering()
111 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AVRTargetLowering()
112 setOperationAction(ISD::SELECT, MVT::i8, Expand); in AVRTargetLowering()
113 setOperationAction(ISD::SELECT, MVT::i16, Expand); in AVRTargetLowering()
115 setOperationAction(ISD::BSWAP, MVT::i16, Expand); in AVRTargetLowering()
118 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
119 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
121 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
122 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
123 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
125 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
127 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AVRTargetLowering()
129 setOperationAction(ISD::VASTART, MVT::Other, Custom); in AVRTargetLowering()
130 setOperationAction(ISD::VAEND, MVT::Other, Expand); in AVRTargetLowering()
131 setOperationAction(ISD::VAARG, MVT::Other, Expand); in AVRTargetLowering()
132 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in AVRTargetLowering()
136 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); in AVRTargetLowering()
137 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); in AVRTargetLowering()
138 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); in AVRTargetLowering()
139 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); in AVRTargetLowering()
140 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); in AVRTargetLowering()
141 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); in AVRTargetLowering()
142 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); in AVRTargetLowering()
146 setOperationAction(ISD::UDIV, MVT::i8, Expand); in AVRTargetLowering()
147 setOperationAction(ISD::UDIV, MVT::i16, Expand); in AVRTargetLowering()
148 setOperationAction(ISD::UREM, MVT::i8, Expand); in AVRTargetLowering()
149 setOperationAction(ISD::UREM, MVT::i16, Expand); in AVRTargetLowering()
150 setOperationAction(ISD::SDIV, MVT::i8, Expand); in AVRTargetLowering()
151 setOperationAction(ISD::SDIV, MVT::i16, Expand); in AVRTargetLowering()
152 setOperationAction(ISD::SREM, MVT::i8, Expand); in AVRTargetLowering()
153 setOperationAction(ISD::SREM, MVT::i16, Expand); in AVRTargetLowering()
156 setOperationAction(ISD::UDIVREM, MVT::i8, Custom); in AVRTargetLowering()
157 setOperationAction(ISD::UDIVREM, MVT::i16, Custom); in AVRTargetLowering()
158 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AVRTargetLowering()
159 setOperationAction(ISD::SDIVREM, MVT::i8, Custom); in AVRTargetLowering()
160 setOperationAction(ISD::SDIVREM, MVT::i16, Custom); in AVRTargetLowering()
161 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in AVRTargetLowering()
164 setOperationAction(ISD::MUL, MVT::i8, Expand); in AVRTargetLowering()
165 setOperationAction(ISD::MUL, MVT::i16, Expand); in AVRTargetLowering()
168 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); in AVRTargetLowering()
169 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); in AVRTargetLowering()
174 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); in AVRTargetLowering()
175 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); in AVRTargetLowering()
179 setOperationAction(ISD::MULHS, VT, Expand); in AVRTargetLowering()
180 setOperationAction(ISD::MULHU, VT, Expand); in AVRTargetLowering()
184 setOperationAction(ISD::CTPOP, VT, Expand); in AVRTargetLowering()
185 setOperationAction(ISD::CTLZ, VT, Expand); in AVRTargetLowering()
186 setOperationAction(ISD::CTTZ, VT, Expand); in AVRTargetLowering()
190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in AVRTargetLowering()
285 case ISD::SHL: in LowerShifts()
288 case ISD::SRL: in LowerShifts()
291 case ISD::ROTL: { in LowerShifts()
294 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, in LowerShifts()
298 case ISD::ROTR: { in LowerShifts()
301 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, in LowerShifts()
305 case ISD::SRA: in LowerShifts()
315 case ISD::SRA: in LowerShifts()
318 case ISD::ROTL: in LowerShifts()
322 case ISD::ROTR: in LowerShifts()
326 case ISD::SRL: in LowerShifts()
329 case ISD::SHL: in LowerShifts()
338 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
342 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT)); in LowerShifts()
344 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
349 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT)); in LowerShifts()
351 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { in LowerShifts()
356 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { in LowerShifts()
361 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) { in LowerShifts()
366 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { in LowerShifts()
373 if (Op.getOpcode() == ISD::SRA) in LowerShifts()
396 case ISD::SHL: in LowerShifts()
401 case ISD::SRL: in LowerShifts()
411 case ISD::SHL: in LowerShifts()
418 case ISD::SRL: in LowerShifts()
425 case ISD::SRA: in LowerShifts()
437 case ISD::SHL: in LowerShifts()
444 case ISD::SRL: in LowerShifts()
451 case ISD::SRA: in LowerShifts()
472 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
474 bool IsSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
547 static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) { in intCCToAVRCC()
551 case ISD::SETEQ: in intCCToAVRCC()
553 case ISD::SETNE: in intCCToAVRCC()
555 case ISD::SETGE: in intCCToAVRCC()
557 case ISD::SETLT: in intCCToAVRCC()
559 case ISD::SETUGE: in intCCToAVRCC()
561 case ISD::SETULT: in intCCToAVRCC()
579 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, in getAVRCmp()
581 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, in getAVRCmp()
583 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, in getAVRCmp()
585 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, in getAVRCmp()
599 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, in getAVRCmp()
609 case ISD::SETLE: { in getAVRCmp()
612 CC = ISD::SETGE; in getAVRCmp()
615 case ISD::SETGT: { in getAVRCmp()
630 CC = ISD::SETLT; in getAVRCmp()
637 CC = ISD::SETGE; in getAVRCmp()
645 CC = ISD::SETLT; in getAVRCmp()
648 case ISD::SETLT: { in getAVRCmp()
656 CC = ISD::SETGE; in getAVRCmp()
670 case ISD::SETULE: { in getAVRCmp()
673 CC = ISD::SETUGE; in getAVRCmp()
676 case ISD::SETUGT: { in getAVRCmp()
681 CC = ISD::SETUGE; in getAVRCmp()
686 CC = ISD::SETULT; in getAVRCmp()
694 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, in getAVRCmp()
696 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, in getAVRCmp()
698 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, in getAVRCmp()
700 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, in getAVRCmp()
705 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi, in getAVRCmp()
713 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, in getAVRCmp()
715 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, in getAVRCmp()
718 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp()
720 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp()
722 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, in getAVRCmp()
724 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, in getAVRCmp()
727 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, in getAVRCmp()
729 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, in getAVRCmp()
732 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp()
734 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp()
736 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, in getAVRCmp()
738 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, in getAVRCmp()
743 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3, in getAVRCmp()
758 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, in getAVRCmp()
777 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
795 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
810 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
843 case ISD::SHL: in LowerOperation()
844 case ISD::SRA: in LowerOperation()
845 case ISD::SRL: in LowerOperation()
846 case ISD::ROTL: in LowerOperation()
847 case ISD::ROTR: in LowerOperation()
849 case ISD::GlobalAddress: in LowerOperation()
851 case ISD::BlockAddress: in LowerOperation()
853 case ISD::BR_CC: in LowerOperation()
855 case ISD::SELECT_CC: in LowerOperation()
857 case ISD::SETCC: in LowerOperation()
859 case ISD::VASTART: in LowerOperation()
861 case ISD::SDIVREM: in LowerOperation()
862 case ISD::UDIVREM: in LowerOperation()
877 case ISD::ADD: { in ReplaceNodeResults()
881 ISD::SUB, DL, N->getValueType(0), N->getOperand(0), in ReplaceNodeResults()
932 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
941 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPreIndexedAddressParts()
960 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { in getPreIndexedAddressParts()
966 if (Op->getOpcode() == ISD::SUB) in getPreIndexedAddressParts()
975 AM = ISD::PRE_DEC; in getPreIndexedAddressParts()
989 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
996 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPostIndexedAddressParts()
1011 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { in getPostIndexedAddressParts()
1017 if (Op->getOpcode() == ISD::SUB) in getPostIndexedAddressParts()
1025 AM = ISD::POST_INC; in getPostIndexedAddressParts()
1212 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments()
1261 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
1264 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
1269 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1271 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
1314 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
1316 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
1379 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1382 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1385 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1388 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); in LowerCall()
1420 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerCall()
1430 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall()
1487 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
1520 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn()
1534 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()