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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1 |
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| #
bce2e208 |
| 26-Mar-2022 |
Ben Shi <[email protected]> |
[AVR] Optimize int16 airthmetic right shift for shift amount 7/14/15
Reviewed By: aykevl
Differential Revision: https://reviews.llvm.org/D115618
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| #
f319c245 |
| 14-Mar-2022 |
Ben Shi <[email protected]> |
[AVR] Reject/Reserve R0~R15 on AVRTiny.
Reviewed By: aykevl, dylanmckay
Differential Revision: https://reviews.llvm.org/D121672
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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| #
fa2d31e9 |
| 10-Feb-2022 |
Ben Shi <[email protected]> |
[AVR] Fix a potential assert failure
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D119416
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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| #
31666478 |
| 19-Jan-2022 |
Ayke van Laethem <[email protected]> |
[AVR] Fix atomicrmw result value
This patch fixes the atomicrmw result value to be the value before the
operation instead of the value after the operation. This was a bug, left
as a FIXME in the cod
[AVR] Fix atomicrmw result value
This patch fixes the atomicrmw result value to be the value before the
operation instead of the value after the operation. This was a bug, left
as a FIXME in the code (see https://reviews.llvm.org/D97127).
From the LangRef:
> The contents of memory at the location specified by the <pointer>
> operand are atomically read, modified, and written back. The original
> value at the location is returned.
Doing this expansion early allows the register allocator to arrange
registers in such a way that commutable operations are simply swapped
around as needed, which results in shorter code while still being
correct.
Differential Revision: https://reviews.llvm.org/D117725
show more ...
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| #
f15014ff |
| 26-Jan-2022 |
Benjamin Kramer <[email protected]> |
Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"
This reverts commit ef8206320769ad31422a803a0d6de6077fd231d2.
- It conflicts with the existing llvm::size in STLEx
Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"
This reverts commit ef8206320769ad31422a803a0d6de6077fd231d2.
- It conflicts with the existing llvm::size in STLExtras, which will now
never be called.
- Calling it without llvm:: breaks C++17 compat
show more ...
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| #
ef820632 |
| 26-Jan-2022 |
serge-sans-paille <[email protected]> |
Rename llvm::array_lengthof into llvm::size to match std::size from C++17
As a conquence move llvm::array_lengthof from STLExtras.h to
STLForwardCompat.h (which is included by STLExtras.h so no buil
Rename llvm::array_lengthof into llvm::size to match std::size from C++17
As a conquence move llvm::array_lengthof from STLExtras.h to
STLForwardCompat.h (which is included by STLExtras.h so no build
breakage expected).
show more ...
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| #
116ab786 |
| 16-Jan-2022 |
Ayke van Laethem <[email protected]> |
[AVR] Make use of the constant value 0 in R1
The register R1 is defined to have the constant value 0 in the avr-gcc
calling convention (which we follow). Unfortunately, we don't really
make use of i
[AVR] Make use of the constant value 0 in R1
The register R1 is defined to have the constant value 0 in the avr-gcc
calling convention (which we follow). Unfortunately, we don't really
make use of it. This patch replaces `LDI 0` instructions with a copy
from R1.
This reduces code size: my AVR build of compiler-rt goes from 50660 to
50240 bytes of code size, which is a 0.8% reduction. Presumably it will
also improve execution speed, although I didn't measure this.
Differential Revision: https://reviews.llvm.org/D117425
show more ...
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| #
d6b07348 |
| 19-Jan-2022 |
Jim Lin <[email protected]> |
[NFC] Use Register instead of unsigned
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Revision tags: llvmorg-13.0.1-rc2 |
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| #
99e7bf46 |
| 04-Jan-2022 |
Ben Shi <[email protected]> |
[AVR] Optimize int16 shift operation for shift amount greater than 8
Skip operation on the lower byte in int16 logical left shift when
shift amount is greater than 8.
Skip operation on the higher b
[AVR] Optimize int16 shift operation for shift amount greater than 8
Skip operation on the lower byte in int16 logical left shift when
shift amount is greater than 8.
Skip operation on the higher byte in int16 logical & arithmetic
right shift when shift amount is greater than 8.
Reviewed By: aykevl
Differential Revision: https://reviews.llvm.org/D115594
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| #
f4ef7930 |
| 04-Jan-2022 |
Ben Shi <[email protected]> |
[AVR] Optimize int8 arithmetic right shift 6 bits
Reviewed By: aykevl
Differential Revision: https://reviews.llvm.org/D115593
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| #
9fb4e79d |
| 04-Jan-2022 |
Ben Shi <[email protected]> |
Revert "[AVR] Optimize int8 arithmetic right shift 6 bits"
This reverts commit 5723261370b45fa4d0d295845c6ef9e223f2ff4a.
There are failures as reported in
https://lab.llvm.org/buildbot#builders/16
Revert "[AVR] Optimize int8 arithmetic right shift 6 bits"
This reverts commit 5723261370b45fa4d0d295845c6ef9e223f2ff4a.
There are failures as reported in
https://lab.llvm.org/buildbot#builders/16/builds/21638
https://lab.llvm.org/buildbot#builders/104/builds/5394
show more ...
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| #
57232613 |
| 04-Jan-2022 |
Ben Shi <[email protected]> |
[AVR] Optimize int8 arithmetic right shift 6 bits
Reviewed By: aykevl
Differential Revision: https://reviews.llvm.org/D115593
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| #
69ccc961 |
| 01-Jan-2022 |
Kazu Hirata <[email protected]> |
[llvm] Use the default constructor for SDValue (NFC)
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| #
5a667c0e |
| 28-Dec-2021 |
Kazu Hirata <[email protected]> |
[llvm] Use nullptr instead of 0 (NFC)
Identified with modernize-use-nullptr.
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Revision tags: llvmorg-13.0.1-rc1 |
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| #
5b8bbbec |
| 18-Nov-2021 |
Zarko Todorovski <[email protected]> |
[NFC][llvm] Inclusive language: reword and remove uses of sanity in llvm/lib/Target
Reworded removed code comments that contain `sanity check` and `sanity
test`.
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3 |
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| #
5449d2da |
| 04-Sep-2021 |
Shivam Gupta <[email protected]> |
[NFC] Run clang-format on llvm/lib/Trget/AVR/
The current inconsistency confuse contributors which coding guidlines to follow.
It would be better to have it consistent using clang-format tool.
Revi
[NFC] Run clang-format on llvm/lib/Trget/AVR/
The current inconsistency confuse contributors which coding guidlines to follow.
It would be better to have it consistent using clang-format tool.
Reviewed By: mhjacobson
Differential Revision: https://reviews.llvm.org/D109270
show more ...
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Revision tags: llvmorg-13.0.0-rc2 |
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| #
d7593eba |
| 13-Aug-2021 |
Arthur Eubanks <[email protected]> |
[NFC] Clean up users of AttributeList::hasAttribute()
AttributeList::hasAttribute() is confusing, use clearer methods like
hasParamAttr()/hasRetAttr().
Add hasRetAttr() since it was missing from At
[NFC] Clean up users of AttributeList::hasAttribute()
AttributeList::hasAttribute() is confusing, use clearer methods like
hasParamAttr()/hasRetAttr().
Add hasRetAttr() since it was missing from AttributeList.
show more ...
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Revision tags: llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2 |
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| #
4d7f5c0a |
| 18-Feb-2021 |
Ayke van Laethem <[email protected]> |
[AVR] Only support sp, r0 and r1 in llvm.read_register
Most other registers are allocatable and therefore cannot be used.
This issue was flagged by the machine verifier, because reading other
regis
[AVR] Only support sp, r0 and r1 in llvm.read_register
Most other registers are allocatable and therefore cannot be used.
This issue was flagged by the machine verifier, because reading other
registers is considered reading from an undefined register.
Differential Revision: https://reviews.llvm.org/D96969
show more ...
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| #
feda08b7 |
| 03-Mar-2021 |
Ayke van Laethem <[email protected]> |
[AVR] Do not chain stores in call frame setup
Previously, AVRTargetLowering::LowerCall attempted to keep stack stores
in order with chains. Perhaps this worked in the past, but it does not
work now:
[AVR] Do not chain stores in call frame setup
Previously, AVRTargetLowering::LowerCall attempted to keep stack stores
in order with chains. Perhaps this worked in the past, but it does not
work now: it appears that the SelectionDAG legalization phase removes
these chains. Therefore, I've removed these chains entirely to match
X86 (which, similar to AVR, also prefers to use push instructions over
stack-relative stores to set up a call frame). With this change, all the
stack stores are in a somewhat reasonable order.
Differential Revision: https://reviews.llvm.org/D97853
show more ...
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| #
22668c6e |
| 31-May-2021 |
Ben Shi <[email protected]> |
[AVR][NFC] Refactor 8-bit & 16-bit shifts
Reviewed By: dylanmckay
Differential Revision: https://reviews.llvm.org/D98335
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| #
86812faa |
| 30-May-2021 |
Ben Shi <[email protected]> |
[AVR] Improve inline assembly
Reviewed By: dylanmckay
Differential Revision: https://reviews.llvm.org/D96394
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| #
83e2710e |
| 04-Feb-2021 |
Dylan McKay <[email protected]> |
[AVR] Remove an assertion that causes generic CodeGen tests to fail
It was discussed a few years ago and agreed that it makes sense to
remove this assertion as other targets do not perform similar r
[AVR] Remove an assertion that causes generic CodeGen tests to fail
It was discussed a few years ago and agreed that it makes sense to
remove this assertion as other targets do not perform similar register
size checking in inline assembly constraint logic, so the check just
adds a needless barrier on AVR.
This patch removes the assertion and removes 'XFAIL' from two Generic
CodeGen tests for AVR as a result.
show more ...
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Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3 |
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| #
8ed16361 |
| 30-Jan-2021 |
Kazu Hirata <[email protected]> |
[llvm] Use isa instead of dyn_cast (NFC)
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| #
50f1aa1d |
| 28-Jan-2021 |
Ben Shi <[email protected]> |
[AVR] Optimize 16-bit int shift
Reviewed By: dylanmckay
Differential Revision: https://reviews.llvm.org/D90092
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Revision tags: llvmorg-12.0.0-rc1, llvmorg-13-init |
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| #
2a4acf3e |
| 24-Jan-2021 |
Ben Shi <[email protected]> |
[AVR] Optimize 8-bit int shift
Reviewed By: dylanmckay
Differential Revision: https://reviews.llvm.org/D90678
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