Lines Matching refs:ISD
43 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
56 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Split_64()
82 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Ret_Split_64()
106 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in Analyze_CC_Sparc64_Full()
156 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in Analyze_CC_Sparc64_Half()
193 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
200 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
207 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in RetCC_Sparc64_Full()
214 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in RetCC_Sparc64_Half()
234 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn()
244 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
255 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
289 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
292 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
340 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
370 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
373 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
376 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
385 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
391 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
392 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
416 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
430 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments_32()
488 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
489 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
497 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
499 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
501 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
544 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
545 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
576 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerFormalArguments_32()
615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerFormalArguments_32()
625 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments_64()
651 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
658 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
662 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
671 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
726 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); in LowerFormalArguments_64()
796 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall_32()
798 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall_32()
825 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall_32()
869 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; in LowerCall_32()
884 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
887 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
890 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
893 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
906 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
926 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
939 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
942 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
945 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
960 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
969 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
974 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
988 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
999 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
1007 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32()
1083 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32); in LowerCall_32()
1088 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, in LowerCall_32()
1094 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi, in LowerCall_32()
1140 ArrayRef<ISD::OutputArg> Outs) { in fixupVariableFloatArgs()
1241 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1244 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1247 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1254 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1266 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff); in LowerCall_64()
1268 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff); in LowerCall_64()
1288 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, in LowerCall_64()
1295 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
1297 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); in LowerCall_64()
1315 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff); in LowerCall_64()
1322 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall_64()
1405 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
1417 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1424 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1428 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1437 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()
1459 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { in IntCondCCodeToICC()
1462 case ISD::SETEQ: return SPCC::ICC_E; in IntCondCCodeToICC()
1463 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1464 case ISD::SETLT: return SPCC::ICC_L; in IntCondCCodeToICC()
1465 case ISD::SETGT: return SPCC::ICC_G; in IntCondCCodeToICC()
1466 case ISD::SETLE: return SPCC::ICC_LE; in IntCondCCodeToICC()
1467 case ISD::SETGE: return SPCC::ICC_GE; in IntCondCCodeToICC()
1468 case ISD::SETULT: return SPCC::ICC_CS; in IntCondCCodeToICC()
1469 case ISD::SETULE: return SPCC::ICC_LEU; in IntCondCCodeToICC()
1470 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
1471 case ISD::SETUGE: return SPCC::ICC_CC; in IntCondCCodeToICC()
1477 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC()
1480 case ISD::SETEQ: in FPCondCCodeToFCC()
1481 case ISD::SETOEQ: return SPCC::FCC_E; in FPCondCCodeToFCC()
1482 case ISD::SETNE: in FPCondCCodeToFCC()
1483 case ISD::SETUNE: return SPCC::FCC_NE; in FPCondCCodeToFCC()
1484 case ISD::SETLT: in FPCondCCodeToFCC()
1485 case ISD::SETOLT: return SPCC::FCC_L; in FPCondCCodeToFCC()
1486 case ISD::SETGT: in FPCondCCodeToFCC()
1487 case ISD::SETOGT: return SPCC::FCC_G; in FPCondCCodeToFCC()
1488 case ISD::SETLE: in FPCondCCodeToFCC()
1489 case ISD::SETOLE: return SPCC::FCC_LE; in FPCondCCodeToFCC()
1490 case ISD::SETGE: in FPCondCCodeToFCC()
1491 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
1492 case ISD::SETULT: return SPCC::FCC_UL; in FPCondCCodeToFCC()
1493 case ISD::SETULE: return SPCC::FCC_ULE; in FPCondCCodeToFCC()
1494 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
1495 case ISD::SETUGE: return SPCC::FCC_UGE; in FPCondCCodeToFCC()
1496 case ISD::SETUO: return SPCC::FCC_U; in FPCondCCodeToFCC()
1497 case ISD::SETO: return SPCC::FCC_O; in FPCondCCodeToFCC()
1498 case ISD::SETONE: return SPCC::FCC_LG; in FPCondCCodeToFCC()
1499 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
1532 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { in SparcTargetLowering()
1537 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1538 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1539 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1541 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1542 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1543 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1549 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1550 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
1551 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
1552 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal); in SparcTargetLowering()
1555 setOperationAction(ISD::LOAD, MVT::i64, Custom); in SparcTargetLowering()
1556 setOperationAction(ISD::STORE, MVT::i64, Custom); in SparcTargetLowering()
1565 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in SparcTargetLowering()
1566 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1567 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
1572 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SparcTargetLowering()
1583 setOperationAction(ISD::GlobalAddress, PtrVT, Custom); in SparcTargetLowering()
1584 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom); in SparcTargetLowering()
1585 setOperationAction(ISD::ConstantPool, PtrVT, Custom); in SparcTargetLowering()
1586 setOperationAction(ISD::BlockAddress, PtrVT, Custom); in SparcTargetLowering()
1589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
1594 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1595 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1596 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1597 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1601 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
1602 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
1603 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1604 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1608 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1609 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1610 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
1611 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1614 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1615 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1616 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
1617 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1620 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in SparcTargetLowering()
1621 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in SparcTargetLowering()
1622 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in SparcTargetLowering()
1623 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in SparcTargetLowering()
1624 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); in SparcTargetLowering()
1625 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand); in SparcTargetLowering()
1627 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1628 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1631 setOperationAction(ISD::SELECT, MVT::i32, Expand); in SparcTargetLowering()
1632 setOperationAction(ISD::SELECT, MVT::f32, Expand); in SparcTargetLowering()
1633 setOperationAction(ISD::SELECT, MVT::f64, Expand); in SparcTargetLowering()
1634 setOperationAction(ISD::SELECT, MVT::f128, Expand); in SparcTargetLowering()
1636 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1637 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1638 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1639 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1642 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
1643 setOperationAction(ISD::BRIND, MVT::Other, Expand); in SparcTargetLowering()
1644 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in SparcTargetLowering()
1645 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1646 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1647 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1648 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1650 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1651 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1652 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1653 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1655 setOperationAction(ISD::ADDC, MVT::i32, Custom); in SparcTargetLowering()
1656 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1657 setOperationAction(ISD::SUBC, MVT::i32, Custom); in SparcTargetLowering()
1658 setOperationAction(ISD::SUBE, MVT::i32, Custom); in SparcTargetLowering()
1661 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
1662 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
1663 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
1664 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
1665 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
1666 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering()
1667 setOperationAction(ISD::SELECT, MVT::i64, Expand); in SparcTargetLowering()
1668 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
1669 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
1670 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1672 setOperationAction(ISD::CTPOP, MVT::i64, in SparcTargetLowering()
1674 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1675 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1676 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in SparcTargetLowering()
1677 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1678 setOperationAction(ISD::ROTR , MVT::i64, Expand); in SparcTargetLowering()
1679 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in SparcTargetLowering()
1695 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1697 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1700 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in SparcTargetLowering()
1701 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in SparcTargetLowering()
1704 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1705 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1706 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); in SparcTargetLowering()
1707 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); in SparcTargetLowering()
1722 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1723 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1726 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1727 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1728 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1729 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1730 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1731 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1732 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1733 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1734 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1735 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1736 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1737 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
1738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
1739 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
1740 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
1741 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
1742 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
1743 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
1744 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
1745 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in SparcTargetLowering()
1746 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1747 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1748 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
1749 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1750 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1751 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
1753 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1754 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1755 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1758 setOperationAction(ISD::MULHU, MVT::i32, Expand); in SparcTargetLowering()
1759 setOperationAction(ISD::MULHS, MVT::i32, Expand); in SparcTargetLowering()
1760 setOperationAction(ISD::MUL, MVT::i32, Expand); in SparcTargetLowering()
1764 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1765 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1768 setOperationAction(ISD::SDIV, MVT::i32, Expand); in SparcTargetLowering()
1771 setOperationAction(ISD::UDIV, MVT::i32, Expand); in SparcTargetLowering()
1779 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1780 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1781 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
1782 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
1784 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
1785 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
1787 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1788 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1789 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1793 setOperationAction(ISD::VASTART , MVT::Other, Custom); in SparcTargetLowering()
1795 setOperationAction(ISD::VAARG , MVT::Other, Custom); in SparcTargetLowering()
1797 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
1798 setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal); in SparcTargetLowering()
1801 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in SparcTargetLowering()
1802 setOperationAction(ISD::VAEND , MVT::Other, Expand); in SparcTargetLowering()
1803 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in SparcTargetLowering()
1804 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); in SparcTargetLowering()
1805 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in SparcTargetLowering()
1809 setOperationAction(ISD::CTPOP, MVT::i32, in SparcTargetLowering()
1813 setOperationAction(ISD::LOAD, MVT::f128, Legal); in SparcTargetLowering()
1814 setOperationAction(ISD::STORE, MVT::f128, Legal); in SparcTargetLowering()
1816 setOperationAction(ISD::LOAD, MVT::f128, Custom); in SparcTargetLowering()
1817 setOperationAction(ISD::STORE, MVT::f128, Custom); in SparcTargetLowering()
1821 setOperationAction(ISD::FADD, MVT::f128, Legal); in SparcTargetLowering()
1822 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1823 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1824 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1825 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1826 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1827 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1829 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1830 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1832 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1833 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1846 setOperationAction(ISD::FADD, MVT::f128, Custom); in SparcTargetLowering()
1847 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
1848 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1849 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1850 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1851 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1852 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1854 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
1855 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1856 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
1901 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
1902 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
1906 setOperationAction(ISD::FMUL, MVT::f32, Promote); in SparcTargetLowering()
1911 setTargetDAGCombine(ISD::BITCAST); in SparcTargetLowering()
1914 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in SparcTargetLowering()
1916 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in SparcTargetLowering()
1993 ISD::CondCode CC, unsigned &SPCC) { in LookThroughSetCC()
1995 CC == ISD::SETNE && in LookThroughSetCC()
2045 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeHiLoPair()
2071 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx); in makeAddress()
2092 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); in makeAddress()
2095 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); in makeAddress()
2101 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); in makeAddress()
2104 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeAddress()
2189 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
2208 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); in LowerGlobalTLSAddress()
2223 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
2225 return DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalTLSAddress()
2359 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2392 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2399 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2467 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in LowerFP_TO_SINT()
2493 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); in LowerSINT_TO_FP()
2542 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
2580 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
2624 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT), in LowerVASTART()
2642 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, in LowerVAARG()
2701 Size = DAG.getNode(ISD::ADD, dl, VT, Size, in LowerDYNAMIC_STACKALLOC()
2708 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
2713 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, in LowerDYNAMIC_STACKALLOC()
2749 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2754 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2795 SDValue Ptr = DAG.getNode(ISD::ADD, in LowerRETURNADDR()
2807 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2850 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Load()
2874 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Load()
2918 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Store()
2924 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Store()
2939 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue()); in LowerSTORE()
2951 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3000 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
3001 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
3003 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
3006 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
3007 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
3009 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
3016 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3017 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3018 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3019 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3032 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
3033 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
3034 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, in LowerADDC_ADDE_SUBC_SUBE()
3037 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); in LowerADDC_ADDE_SUBC_SUBE()
3048 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3050 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
3064 HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO()
3065 HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
3078 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, in LowerUMULO_SMULO()
3080 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, in LowerUMULO_SMULO()
3083 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO()
3084 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
3087 ISD::SETNE); in LowerUMULO_SMULO()
3131 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this, in LowerOperation()
3133 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG, in LowerOperation()
3135 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
3136 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
3137 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
3138 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
3139 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3141 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3143 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, in LowerOperation()
3145 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3147 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, in LowerOperation()
3149 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, in LowerOperation()
3151 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); in LowerOperation()
3152 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
3153 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, in LowerOperation()
3156 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
3157 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
3158 case ISD::FADD: return LowerF128Op(Op, DAG, in LowerOperation()
3160 case ISD::FSUB: return LowerF128Op(Op, DAG, in LowerOperation()
3162 case ISD::FMUL: return LowerF128Op(Op, DAG, in LowerOperation()
3164 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
3166 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
3168 case ISD::FABS: in LowerOperation()
3169 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
3170 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
3171 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
3172 case ISD::ADDC: in LowerOperation()
3173 case ISD::ADDE: in LowerOperation()
3174 case ISD::SUBC: in LowerOperation()
3175 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
3176 case ISD::UMULO: in LowerOperation()
3177 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
3178 case ISD::ATOMIC_LOAD: in LowerOperation()
3179 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG); in LowerOperation()
3180 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
3212 case ISD::BITCAST: in PerformDAGCombine()
3488 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3489 case ISD::FP_TO_UINT: in ReplaceNodeResults()
3494 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
3503 case ISD::READCYCLECOUNTER: { in ReplaceNodeResults()
3508 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops); in ReplaceNodeResults()
3513 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3514 case ISD::UINT_TO_FP: in ReplaceNodeResults()
3520 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
3529 case ISD::LOAD: { in ReplaceNodeResults()
3543 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes); in ReplaceNodeResults()