Lines Matching refs:ISD
63 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
64 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
76 setOperationAction(ISD::MUL, MVT::i8, Promote); in M68kTargetLowering()
77 setOperationAction(ISD::MUL, MVT::i16, Legal); in M68kTargetLowering()
79 setOperationAction(ISD::MUL, MVT::i32, Legal); in M68kTargetLowering()
81 setOperationAction(ISD::MUL, MVT::i32, LibCall); in M68kTargetLowering()
82 setOperationAction(ISD::MUL, MVT::i64, LibCall); in M68kTargetLowering()
85 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
98 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
104 for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) in M68kTargetLowering()
109 setOperationAction(ISD::ADDC, VT, Custom); in M68kTargetLowering()
110 setOperationAction(ISD::ADDE, VT, Custom); in M68kTargetLowering()
111 setOperationAction(ISD::SUBC, VT, Custom); in M68kTargetLowering()
112 setOperationAction(ISD::SUBE, VT, Custom); in M68kTargetLowering()
117 setOperationAction(ISD::SADDO, VT, Custom); in M68kTargetLowering()
118 setOperationAction(ISD::UADDO, VT, Custom); in M68kTargetLowering()
119 setOperationAction(ISD::SSUBO, VT, Custom); in M68kTargetLowering()
120 setOperationAction(ISD::USUBO, VT, Custom); in M68kTargetLowering()
123 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in M68kTargetLowering()
124 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in M68kTargetLowering()
127 setOperationAction(ISD::BR_CC, VT, Expand); in M68kTargetLowering()
128 setOperationAction(ISD::SELECT, VT, Custom); in M68kTargetLowering()
129 setOperationAction(ISD::SELECT_CC, VT, Expand); in M68kTargetLowering()
130 setOperationAction(ISD::SETCC, VT, Custom); in M68kTargetLowering()
131 setOperationAction(ISD::SETCCCARRY, VT, Custom); in M68kTargetLowering()
135 setOperationAction(ISD::BSWAP, VT, Expand); in M68kTargetLowering()
136 setOperationAction(ISD::CTTZ, VT, Expand); in M68kTargetLowering()
137 setOperationAction(ISD::CTLZ, VT, Expand); in M68kTargetLowering()
138 setOperationAction(ISD::CTPOP, VT, Expand); in M68kTargetLowering()
141 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in M68kTargetLowering()
142 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in M68kTargetLowering()
143 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in M68kTargetLowering()
144 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in M68kTargetLowering()
145 setOperationAction(ISD::ExternalSymbol, MVT::i32, Custom); in M68kTargetLowering()
146 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in M68kTargetLowering()
148 setOperationAction(ISD::VASTART, MVT::Other, Custom); in M68kTargetLowering()
149 setOperationAction(ISD::VAEND, MVT::Other, Expand); in M68kTargetLowering()
150 setOperationAction(ISD::VAARG, MVT::Other, Expand); in M68kTargetLowering()
151 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in M68kTargetLowering()
153 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in M68kTargetLowering()
154 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in M68kTargetLowering()
156 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom); in M68kTargetLowering()
184 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { in callIsStructReturn()
188 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; in callIsStructReturn()
198 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { in argsAreStructReturn()
202 const ISD::ArgFlagsTy &Flags = Ins[0].Flags; in argsAreStructReturn()
214 SDValue Chain, ISD::ArgFlagsTy Flags, in CreateCopyOfByValArgument()
247 ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, in MatchingStackOffset()
256 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
260 if (Op == ISD::TRUNCATE) { in MatchingStackOffset()
262 if (TruncInput.getOpcode() == ISD::AssertZext && in MatchingStackOffset()
273 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
305 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { in MatchingStackOffset()
381 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerMemArgument()
387 ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags; in LowerMemArgument()
444 return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val) in LowerMemArgument()
453 ISD::ArgFlagsTy Flags) const { in LowerMemOpCallTo()
456 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
474 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
476 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
589 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
607 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
610 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
613 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
644 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall()
679 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
696 Source = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerCall()
710 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2); in LowerCall()
727 if (Callee->getOpcode() == ISD::GlobalAddress) { in LowerCall()
838 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCallResult()
858 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
873 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
913 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
916 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
923 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
956 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); in LowerFormalArguments()
1017 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
1044 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1046 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1049 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1051 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1170 const SmallVectorImpl<ISD::OutputArg> &Outs, in IsEligibleForTailCallOptimization()
1172 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const { in IsEligibleForTailCallOptimization()
1253 ISD::ArgFlagsTy Flags = Outs[i].Flags; in IsEligibleForTailCallOptimization()
1326 case ISD::SADDO: in LowerOperation()
1327 case ISD::UADDO: in LowerOperation()
1328 case ISD::SSUBO: in LowerOperation()
1329 case ISD::USUBO: in LowerOperation()
1330 case ISD::SMULO: in LowerOperation()
1331 case ISD::UMULO: in LowerOperation()
1333 case ISD::SETCC: in LowerOperation()
1335 case ISD::SETCCCARRY: in LowerOperation()
1337 case ISD::SELECT: in LowerOperation()
1339 case ISD::BRCOND: in LowerOperation()
1341 case ISD::ADDC: in LowerOperation()
1342 case ISD::ADDE: in LowerOperation()
1343 case ISD::SUBC: in LowerOperation()
1344 case ISD::SUBE: in LowerOperation()
1346 case ISD::ConstantPool: in LowerOperation()
1348 case ISD::GlobalAddress: in LowerOperation()
1350 case ISD::ExternalSymbol: in LowerOperation()
1352 case ISD::BlockAddress: in LowerOperation()
1354 case ISD::JumpTable: in LowerOperation()
1356 case ISD::VASTART: in LowerOperation()
1358 case ISD::DYNAMIC_STACKALLOC: in LowerOperation()
1360 case ISD::SHL_PARTS: in LowerOperation()
1362 case ISD::SRA_PARTS: in LowerOperation()
1364 case ISD::SRL_PARTS: in LowerOperation()
1393 case ISD::SADDO: in LowerXALUO()
1397 case ISD::UADDO: in LowerXALUO()
1401 case ISD::SSUBO: in LowerXALUO()
1405 case ISD::USUBO: in LowerXALUO()
1418 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC); in LowerXALUO()
1423 static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, in getBitTestCondition()
1429 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src); in getBitTestCondition()
1434 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo); in getBitTestCondition()
1439 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition()
1445 static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, in LowerAndToBTST()
1449 if (Op0.getOpcode() == ISD::TRUNCATE) in LowerAndToBTST()
1451 if (Op1.getOpcode() == ISD::TRUNCATE) in LowerAndToBTST()
1455 if (Op1.getOpcode() == ISD::SHL) in LowerAndToBTST()
1457 if (Op0.getOpcode() == ISD::SHL) { in LowerAndToBTST()
1475 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { in LowerAndToBTST()
1493 static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode) { in TranslateIntegerM68kCC()
1497 case ISD::SETEQ: in TranslateIntegerM68kCC()
1499 case ISD::SETGT: in TranslateIntegerM68kCC()
1501 case ISD::SETGE: in TranslateIntegerM68kCC()
1503 case ISD::SETLT: in TranslateIntegerM68kCC()
1505 case ISD::SETLE: in TranslateIntegerM68kCC()
1507 case ISD::SETNE: in TranslateIntegerM68kCC()
1509 case ISD::SETULT: in TranslateIntegerM68kCC()
1511 case ISD::SETUGE: in TranslateIntegerM68kCC()
1513 case ISD::SETUGT: in TranslateIntegerM68kCC()
1515 case ISD::SETULE: in TranslateIntegerM68kCC()
1523 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, in TranslateM68kCC()
1528 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { in TranslateM68kCC()
1533 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateM68kCC()
1537 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1550 if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) { in TranslateM68kCC()
1558 case ISD::SETOLT: in TranslateM68kCC()
1559 case ISD::SETOLE: in TranslateM68kCC()
1560 case ISD::SETUGT: in TranslateM68kCC()
1561 case ISD::SETUGE: in TranslateM68kCC()
1575 case ISD::SETUEQ: in TranslateM68kCC()
1576 case ISD::SETEQ: in TranslateM68kCC()
1578 case ISD::SETOLT: // flipped in TranslateM68kCC()
1579 case ISD::SETOGT: in TranslateM68kCC()
1580 case ISD::SETGT: in TranslateM68kCC()
1582 case ISD::SETOLE: // flipped in TranslateM68kCC()
1583 case ISD::SETOGE: in TranslateM68kCC()
1584 case ISD::SETGE: in TranslateM68kCC()
1586 case ISD::SETUGT: // flipped in TranslateM68kCC()
1587 case ISD::SETULT: in TranslateM68kCC()
1588 case ISD::SETLT: in TranslateM68kCC()
1590 case ISD::SETUGE: // flipped in TranslateM68kCC()
1591 case ISD::SETULE: in TranslateM68kCC()
1592 case ISD::SETLE: in TranslateM68kCC()
1594 case ISD::SETONE: in TranslateM68kCC()
1595 case ISD::SETNE: in TranslateM68kCC()
1597 case ISD::SETOEQ: in TranslateM68kCC()
1598 case ISD::SETUNE: in TranslateM68kCC()
1604 static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, in LowerTruncateToBTST()
1607 assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 && in LowerTruncateToBTST()
1610 if (Op.getOperand(0).getOpcode() != ISD::SRL) in LowerTruncateToBTST()
1624 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { in hasNonFlagsUse()
1630 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && in hasNonFlagsUse()
1631 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) in hasNonFlagsUse()
1663 case ISD::ADD: in EmitTest()
1664 case ISD::SUB: in EmitTest()
1665 case ISD::MUL: in EmitTest()
1666 case ISD::SHL: { in EmitTest()
1694 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { in EmitTest()
1701 case ISD::ADD: in EmitTest()
1702 case ISD::SUB: in EmitTest()
1703 case ISD::AND: in EmitTest()
1704 case ISD::OR: in EmitTest()
1705 case ISD::XOR: { in EmitTest()
1716 case ISD::ADD: in EmitTest()
1720 case ISD::SHL: in EmitTest()
1721 case ISD::SRL: in EmitTest()
1733 APInt Mask = ArithOp.getOpcode() == ISD::SRL in EmitTest()
1738 Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0), in EmitTest()
1743 case ISD::AND: in EmitTest()
1759 case ISD::SUB: in EmitTest()
1760 case ISD::OR: in EmitTest()
1761 case ISD::XOR: in EmitTest()
1765 if (U->getOpcode() == ISD::STORE) in EmitTest()
1772 case ISD::SUB: in EmitTest()
1775 case ISD::XOR: in EmitTest()
1778 case ISD::AND: in EmitTest()
1781 case ISD::OR: in EmitTest()
1812 case ISD::ADD: in EmitTest()
1815 case ISD::SUB: in EmitTest()
1818 case ISD::AND: in EmitTest()
1821 case ISD::OR: in EmitTest()
1824 case ISD::XOR: in EmitTest()
1832 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0)); in EmitTest()
1833 SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1)); in EmitTest()
1888 isM68kCCUnsigned(M68kCC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in EmitCmp()
1902 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC, in LowerToBTST()
1905 if (Op.getOpcode() == ISD::AND) in LowerToBTST()
1907 if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1) in LowerToBTST()
1919 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
1927 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1930 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC); in LowerSETCC()
1938 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1944 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in LowerSETCC()
1953 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
1957 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1959 ISD::CondCode NewCC = ISD::GlobalISel::getSetCCInverse(CC, true); in LowerSETCC()
1963 SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1); in LowerSETCC()
2020 if (V.getOpcode() != ISD::TRUNCATE) in isTruncWithZeroHighBitsInput()
2038 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
2089 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); in LowerSELECT()
2095 if (Cond.getOpcode() == ISD::AND && in LowerSELECT()
2115 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || in LowerSELECT()
2116 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT()
2117 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
2124 case ISD::UADDO: in LowerSELECT()
2128 case ISD::SADDO: in LowerSELECT()
2132 case ISD::USUBO: in LowerSELECT()
2136 case ISD::SSUBO: in LowerSELECT()
2140 case ISD::UMULO: in LowerSELECT()
2144 case ISD::SMULO: in LowerSELECT()
2151 if (CondOpcode == ISD::UMULO) in LowerSELECT()
2158 if (CondOpcode == ISD::UMULO) in LowerSELECT()
2174 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { in LowerSELECT()
2175 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerSELECT()
2210 if (Op.getValueType() == MVT::i8 && Op1.getOpcode() == ISD::TRUNCATE && in LowerSELECT()
2211 Op2.getOpcode() == ISD::TRUNCATE) { in LowerSELECT()
2215 T1.getOpcode() != ISD::CopyFromReg && in LowerSELECT()
2216 T2.getOpcode() != ISD::CopyFromReg) { in LowerSELECT()
2219 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov); in LowerSELECT()
2234 if (Opc != ISD::OR && Opc != ISD::AND) in isAndOrOfSetCCs()
2245 if (Op.getOpcode() != ISD::XOR) in isXor1OfSetCC()
2262 if (Cond.getOpcode() == ISD::SETCC) { in LowerBRCOND()
2264 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && in LowerBRCOND()
2267 (Cond.getOperand(0).getOpcode() == ISD::SADDO || in LowerBRCOND()
2268 Cond.getOperand(0).getOpcode() == ISD::UADDO || in LowerBRCOND()
2269 Cond.getOperand(0).getOpcode() == ISD::SSUBO || in LowerBRCOND()
2270 Cond.getOperand(0).getOpcode() == ISD::USUBO)) { in LowerBRCOND()
2280 if (Cond.getOpcode() == ISD::AND && in LowerBRCOND()
2312 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerBRCOND()
2313 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO) { in LowerBRCOND()
2323 case ISD::UADDO: in LowerBRCOND()
2327 case ISD::SADDO: in LowerBRCOND()
2331 case ISD::USUBO: in LowerBRCOND()
2335 case ISD::SSUBO: in LowerBRCOND()
2339 case ISD::UMULO: in LowerBRCOND()
2343 case ISD::SMULO: in LowerBRCOND()
2354 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
2361 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
2372 if (CondOpc == ISD::OR) { in LowerBRCOND()
2400 if (User->getOpcode() == ISD::BR) { in LowerBRCOND()
2439 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerBRCOND()
2471 case ISD::ADDC: in LowerADDC_ADDE_SUBC_SUBE()
2474 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
2478 case ISD::SUBC: in LowerADDC_ADDE_SUBC_SUBE()
2481 case ISD::SUBE: in LowerADDC_ADDE_SUBC_SUBE()
2521 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerConstantPool()
2551 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerExternalSymbol()
2586 DAG.getNode(ISD::ADD, DL, PtrVT, in LowerBlockAddress()
2617 DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalAddress()
2631 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result, in LowerGlobalAddress()
2669 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerJumpTable()
3237 Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
3239 Result = DAG.getNode(ISD::AND, DL, VT, Result, in LowerDYNAMIC_STACKALLOC()
3271 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftLeftParts()
3273 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftLeftParts()
3275 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in LowerShiftLeftParts()
3276 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in LowerShiftLeftParts()
3278 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt); in LowerShiftLeftParts()
3279 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in LowerShiftLeftParts()
3280 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); in LowerShiftLeftParts()
3281 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize); in LowerShiftLeftParts()
3284 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
3286 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); in LowerShiftLeftParts()
3287 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in LowerShiftLeftParts()
3316 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in LowerShiftRightParts()
3323 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftRightParts()
3325 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftRightParts()
3327 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in LowerShiftRightParts()
3328 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); in LowerShiftRightParts()
3330 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt); in LowerShiftRightParts()
3331 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi); in LowerShiftRightParts()
3336 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero; in LowerShiftRightParts()
3339 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()
3341 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); in LowerShiftRightParts()
3342 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in LowerShiftRightParts()
3363 while (Carry.getOpcode() == ISD::TRUNCATE || in combineCarryThroughADD()
3364 Carry.getOpcode() == ISD::ZERO_EXTEND || in combineCarryThroughADD()
3365 Carry.getOpcode() == ISD::SIGN_EXTEND || in combineCarryThroughADD()
3366 Carry.getOpcode() == ISD::ANY_EXTEND || in combineCarryThroughADD()
3367 (Carry.getOpcode() == ISD::AND && in combineCarryThroughADD()