Lines Matching refs:ISD
85 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in LanaiTargetLowering()
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in LanaiTargetLowering()
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in LanaiTargetLowering()
88 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
89 setOperationAction(ISD::SELECT, MVT::i32, Expand); in LanaiTargetLowering()
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in LanaiTargetLowering()
92 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in LanaiTargetLowering()
93 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in LanaiTargetLowering()
94 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in LanaiTargetLowering()
95 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in LanaiTargetLowering()
97 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in LanaiTargetLowering()
98 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in LanaiTargetLowering()
99 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in LanaiTargetLowering()
101 setOperationAction(ISD::VASTART, MVT::Other, Custom); in LanaiTargetLowering()
102 setOperationAction(ISD::VAARG, MVT::Other, Expand); in LanaiTargetLowering()
103 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in LanaiTargetLowering()
104 setOperationAction(ISD::VAEND, MVT::Other, Expand); in LanaiTargetLowering()
106 setOperationAction(ISD::SDIV, MVT::i32, Expand); in LanaiTargetLowering()
107 setOperationAction(ISD::UDIV, MVT::i32, Expand); in LanaiTargetLowering()
108 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in LanaiTargetLowering()
109 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in LanaiTargetLowering()
110 setOperationAction(ISD::SREM, MVT::i32, Expand); in LanaiTargetLowering()
111 setOperationAction(ISD::UREM, MVT::i32, Expand); in LanaiTargetLowering()
113 setOperationAction(ISD::MUL, MVT::i32, Custom); in LanaiTargetLowering()
114 setOperationAction(ISD::MULHU, MVT::i32, Expand); in LanaiTargetLowering()
115 setOperationAction(ISD::MULHS, MVT::i32, Expand); in LanaiTargetLowering()
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in LanaiTargetLowering()
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in LanaiTargetLowering()
119 setOperationAction(ISD::ROTR, MVT::i32, Expand); in LanaiTargetLowering()
120 setOperationAction(ISD::ROTL, MVT::i32, Expand); in LanaiTargetLowering()
121 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in LanaiTargetLowering()
122 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in LanaiTargetLowering()
123 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in LanaiTargetLowering()
125 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in LanaiTargetLowering()
126 setOperationAction(ISD::CTPOP, MVT::i32, Legal); in LanaiTargetLowering()
127 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in LanaiTargetLowering()
128 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in LanaiTargetLowering()
130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LanaiTargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in LanaiTargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in LanaiTargetLowering()
136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()
138 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()
141 setTargetDAGCombine({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR}); in LanaiTargetLowering()
174 case ISD::MUL: in LowerOperation()
176 case ISD::BR_CC: in LowerOperation()
178 case ISD::ConstantPool: in LowerOperation()
180 case ISD::GlobalAddress: in LowerOperation()
182 case ISD::BlockAddress: in LowerOperation()
184 case ISD::JumpTable: in LowerOperation()
186 case ISD::SELECT_CC: in LowerOperation()
188 case ISD::SETCC: in LowerOperation()
190 case ISD::SHL_PARTS: in LowerOperation()
192 case ISD::SRL_PARTS: in LowerOperation()
194 case ISD::VASTART: in LowerOperation()
196 case ISD::DYNAMIC_STACKALLOC: in LowerOperation()
198 case ISD::RETURNADDR: in LowerOperation()
200 case ISD::FRAMEADDR: in LowerOperation()
367 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Lanai32_VarArg()
394 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
409 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
411 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
435 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCCCArguments()
467 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
470 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
516 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); in LowerCCCArguments()
531 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn()
541 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
603 bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo()
605 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCCCCallTo()
635 ISD::ArgFlagsTy Flags = Outs[I].Flags; in LowerCCCCallTo()
665 ISD::ArgFlagsTy Flags = Outs[I].Flags; in LowerCCCCallTo()
672 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
675 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
678 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
700 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, in LowerCCCCallTo()
711 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, in LowerCCCCallTo()
781 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCallResult()
808 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); in IntCondCCodeToICC()
815 case ISD::SETEQ: in IntCondCCodeToICC()
817 case ISD::SETGT: in IntCondCCodeToICC()
825 case ISD::SETUGT: in IntCondCCodeToICC()
827 case ISD::SETLT: in IntCondCCodeToICC()
833 case ISD::SETULT: in IntCondCCodeToICC()
835 case ISD::SETLE: in IntCondCCodeToICC()
843 case ISD::SETULE: in IntCondCCodeToICC()
845 case ISD::SETGE: in IntCondCCodeToICC()
851 case ISD::SETUGE: in IntCondCCodeToICC()
853 case ISD::SETNE: in IntCondCCodeToICC()
855 case ISD::SETONE: in IntCondCCodeToICC()
856 case ISD::SETUNE: in IntCondCCodeToICC()
857 case ISD::SETOGE: in IntCondCCodeToICC()
858 case ISD::SETOLE: in IntCondCCodeToICC()
859 case ISD::SETOLT: in IntCondCCodeToICC()
860 case ISD::SETOGT: in IntCondCCodeToICC()
861 case ISD::SETOEQ: in IntCondCCodeToICC()
862 case ISD::SETUEQ: in IntCondCCodeToICC()
863 case ISD::SETO: in IntCondCCodeToICC()
864 case ISD::SETUO: in IntCondCCodeToICC()
951 Res = DAG.getNode(ISD::SHL, DL, VT, V, in LowerMUL()
965 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32)); in LowerMUL()
967 Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op); in LowerMUL()
969 Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op); in LowerMUL()
1035 SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size); in LowerDYNAMIC_STACKALLOC()
1069 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, in LowerRETURNADDR()
1091 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, in LowerFRAMEADDR()
1145 return DAG.getNode(ISD::OR, DL, MVT::i32, in LowerConstantPool()
1158 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo); in LowerConstantPool()
1179 return DAG.getNode(ISD::OR, DL, MVT::i32, in LowerGlobalAddress()
1193 return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo); in LowerGlobalAddress()
1209 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo); in LowerBlockAddress()
1222 return DAG.getNode(ISD::OR, DL, MVT::i32, in LowerJumpTable()
1235 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo); in LowerJumpTable()
1257 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerSHL_PARTS()
1259 SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerSHL_PARTS()
1264 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS()
1267 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, in LowerSHL_PARTS()
1269 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerSHL_PARTS()
1271 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi); in LowerSHL_PARTS()
1273 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerSHL_PARTS()
1275 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1281 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerSHL_PARTS()
1311 ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); in LowerSRL_PARTS()
1312 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS()
1314 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt); in LowerSRL_PARTS()
1317 SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt); in LowerSRL_PARTS()
1320 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32); in LowerSRL_PARTS()
1321 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSRL_PARTS()
1323 DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits)); in LowerSRL_PARTS()
1358 case ISD::SELECT: { in isConditionalZeroOrAllOnes()
1374 case ISD::ZERO_EXTEND: { in isConditionalZeroOrAllOnes()
1387 case ISD::SIGN_EXTEND: { in isConditionalZeroOrAllOnes()
1442 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal); in combineSelectAndUse()
1479 case ISD::ADD: in PerformDAGCombine()
1480 case ISD::OR: in PerformDAGCombine()
1481 case ISD::XOR: in PerformDAGCombine()
1483 case ISD::AND: in PerformDAGCombine()
1485 case ISD::SUB: in PerformDAGCombine()