Lines Matching refs:ISD
268 case ISD::LOAD: { in LegalizeOp()
270 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
272 if (LoadedVT.isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
276 case ISD::STORE: { in LegalizeOp()
284 case ISD::MERGE_VALUES: in LegalizeOp()
292 case ISD::STRICT_##DAGN: in LegalizeOp()
295 if (Op.getOpcode() == ISD::STRICT_SINT_TO_FP || in LegalizeOp()
296 Op.getOpcode() == ISD::STRICT_UINT_TO_FP) in LegalizeOp()
315 case ISD::ADD: in LegalizeOp()
316 case ISD::SUB: in LegalizeOp()
317 case ISD::MUL: in LegalizeOp()
318 case ISD::MULHS: in LegalizeOp()
319 case ISD::MULHU: in LegalizeOp()
320 case ISD::SDIV: in LegalizeOp()
321 case ISD::UDIV: in LegalizeOp()
322 case ISD::SREM: in LegalizeOp()
323 case ISD::UREM: in LegalizeOp()
324 case ISD::SDIVREM: in LegalizeOp()
325 case ISD::UDIVREM: in LegalizeOp()
326 case ISD::FADD: in LegalizeOp()
327 case ISD::FSUB: in LegalizeOp()
328 case ISD::FMUL: in LegalizeOp()
329 case ISD::FDIV: in LegalizeOp()
330 case ISD::FREM: in LegalizeOp()
331 case ISD::AND: in LegalizeOp()
332 case ISD::OR: in LegalizeOp()
333 case ISD::XOR: in LegalizeOp()
334 case ISD::SHL: in LegalizeOp()
335 case ISD::SRA: in LegalizeOp()
336 case ISD::SRL: in LegalizeOp()
337 case ISD::FSHL: in LegalizeOp()
338 case ISD::FSHR: in LegalizeOp()
339 case ISD::ROTL: in LegalizeOp()
340 case ISD::ROTR: in LegalizeOp()
341 case ISD::ABS: in LegalizeOp()
342 case ISD::BSWAP: in LegalizeOp()
343 case ISD::BITREVERSE: in LegalizeOp()
344 case ISD::CTLZ: in LegalizeOp()
345 case ISD::CTTZ: in LegalizeOp()
346 case ISD::CTLZ_ZERO_UNDEF: in LegalizeOp()
347 case ISD::CTTZ_ZERO_UNDEF: in LegalizeOp()
348 case ISD::CTPOP: in LegalizeOp()
349 case ISD::SELECT: in LegalizeOp()
350 case ISD::VSELECT: in LegalizeOp()
351 case ISD::SELECT_CC: in LegalizeOp()
352 case ISD::ZERO_EXTEND: in LegalizeOp()
353 case ISD::ANY_EXTEND: in LegalizeOp()
354 case ISD::TRUNCATE: in LegalizeOp()
355 case ISD::SIGN_EXTEND: in LegalizeOp()
356 case ISD::FP_TO_SINT: in LegalizeOp()
357 case ISD::FP_TO_UINT: in LegalizeOp()
358 case ISD::FNEG: in LegalizeOp()
359 case ISD::FABS: in LegalizeOp()
360 case ISD::FMINNUM: in LegalizeOp()
361 case ISD::FMAXNUM: in LegalizeOp()
362 case ISD::FMINNUM_IEEE: in LegalizeOp()
363 case ISD::FMAXNUM_IEEE: in LegalizeOp()
364 case ISD::FMINIMUM: in LegalizeOp()
365 case ISD::FMAXIMUM: in LegalizeOp()
366 case ISD::FCOPYSIGN: in LegalizeOp()
367 case ISD::FSQRT: in LegalizeOp()
368 case ISD::FSIN: in LegalizeOp()
369 case ISD::FCOS: in LegalizeOp()
370 case ISD::FPOWI: in LegalizeOp()
371 case ISD::FPOW: in LegalizeOp()
372 case ISD::FLOG: in LegalizeOp()
373 case ISD::FLOG2: in LegalizeOp()
374 case ISD::FLOG10: in LegalizeOp()
375 case ISD::FEXP: in LegalizeOp()
376 case ISD::FEXP2: in LegalizeOp()
377 case ISD::FCEIL: in LegalizeOp()
378 case ISD::FTRUNC: in LegalizeOp()
379 case ISD::FRINT: in LegalizeOp()
380 case ISD::FNEARBYINT: in LegalizeOp()
381 case ISD::FROUND: in LegalizeOp()
382 case ISD::FROUNDEVEN: in LegalizeOp()
383 case ISD::FFLOOR: in LegalizeOp()
384 case ISD::FP_ROUND: in LegalizeOp()
385 case ISD::FP_EXTEND: in LegalizeOp()
386 case ISD::FMA: in LegalizeOp()
387 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
388 case ISD::ANY_EXTEND_VECTOR_INREG: in LegalizeOp()
389 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
390 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
391 case ISD::SMIN: in LegalizeOp()
392 case ISD::SMAX: in LegalizeOp()
393 case ISD::UMIN: in LegalizeOp()
394 case ISD::UMAX: in LegalizeOp()
395 case ISD::SMUL_LOHI: in LegalizeOp()
396 case ISD::UMUL_LOHI: in LegalizeOp()
397 case ISD::SADDO: in LegalizeOp()
398 case ISD::UADDO: in LegalizeOp()
399 case ISD::SSUBO: in LegalizeOp()
400 case ISD::USUBO: in LegalizeOp()
401 case ISD::SMULO: in LegalizeOp()
402 case ISD::UMULO: in LegalizeOp()
403 case ISD::FCANONICALIZE: in LegalizeOp()
404 case ISD::SADDSAT: in LegalizeOp()
405 case ISD::UADDSAT: in LegalizeOp()
406 case ISD::SSUBSAT: in LegalizeOp()
407 case ISD::USUBSAT: in LegalizeOp()
408 case ISD::SSHLSAT: in LegalizeOp()
409 case ISD::USHLSAT: in LegalizeOp()
410 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
411 case ISD::FP_TO_UINT_SAT: in LegalizeOp()
412 case ISD::MGATHER: in LegalizeOp()
415 case ISD::SMULFIX: in LegalizeOp()
416 case ISD::SMULFIXSAT: in LegalizeOp()
417 case ISD::UMULFIX: in LegalizeOp()
418 case ISD::UMULFIXSAT: in LegalizeOp()
419 case ISD::SDIVFIX: in LegalizeOp()
420 case ISD::SDIVFIXSAT: in LegalizeOp()
421 case ISD::UDIVFIX: in LegalizeOp()
422 case ISD::UDIVFIXSAT: { in LegalizeOp()
428 case ISD::SINT_TO_FP: in LegalizeOp()
429 case ISD::UINT_TO_FP: in LegalizeOp()
430 case ISD::VECREDUCE_ADD: in LegalizeOp()
431 case ISD::VECREDUCE_MUL: in LegalizeOp()
432 case ISD::VECREDUCE_AND: in LegalizeOp()
433 case ISD::VECREDUCE_OR: in LegalizeOp()
434 case ISD::VECREDUCE_XOR: in LegalizeOp()
435 case ISD::VECREDUCE_SMAX: in LegalizeOp()
436 case ISD::VECREDUCE_SMIN: in LegalizeOp()
437 case ISD::VECREDUCE_UMAX: in LegalizeOp()
438 case ISD::VECREDUCE_UMIN: in LegalizeOp()
439 case ISD::VECREDUCE_FADD: in LegalizeOp()
440 case ISD::VECREDUCE_FMUL: in LegalizeOp()
441 case ISD::VECREDUCE_FMAX: in LegalizeOp()
442 case ISD::VECREDUCE_FMIN: in LegalizeOp()
446 case ISD::VECREDUCE_SEQ_FADD: in LegalizeOp()
447 case ISD::VECREDUCE_SEQ_FMUL: in LegalizeOp()
451 case ISD::SETCC: { in LegalizeOp()
453 ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get(); in LegalizeOp()
461 case ISD::VPID: { \ in LegalizeOp()
464 if (ISD::VPID == ISD::VP_SETCC) { \ in LegalizeOp()
465 ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get(); \ in LegalizeOp()
481 assert((Op.getOpcode() != ISD::LOAD && Op.getOpcode() != ISD::STORE) && in LegalizeOp()
544 case ISD::SINT_TO_FP: in Promote()
545 case ISD::UINT_TO_FP: in Promote()
546 case ISD::STRICT_SINT_TO_FP: in Promote()
547 case ISD::STRICT_UINT_TO_FP: in Promote()
551 case ISD::FP_TO_UINT: in Promote()
552 case ISD::FP_TO_SINT: in Promote()
553 case ISD::STRICT_FP_TO_UINT: in Promote()
554 case ISD::STRICT_FP_TO_SINT: in Promote()
558 case ISD::FP_ROUND: in Promote()
559 case ISD::FP_EXTEND: in Promote()
584 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j)); in Promote()
586 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j)); in Promote()
597 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl)); in Promote()
599 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
617 unsigned Opc = (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteINT_TO_FP()
618 Node->getOpcode() == ISD::STRICT_UINT_TO_FP) in PromoteINT_TO_FP()
619 ? ISD::ZERO_EXTEND in PromoteINT_TO_FP()
620 : ISD::SIGN_EXTEND; in PromoteINT_TO_FP()
656 if (NewOpc == ISD::FP_TO_UINT && in PromoteFP_TO_INT()
657 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
658 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
660 if (NewOpc == ISD::STRICT_FP_TO_UINT && in PromoteFP_TO_INT()
661 TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
662 NewOpc = ISD::STRICT_FP_TO_SINT; in PromoteFP_TO_INT()
676 if (Node->getOpcode() == ISD::FP_TO_UINT || in PromoteFP_TO_INT()
677 Node->getOpcode() == ISD::STRICT_FP_TO_UINT) in PromoteFP_TO_INT()
678 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT()
680 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT()
684 Promoted = DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted); in PromoteFP_TO_INT()
703 case ISD::LOAD: { in Expand()
709 case ISD::STORE: in Expand()
712 case ISD::MERGE_VALUES: in Expand()
716 case ISD::SIGN_EXTEND_INREG: in Expand()
719 case ISD::ANY_EXTEND_VECTOR_INREG: in Expand()
722 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
725 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
728 case ISD::BSWAP: in Expand()
731 case ISD::VSELECT: in Expand()
734 case ISD::VP_SELECT: in Expand()
737 case ISD::SELECT: in Expand()
740 case ISD::SELECT_CC: { in Expand()
745 DAG.getNode(ISD::SETCC, SDLoc(Node), CondVT, Node->getOperand(0), in Expand()
754 case ISD::FP_TO_UINT: in Expand()
757 case ISD::UINT_TO_FP: in Expand()
760 case ISD::FNEG: in Expand()
763 case ISD::FSUB: in Expand()
766 case ISD::SETCC: in Expand()
767 case ISD::VP_SETCC: in Expand()
770 case ISD::ABS: in Expand()
776 case ISD::BITREVERSE: in Expand()
779 case ISD::CTPOP: in Expand()
785 case ISD::CTLZ: in Expand()
786 case ISD::CTLZ_ZERO_UNDEF: in Expand()
792 case ISD::CTTZ: in Expand()
793 case ISD::CTTZ_ZERO_UNDEF: in Expand()
799 case ISD::FSHL: in Expand()
800 case ISD::FSHR: in Expand()
806 case ISD::ROTL: in Expand()
807 case ISD::ROTR: in Expand()
813 case ISD::FMINNUM: in Expand()
814 case ISD::FMAXNUM: in Expand()
820 case ISD::SMIN: in Expand()
821 case ISD::SMAX: in Expand()
822 case ISD::UMIN: in Expand()
823 case ISD::UMAX: in Expand()
829 case ISD::UADDO: in Expand()
830 case ISD::USUBO: in Expand()
833 case ISD::SADDO: in Expand()
834 case ISD::SSUBO: in Expand()
837 case ISD::UMULO: in Expand()
838 case ISD::SMULO: in Expand()
841 case ISD::USUBSAT: in Expand()
842 case ISD::SSUBSAT: in Expand()
843 case ISD::UADDSAT: in Expand()
844 case ISD::SADDSAT: in Expand()
850 case ISD::FP_TO_SINT_SAT: in Expand()
851 case ISD::FP_TO_UINT_SAT: in Expand()
860 case ISD::SMULFIX: in Expand()
861 case ISD::UMULFIX: in Expand()
867 case ISD::SMULFIXSAT: in Expand()
868 case ISD::UMULFIXSAT: in Expand()
874 case ISD::SDIVFIX: in Expand()
875 case ISD::UDIVFIX: in Expand()
878 case ISD::SDIVFIXSAT: in Expand()
879 case ISD::UDIVFIXSAT: in Expand()
882 case ISD::STRICT_##DAGN: in Expand()
886 case ISD::VECREDUCE_ADD: in Expand()
887 case ISD::VECREDUCE_MUL: in Expand()
888 case ISD::VECREDUCE_AND: in Expand()
889 case ISD::VECREDUCE_OR: in Expand()
890 case ISD::VECREDUCE_XOR: in Expand()
891 case ISD::VECREDUCE_SMAX: in Expand()
892 case ISD::VECREDUCE_SMIN: in Expand()
893 case ISD::VECREDUCE_UMAX: in Expand()
894 case ISD::VECREDUCE_UMIN: in Expand()
895 case ISD::VECREDUCE_FADD: in Expand()
896 case ISD::VECREDUCE_FMUL: in Expand()
897 case ISD::VECREDUCE_FMAX: in Expand()
898 case ISD::VECREDUCE_FMIN: in Expand()
901 case ISD::VECREDUCE_SEQ_FADD: in Expand()
902 case ISD::VECREDUCE_SEQ_FMUL: in Expand()
905 case ISD::SREM: in Expand()
906 case ISD::UREM: in Expand()
909 case ISD::VP_MERGE: in Expand()
939 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || in ExpandSELECT()
940 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || in ExpandSELECT()
941 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand || in ExpandSELECT()
942 TLI.getOperationAction(VT.isFixedLengthVector() ? ISD::BUILD_VECTOR in ExpandSELECT()
943 : ISD::SPLAT_VECTOR, in ExpandSELECT()
965 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); in ExpandSELECT()
966 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
970 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); in ExpandSELECT()
971 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); in ExpandSELECT()
972 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); in ExpandSELECT()
973 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val); in ExpandSELECT()
980 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
981 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) in ExpandSEXTINREG()
991 SDValue Op = DAG.getNode(ISD::SHL, DL, VT, Node->getOperand(0), ShiftSz); in ExpandSEXTINREG()
992 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
1013 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1028 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
1040 SDValue Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src); in ExpandSIGN_EXTEND_VECTOR_INREG()
1048 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
1049 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1072 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
1088 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG()
1114 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0)); in ExpandBSWAP()
1116 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBSWAP()
1121 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBSWAP()
1122 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBSWAP()
1123 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) && in ExpandBSWAP()
1124 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT)) in ExpandBSWAP()
1142 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType())) { in ExpandBITREVERSE()
1158 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) || in ExpandBITREVERSE()
1159 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) && in ExpandBITREVERSE()
1160 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && in ExpandBITREVERSE()
1161 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) && in ExpandBITREVERSE()
1162 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) { in ExpandBITREVERSE()
1164 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0)); in ExpandBITREVERSE()
1167 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op); in ExpandBITREVERSE()
1168 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBITREVERSE()
1176 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBITREVERSE()
1177 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBITREVERSE()
1178 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) && in ExpandBITREVERSE()
1179 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT)) { in ExpandBITREVERSE()
1204 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || in ExpandVSELECT()
1205 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || in ExpandVSELECT()
1206 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand) in ExpandVSELECT()
1228 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); in ExpandVSELECT()
1229 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
1233 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); in ExpandVSELECT()
1234 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
1235 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
1236 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val); in ExpandVSELECT()
1253 if (TLI.getOperationAction(ISD::VP_AND, VT) == TargetLowering::Expand || in ExpandVP_SELECT()
1254 TLI.getOperationAction(ISD::VP_XOR, VT) == TargetLowering::Expand || in ExpandVP_SELECT()
1255 TLI.getOperationAction(ISD::VP_OR, VT) == TargetLowering::Expand) in ExpandVP_SELECT()
1263 SDValue NotMask = DAG.getNode(ISD::VP_XOR, DL, VT, Mask, Ones, Mask, EVL); in ExpandVP_SELECT()
1265 Op1 = DAG.getNode(ISD::VP_AND, DL, VT, Op1, Mask, Mask, EVL); in ExpandVP_SELECT()
1266 Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Mask, EVL); in ExpandVP_SELECT()
1267 return DAG.getNode(ISD::VP_OR, DL, VT, Op1, Op2, Mask, EVL); in ExpandVP_SELECT()
1290 !TLI.isOperationLegalOrCustom(ISD::BUILD_VECTOR, EVLVecVT)) || in ExpandVP_MERGE()
1292 (!TLI.isOperationLegalOrCustom(ISD::STEP_VECTOR, EVLVecVT) || in ExpandVP_MERGE()
1293 !TLI.isOperationLegalOrCustom(ISD::SPLAT_VECTOR, EVLVecVT)))) in ExpandVP_MERGE()
1306 DAG.getSetCC(DL, MaskVT, StepVec, SplatEVL, ISD::CondCode::SETULT); in ExpandVP_MERGE()
1308 SDValue FullMask = DAG.getNode(ISD::AND, DL, MaskVT, Mask, EVLMask); in ExpandVP_MERGE()
1351 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) == in ExpandUINT_TO_FLOAT()
1353 (IsStrict && TLI.getOperationAction(ISD::STRICT_SINT_TO_FP, VT) == in ExpandUINT_TO_FLOAT()
1355 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) { in ExpandUINT_TO_FLOAT()
1382 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord); in ExpandUINT_TO_FLOAT()
1383 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Src, HalfWordMask); in ExpandUINT_TO_FLOAT()
1389 SDValue fHI = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL, in ExpandUINT_TO_FLOAT()
1392 fHI = DAG.getNode(ISD::STRICT_FMUL, DL, {Node->getValueType(0), MVT::Other}, in ExpandUINT_TO_FLOAT()
1394 SDValue fLO = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL, in ExpandUINT_TO_FLOAT()
1398 SDValue TF = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, fHI.getValue(1), in ExpandUINT_TO_FLOAT()
1403 DAG.getNode(ISD::STRICT_FADD, DL, {Node->getValueType(0), MVT::Other}, in ExpandUINT_TO_FLOAT()
1414 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI); in ExpandUINT_TO_FLOAT()
1415 fHI = DAG.getNode(ISD::FMUL, DL, Node->getValueType(0), fHI, TWOHW); in ExpandUINT_TO_FLOAT()
1416 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO); in ExpandUINT_TO_FLOAT()
1420 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO)); in ExpandUINT_TO_FLOAT()
1424 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { in ExpandFNEG()
1428 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero, in ExpandFNEG()
1440 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
1441 TLI.isOperationLegalOrCustom(ISD::FADD, VT)) in ExpandFSUB()
1451 bool IsVP = Node->getOpcode() == ISD::VP_SETCC; in ExpandSETCC()
1454 ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get(); in ExpandSETCC()
1480 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC, in ExpandSETCC()
1483 LHS = DAG.getNode(ISD::VP_SETCC, dl, Node->getValueType(0), in ExpandSETCC()
1500 DAG.getNode(ISD::SELECT_CC, dl, VT, LHS, RHS, in ExpandSETCC()
1545 if (Node->getOpcode() == ISD::STRICT_UINT_TO_FP) { in ExpandStrictFPOp()
1549 if (Node->getOpcode() == ISD::STRICT_FP_TO_UINT) { in ExpandStrictFPOp()
1559 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
1577 if (Node->getOpcode() == ISD::STRICT_FSETCC || in UnrollStrictFPOp()
1578 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
1601 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in UnrollStrictFPOp()
1611 if (Node->getOpcode() == ISD::STRICT_FSETCC || in UnrollStrictFPOp()
1612 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
1622 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OpChains); in UnrollStrictFPOp()
1639 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
1641 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
1643 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()