[DAG] extractShiftForRotate - replace assertion for shift opcode with an early-out

We feed the result from the first extractShiftForRotate call into the second, and that result might no longer be a

[DAG] extractShiftForRotate - replace assertion for shift opcode with an early-out

We feed the result from the first extractShiftForRotate call into the second, and that result might no longer be a shift op (usually due to constant folding).

NOTE: We REALLY need to stop creating nodes on the fly inside extractShiftForRotate!

Fixes Issue #57474

(cherry picked from commit eaede4b5b7cfc13ca0e484b4cb25b2f751d86fd9)

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[DAG] MatchRotate - bail if we fail to match a shl/srl pair

extractShiftForRotate may fail to return canonicalized shifts due to constant folding or other simplification that can occur in getNode()

[DAG] MatchRotate - bail if we fail to match a shl/srl pair

extractShiftForRotate may fail to return canonicalized shifts due to constant folding or other simplification that can occur in getNode()

Fixes Issue #57283

(cherry picked from commit e624f8a3bb88075493dec521408993ea0ef7bde0)

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[DAG] Ensure more Legal BUILD_VECTOR elements types in shuffle->And combine

This is a followup to D131350, which caused another problem for i64
types being split into i32 on i32 targets. This patch

[DAG] Ensure more Legal BUILD_VECTOR elements types in shuffle->And combine

This is a followup to D131350, which caused another problem for i64
types being split into i32 on i32 targets. This patch tries to make sure
that either Illegal types are OK, or that the element types of a
buildvector are legal and bigger than or equal to the size of the
original elements.

Differential Revision: https://reviews.llvm.org/D131883

(cherry picked from commit dfc95bab078297b1564c1ac757b1ac093d125b2d)

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[DAGCombine] Check zext legality in zext-extract-extend combine

Discussed in D131503.

Fix to D130782.

(cherry picked from commit 898699831b5490d88b993593e5cb415fb2d1983a)

[DAG] Ensure Legal BUILD_VECTOR elements types in shuffle->And combine

D129150 added a combine from shuffles to And that creates a BUILD_VECTOR
of constant elements. We need to ensure that the eleme

[DAG] Ensure Legal BUILD_VECTOR elements types in shuffle->And combine

D129150 added a combine from shuffles to And that creates a BUILD_VECTOR
of constant elements. We need to ensure that the elements are of a legal
type, to prevent asserts during lowering.

Fixes #56970.

Differential Revision: https://reviews.llvm.org/D131350

(cherry picked from commit 061e0189a3dab6b1831a80d489ff1b15ad93aafb)

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[DAGCombiner] Extend visitAND to include EXTRACT_SUBVECTOR

Eliminate an AND by redefining an anyext|sext|zext.

(and (extract_subvector (anyext|sext|zext v) _) iN_mask)
=> (extract_subvector

[DAGCombiner] Extend visitAND to include EXTRACT_SUBVECTOR

Eliminate an AND by redefining an anyext|sext|zext.

(and (extract_subvector (anyext|sext|zext v) _) iN_mask)
=> (extract_subvector (zeroext_iN v))

Differential Revision: https://reviews.llvm.org/D130782

(cherry picked from commit 41119a0f520d07a438f7434f17ce63cc3a942d1b)

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[DAG] matchRotateSub - ensure the (pre-extended) shift amount is wide enough for the amount mask (PR56859)

matchRotateSub is given shift amounts that will already have stripped any/zero-extend nodes

[DAG] matchRotateSub - ensure the (pre-extended) shift amount is wide enough for the amount mask (PR56859)

matchRotateSub is given shift amounts that will already have stripped any/zero-extend nodes from - so make sure those values are wide enough to take a mask.

(cherry picked from commit b651fdff79027064071db7c1d0250553e3e6a232)

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[DAG] matchRotateSub - set demanded bits to the shift amount type size, not the shift result size.

This should fix a report on D130251 of an assert due to a bitwidth mismatch in APInt::isSubSetOf

[DAGCombine] Mask doesn't have to be (EltSize - 1) exactly when combining rotation

I think what we need is the least Log2(EltSize) significant bits are known to be ones.

Reviewed By: RKSimon

Diffe

[DAGCombine] Mask doesn't have to be (EltSize - 1) exactly when combining rotation

I think what we need is the least Log2(EltSize) significant bits are known to be ones.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D130251

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Reassoc FMF should not optimize FMA(a, 0, b) to (b)

Optimizing (a * 0 + b) to (b) requires assuming that a is finite and not
NaN. DAGCombiner will do this optimization when the reassoc fast math
fla

Reassoc FMF should not optimize FMA(a, 0, b) to (b)

Optimizing (a * 0 + b) to (b) requires assuming that a is finite and not
NaN. DAGCombiner will do this optimization when the reassoc fast math
flag is set, which is not correct. Change DAGCombiner to only consider
UnsafeMath for this optimization.

Differential Revision: https://reviews.llvm.org/D130232

Co-authored-by: Andrea Faulds <[email protected]>

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[DAGCombiner] Teach scalarizeExtractedBinop to support scalable splat.

This patch supports the scalable splat part for scalarizeExtractedBinop.

Differential Revision: https://reviews.llvm.org/D1297

[DAGCombiner] Teach scalarizeExtractedBinop to support scalable splat.

This patch supports the scalable splat part for scalarizeExtractedBinop.

Differential Revision: https://reviews.llvm.org/D129725

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[DAG] visitSMUL_LOHI/visitUMUL_LOHI - ensure we canonicalize constants to the RHS

[DAG] Move OR(AND(X,C1),AND(OR(X,Y),C2)) -> OR(AND(X,OR(C1,C2)),AND(Y,C2)) fold to SimplifyDemandedBits

This will fix the SystemZ v3i31 memcpy regression in D77804 (with the help of D129765 as well.

[DAG] Move OR(AND(X,C1),AND(OR(X,Y),C2)) -> OR(AND(X,OR(C1,C2)),AND(Y,C2)) fold to SimplifyDemandedBits

This will fix the SystemZ v3i31 memcpy regression in D77804 (with the help of D129765 as well....).

It should also allow us to /bend/ the oneuse limitation for cases where we can use demanded bits to safely peek though multiple uses of the AND ops.

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[DAGCombiner] Simplify code around call to reduceLoadWidth in visitAND. NFC

We were looking for loads or any_extend+load. reduceLoadWidth
hasn't known how to look through such an any_extend to find

[DAGCombiner] Simplify code around call to reduceLoadWidth in visitAND. NFC

We were looking for loads or any_extend+load. reduceLoadWidth
hasn't known how to look through such an any_extend to find the
load since D40667 almost 5 years ago.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D130333

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[AArch64] Emit vector FP cmp when LE is used with fast-math

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D130093

recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."

With fix for AArch64 and Hexgon test cases.

[llvm][SVE] Remove redundant and when comparing against extending load

When determining if an `and` should be merged into an extending load
the constant argument to the `and` is currently not checke

[llvm][SVE] Remove redundant and when comparing against extending load

When determining if an `and` should be merged into an extending load
the constant argument to the `and` is currently not checked if the
argument requires truncation. This prevents the combine happening when
the vector width is half the normal available vector width for SVE VLA
vectors.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D129281

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[DAG] Call SimplifyDemandedBits from ISD::MUL nodes

Noticed while triaging D129765.

Revert "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."

This reverts commit 58dfaaaace4ea75ab3588a6e738f2cf58ebf77c2.

Massive AARCH test failures in buildbot.

[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat.

This revision supports to scalarize a binary operation of two scalable splat vectors.

Reviewed By: RKSimon

Differential Revision:

[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat.

This revision supports to scalarize a binary operation of two scalable splat vectors.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D122791

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[SDAG] Remove single-result restriction on commutative CSE

The DAG Combiner unnecessarily restricts commutative CSE
to nodes with a single result value. This commit removes
that restriction.

Signed

[SDAG] Remove single-result restriction on commutative CSE

The DAG Combiner unnecessarily restricts commutative CSE
to nodes with a single result value. This commit removes
that restriction.

Signed-off-by: Itay Bookstein <[email protected]>

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D129666

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[DAG] Fold (or (and X, C1), (and (or X, Y), C2)) -> (or (and X, C1|C2), (and Y, C2))

Pulled out of D77804

Alive2: https://alive2.llvm.org/ce/z/g61VRe

[CodeGen] Qualify auto variables in for loops (NFC)

[SDAG] narrow truncated sign_extend_inreg

trunc (sign_ext_inreg X, iM) to iN --> sign_ext_inreg (trunc X to iN), iM

There are improvements on existing tests from this, and there are a pair
of large

[SDAG] narrow truncated sign_extend_inreg

trunc (sign_ext_inreg X, iM) to iN --> sign_ext_inreg (trunc X to iN), iM

There are improvements on existing tests from this, and there are a pair
of large regressions in D127115 for Thumb2 caused by not folding this
pattern.

Differential Revision: https://reviews.llvm.org/D129890

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[DAG] visitINSERT_VECTOR_ELT - refactor BUILD_VECTOR creation from INSERT_VECTOR_ELT chain.

D127595 added the ability to recurse up a (one-use) INSERT_VECTOR_ELT chain to create a BUILD_VECTOR befor

[DAG] visitINSERT_VECTOR_ELT - refactor BUILD_VECTOR creation from INSERT_VECTOR_ELT chain.

D127595 added the ability to recurse up a (one-use) INSERT_VECTOR_ELT chain to create a BUILD_VECTOR before other combines manage to break the chain, something that is particularly bad in D127115.

The patch generalises this so it doesn't have to build the chain starting from the last element insertion, instead it can now start from any insertion and will recurse up the chain until it finds all elements or finds a UNDEF/BUILD_VECTOR/SCALAR_TO_VECTOR which represents that start of the chain.

Fixes several regressions in D127115

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