Home
last modified time | relevance | path

Searched refs:getReg (Results 1 – 25 of 677) sorted by relevance

12345678910>>...28

/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DConstantFoldingTest.cpp85 MIBCst2.getReg(0), *MRI); in TEST_F()
90 MIBFCst2.getReg(0), *MRI); in TEST_F()
97 MIBCst2.getReg(0), *MRI); in TEST_F()
102 MIBFCst1.getReg(0), *MRI); in TEST_F()
109 MIBCst2.getReg(0), *MRI); in TEST_F()
114 MIBCst2.getReg(0), *MRI); in TEST_F()
121 MIBCst2.getReg(0), *MRI); in TEST_F()
126 MIBCst2.getReg(0), *MRI); in TEST_F()
133 MIBCst2.getReg(0), *MRI); in TEST_F()
145 MIBCst2.getReg(0), *MRI); in TEST_F()
[all …]
H A DPatternMatchTest.cpp51 EXPECT_EQ(Src0->VReg, MIBCst.getReg(0)); in TEST_F()
130 EXPECT_EQ(Src0, MIBAdd.getReg(0)); in TEST_F()
204 match = mi_match(Shl.getReg(0), *MRI, in TEST_F()
345 EXPECT_EQ(Src, Copy0s32.getReg(0)); in TEST_F()
349 EXPECT_EQ(Src, Copy0s32.getReg(0)); in TEST_F()
408 EXPECT_EQ(Src0, MIBTrunc.getReg(0)); in TEST_F()
412 EXPECT_EQ(Src0, MIBTrunc.getReg(0)); in TEST_F()
416 EXPECT_EQ(Src0, MIBTrunc.getReg(0)); in TEST_F()
482 mi_match(MIBAdd.getReg(0), *MRI, in TEST_F()
501 MIBAdd.getReg(0), *MRI, in TEST_F()
[all …]
H A DKnownBitsVectorTest.cpp35 Register SrcReg = FinalCopy->getOperand(1).getReg(); in TEST_F()
76 Register SrcReg = FinalCopy->getOperand(1).getReg(); in TEST_F()
77 Register DstReg = FinalCopy->getOperand(0).getReg(); in TEST_F()
112 Register SrcReg = FinalCopy->getOperand(1).getReg(); in TEST_F()
1054 SrcReg = Copy->getOperand(1).getReg(); in TEST_F()
1061 SrcReg = Copy->getOperand(1).getReg(); in TEST_F()
1068 SrcReg = Copy->getOperand(1).getReg(); in TEST_F()
1500 SrcReg = Copy->getOperand(1).getReg(); in TEST_F()
1508 SrcReg = Copy->getOperand(1).getReg(); in TEST_F()
1516 SrcReg = Copy->getOperand(1).getReg(); in TEST_F()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
436 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
471 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
507 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
545 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
576 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp811 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
1182 {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()}); in applyCombineDivRem()
2370 return MOP1.getReg() == MOP2.getReg(); in matchEqualDefs()
5150 {FpExtX.getReg(0), FpExtY.getReg(0), RHS.Reg}); in matchCombineFAddFpExtFMulToFMadOrFMA()
5165 {FpExtX.getReg(0), FpExtY.getReg(0), LHS.Reg}); in matchCombineFAddFpExtFMulToFMadOrFMA()
5406 B.buildFNeg(DstTy, RHS.MI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFMulToFMadOrFMA()
5439 B.buildFNeg(DstTy, FMulMI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFNegFMulToFMadOrFMA()
5485 B.buildFPExt(DstTy, FMulMI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
5487 B.buildFPExt(DstTy, FMulMI->getOperand(2).getReg()).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
5501 B.buildFPExt(DstTy, FMulMI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
[all …]
H A DGISelKnownBits.cpp59 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
226 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
329 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(), in computeKnownBitsImpl()
454 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
519 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
580 if (MI.getOperand(1).getReg() == R) { in computeKnownBitsImpl()
640 MRI.getType(Src.getReg()).isValid()) { in computeNumSignBits()
648 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
656 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
680 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
[all …]
H A DLegalizerHelper.cpp1008 MIRBuilder.buildFreeze(NarrowTy, Unmerge.getReg(i)).getReg(0)); in narrowScalar()
1331 .getReg(0); in narrowScalar()
1348 .getReg(0)); in narrowScalar()
1356 .getReg(0)); in narrowScalar()
1437 MO.setReg(ExtB.getReg(0)); in widenScalarSrc()
1444 MO.setReg(ExtB.getReg(0)); in narrowScalarSrc()
1904 .getReg(0); in widenScalarAddSubOverflow()
3576 .getReg(0); in clampDynamicVectorIndex()
4501 .getReg(0); in fewerElementsVectorReductions()
4528 .getReg(0); in fewerElementsVectorReductions()
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/llvm/
H A Dprefer-register-over-unsigned.cpp20 llvm::Register getReg();
24 unsigned Reg1 = getReg(); in apply_1()
32 unsigned Reg2 = getReg(); in apply_2()
44 unsigned Reg3 = getReg(); in apply_3()
59 Register Reg2 = getReg(); in done_2()
67 Register Reg3 = getReg(); in done_3()
97 fn1(getReg()); in do_nothing_4()
104 fn2(getReg()); in do_nothing_5()
111 Register Reg6{getReg()}; in do_nothing_6()
120 Reg7.Reg = getReg(); in do_nothing_7()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp161 Register Reg = Op.getReg(); in applyBank()
926 .getReg(0); in executeInWaterfallLoop()
1639 .getReg(0); in applyMappingMAD_64_32()
1672 DstLo = AddLo.getReg(0); in applyMappingMAD_64_32()
1678 DstHi = AddHi.getReg(0); in applyMappingMAD_64_32()
1735 return std::make_pair(ExtLo.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1741 return std::make_pair(ExtLo.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1745 return std::make_pair(Bitcast.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
2412 B.buildBuildVectorTrunc(DstReg, {Lo.getReg(0), Hi.getReg(0)}); in applyMappingImpl()
3317 Register Reg = MO.getReg(); in getMappingType()
[all …]
H A DSIOptimizeExecMasking.cpp102 return MI.getOperand(0).getReg(); in isCopyFromExec()
117 return MI.getOperand(1).getReg(); in isCopyToExec()
142 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
145 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
158 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
161 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
541 .addReg(OtherOp->getReg()); in optimizeExecSequence()
652 {Exec, SaveExecSrc0->getReg()}); in tryRecordVCmpxAndSaveexecSequence()
719 (XorSrc0.getReg() == Exec || XorSrc1.getReg() == Exec)) { in tryRecordOrSaveexecXorSequence()
733 if ((XorSrc0.getReg() == Exec && XorSrc1.getReg() == OrDst.getReg()) || in tryRecordOrSaveexecXorSequence()
[all …]
H A DAMDGPULegalizerInfo.cpp2220 auto X = B.buildXor(S32, Unmerge.getReg(0), Unmerge.getReg(1)); in legalizeITOFP()
3525 return {ResultLo.getReg(0), ResultHi.getReg(0)}; in emitReciprocalU64()
4333 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0)); in handleD16VData()
4338 .getReg(0); in handleD16VData()
4348 .getReg(0); in handleD16VData()
4369 .getReg(0); in handleD16VData()
4601 Repack.push_back(B.buildTrunc(EltTy, Unmerge.getReg(I)).getReg(0)); in legalizeBufferLoad()
5439 V3S32, {Unmerge.getReg(0), Unmerge.getReg(1), Unmerge.getReg(2)}); in legalizeBVHIntrinsic()
5490 B.buildMerge(R1, {UnmergeRayDir.getReg(0), UnmergeRayDir.getReg(1)}); in legalizeBVHIntrinsic()
5491 B.buildMerge(R2, {UnmergeRayDir.getReg(2), UnmergeRayInvDir.getReg(0)}); in legalizeBVHIntrinsic()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp257 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
258 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
278 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
279 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
294 Register V1 = MI.getOperand(1).getReg(); in matchZip()
715 .getReg(0); in applyDupLane()
877 .getReg(0); in getVectorFCMP()
884 .getReg(0); in getVectorFCMP()
891 .getReg(0); in getVectorFCMP()
898 .getReg(0); in getVectorFCMP()
[all …]
H A DAArch64InstructionSelector.cpp656 return RegSequence.getReg(0); in createTuple()
1593 emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, in selectCompareBranchFedByFCmp()
2100 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()}); in earlySelectSHL()
2840 .getReg(0); in select()
3288 .getReg(0); in select()
3385 if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(), MIB, in select()
5056 emitSelect(I.getOperand(0).getReg(), I.getOperand(2).getReg(), in tryOptSelect()
5184 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()}); in selectShuffleVector()
5613 {I.getOperand(0).getReg(), I.getOperand(1).getReg()}, in selectIntrinsicWithSideEffects()
6629 return Copy.getReg(0); in moveScalarRegClass()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
117 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
119 .addReg(MI->getOperand(3).getReg()); in lowerSubvectorLoad()
127 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
129 .addReg(MI->getOperand(3).getReg()) in lowerSubvectorStore()
182 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
183 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
191 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
192 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
[all …]
H A DSystemZTargetStreamer.h35 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
36 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
39 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
40 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp534 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
548 TRI->regsOverlap(Def, MIDef.getReg())) in hasOverlappingMultipleDef()
576 if (!MOUse.getReg()) in forwardUses()
594 Register CopySrcReg = CopySrc.getReg(); in forwardUses()
597 if (MOUse.getReg() != CopyDstReg) { in forwardUses()
738 MCRegister Reg = MO.getReg().asMCReg(); in ForwardCopyPropagateBlock()
757 Register Reg = MO.getReg(); in ForwardCopyPropagateBlock()
878 if (!MODef.getReg()) in propagateDefs()
895 if (MODef.getReg() != Src) in propagateDefs()
951 MCRegister Reg = MO.getReg().asMCReg(); in BackwardCopyPropagateBlock()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp111 printRegName(O, Dst.getReg()); in printInst()
113 printRegName(O, MO1.getReg()); in printInst()
116 printRegName(O, MO2.getReg()); in printInst()
316 unsigned Reg = Op.getReg(); in printOperand()
403 printRegName(O, MO1.getReg()); in printSORegRegOperand()
443 if (!MO2.getReg()) { in printAM2PreOrOffsetIndexOp()
512 if (!MO1.getReg()) { in printAddrMode2OffsetOperand()
541 if (MO2.getReg()) { in printAM3PreOrOffsetIndexOp()
582 if (MO1.getReg()) { in printAddrMode3OffsetOperand()
728 if (MO.getReg() == 0) in printAddrMode6OffsetOperand()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h32 Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); } in getReg() function
44 Register getPointerReg() const { return getOperand(1).getReg(); } in getPointerReg()
82 Register getDstReg() const { return getOperand(0).getReg(); } in getDstReg()
133 Register getValueReg() const { return getOperand(0).getReg(); } in getValueReg()
202 Register getBaseReg() const { return getReg(1); } in getBaseReg()
203 Register getOffsetReg() const { return getReg(2); } in getOffsetReg()
221 Register getCondReg() const { return getReg(1); } in getCondReg()
222 Register getTrueReg() const { return getReg(2); } in getTrueReg()
223 Register getFalseReg() const { return getReg(3); } in getFalseReg()
236 Register getLHSReg() const { return getReg(2); } in getLHSReg()
[all …]
H A DLegalizationArtifactCombiner.h63 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
117 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
544 if (Def.getReg() == SearchDef) in getDefIndex()
628 return BV.getReg(0); in findValueFromBuildVector()
647 return BV.getReg(StartSrcIdx); in findValueFromBuildVector()
738 if (MO.getReg() == DefReg) in findValueFromDefImpl()
790 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs()
824 LLT DestTy = MRI.getType(MI.getReg(0)); in tryCombineUnmergeValues()
868 Register Def = MI.getReg(I); in tryCombineUnmergeValues()
970 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeValues()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp76 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
108 return Register::isVirtualRegister(RA.getReg()) || in checkOpConstraints()
109 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
118 if (!Register::isVirtualRegister(RT.getReg())) in checkOpConstraints()
122 (RT.getReg() == PPC::ZERO || RT.getReg() == PPC::ZERO8)) in checkOpConstraints()
172 (!Register::isVirtualRegister(BT.getReg()) && BT.getReg() != PPC::CR0)) in checkOpConstraints()
184 (!Register::isVirtualRegister(BT.getReg()) && BT.getReg() != PPC::CR0)) in checkOpConstraints()
210 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
221 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
H A DPPCMIPeephole.cpp166 Register Reg = Op->getReg(); in getVRegDefOrNull()
560 MI.getOperand(0).getReg()) in simplifyCode()
590 MI.getOperand(0).getReg()) in simplifyCode()
678 MI.getOperand(0).getReg()) in simplifyCode()
865 MI.getOperand(0).getReg()) in simplifyCode()
912 MI.getOperand(0).getReg()) in simplifyCode()
965 Register DominatorReg = Op2.getReg(); in simplifyCode()
1002 MI.getOperand(0).getReg()) in simplifyCode()
1170 return Phi->getOperand(I-1).getReg(); in getIncomingRegForBlock()
1191 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp238 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
283 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
296 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
303 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
363 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
377 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
379 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
401 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
423 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
438 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp58 GR->add(GV, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
86 Register Reg = MI->getOperand(2).getReg(); in addConstantsToTrack()
130 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
152 Register Reg = MI->getOperand(0).getReg(); in propagateSPIRVType()
235 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
251 Register Reg = MI.getOperand(0).getReg(); in generateAssignInstrs()
366 Register SrcReg = MI.getOperand(1).getReg(); in processInstrsWithTypeFolding()
369 Register DstReg = MI.getOperand(0).getReg(); in processInstrsWithTypeFolding()
407 Register Reg = MI.getOperand(1).getReg(); in processSwitches()
417 Register Dst = MI.getOperand(0).getReg(); in processSwitches()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp213 Register R = Op.getReg(); in isFixedInstr()
261 Register T = MO.getReg(); in partitionRegisters()
501 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
537 Register R = MD.getReg(); in collectIndRegsForLoop()
601 Register R = Op.getReg(); in createHalfInstr()
675 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
809 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
945 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
959 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
1078 Register R = Op.getReg(); in replaceSubregUses()
[all …]

12345678910>>...28