Lines Matching refs:getReg
213 Register R = Op.getReg(); in isFixedInstr()
261 Register T = MO.getReg(); in partitionRegisters()
374 Register Rs = MI->getOperand(1).getReg(); in profit()
375 Register Rt = MI->getOperand(2).getReg(); in profit()
442 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
501 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
509 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
537 Register R = MD.getReg(); in collectIndRegsForLoop()
553 Register T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
601 Register R = Op.getReg(); in createHalfInstr()
641 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
648 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
651 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
657 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
661 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
671 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); in splitMemRef()
675 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
677 MRI->replaceRegWith(UpdOp.getReg(), NewR); in splitMemRef()
705 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitImmediate()
732 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitCombine()
741 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
749 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
761 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitExt()
767 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
769 .addReg(Op1.getReg(), RS, Op1.getSubReg()) in splitExt()
785 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitShift()
807 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
809 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
832 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
835 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
838 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift()
844 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift()
850 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
855 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR) in splitShift()
860 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
866 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)); in splitShift()
872 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
878 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
881 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR); in splitShift()
884 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)) in splitShift()
889 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
910 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitAslOr()
942 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
943 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR); in splitAslOr()
945 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
946 .addReg(Op2.getReg(), RS2, HiSR); in splitAslOr()
949 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
950 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
954 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
959 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
963 .addReg(Op2.getReg(), RS2, HiSR) in splitAslOr()
971 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()
973 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
974 .addReg(Op2.getReg(), RS2, LoSR); in splitAslOr()
982 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()
984 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
985 .addReg(Op2.getReg(), RS2, LoSR) in splitAslOr()
1001 Register DstR = MI->getOperand(0).getReg(); in splitInstr()
1078 Register R = Op.getReg(); in replaceSubregUses()
1103 Register R = Op.getReg(); in collapseRegPairs()