Lines Matching refs:getReg
222 Register Dst = MI.getOperand(0).getReg(); in matchREV()
223 Register Src = MI.getOperand(1).getReg(); in matchREV()
252 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
257 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
258 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
273 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
278 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
279 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
289 Register Dst = MI.getOperand(0).getReg(); in matchZip()
294 Register V1 = MI.getOperand(1).getReg(); in matchZip()
295 Register V2 = MI.getOperand(2).getReg(); in matchZip()
322 MI.getOperand(1).getReg(), MRI); in matchDupFromInsertVectorElt()
326 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), in matchDupFromInsertVectorElt()
331 if (!mi_match(InsMI->getOperand(3).getReg(), MRI, m_ZeroInt())) in matchDupFromInsertVectorElt()
334 MatchInfo = ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), in matchDupFromInsertVectorElt()
335 {InsMI->getOperand(2).getReg()}); in matchDupFromInsertVectorElt()
347 MI.getOperand(1).getReg(), MRI); in matchDupFromBuildVector()
350 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg(); in matchDupFromBuildVector()
352 ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), {Reg}); in matchDupFromBuildVector()
376 Register Dst = MI.getOperand(0).getReg(); in matchEXT()
384 Register V1 = MI.getOperand(1).getReg(); in matchEXT()
385 Register V2 = MI.getOperand(2).getReg(); in matchEXT()
433 Register Dst = MI.getOperand(0).getReg(); in matchINS()
441 Register Left = MI.getOperand(1).getReg(); in matchINS()
442 Register Right = MI.getOperand(2).getReg(); in matchINS()
460 Register Dst = MI.getOperand(0).getReg(); in applyINS()
493 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in matchVAshrLshrImm()
496 return isVShiftRImm(MI.getOperand(2).getReg(), MRI, Ty, Imm); in matchVAshrLshrImm()
620 Register RHS = MI.getOperand(3).getReg(); in matchAdjustICmpImmAndPred()
635 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()), in applyAdjustICmpImmAndPred()
638 RHS.setReg(Cst->getOperand(0).getReg()); in applyAdjustICmpImmAndPred()
647 Register Src1Reg = MI.getOperand(1).getReg(); in matchDupLane()
649 const LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchDupLane()
699 Register Src1Reg = MI.getOperand(1).getReg(); in applyDupLane()
705 Register DupSrc = MI.getOperand(1).getReg(); in applyDupLane()
709 assert(MRI.getType(MI.getOperand(0).getReg()).getNumElements() == 2 && in applyDupLane()
714 {Src1Reg, Undef.getReg(0)}) in applyDupLane()
715 .getReg(0); in applyDupLane()
717 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane}); in applyDupLane()
739 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
740 {MI.getOperand(1).getReg()}); in applyBuildVectorToDup()
760 getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI); in getCmpOperandFoldingProfit()
777 getIConstantVRegValWithLookThrough(Def->getOperand(2).getReg(), MRI); in getCmpOperandFoldingProfit()
782 getDefIgnoringCopies(Def->getOperand(1).getReg(), MRI); in getCmpOperandFoldingProfit()
790 LLT Ty = MRI.getType(Def->getOperand(0).getReg()); in getCmpOperandFoldingProfit()
816 Register RHS = MI.getOperand(3).getReg(); in trySwapICmpOperands()
821 Register LHS = MI.getOperand(2).getReg(); in trySwapICmpOperands()
825 return isCMN(Def, Pred, MRI) ? Def->getOperand(2).getReg() : Reg; in trySwapICmpOperands()
842 Register LHS = MI.getOperand(2).getReg(); in applySwapICmpOperands()
843 Register RHS = MI.getOperand(3).getReg(); in applySwapICmpOperands()
870 return MIB.buildNot(DstTy, FCmp).getReg(0); in getVectorFCMP()
875 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
877 .getReg(0); in getVectorFCMP()
882 ? MIB.buildInstr(AArch64::G_FCMGEZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
884 .getReg(0); in getVectorFCMP()
889 ? MIB.buildInstr(AArch64::G_FCMGTZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
891 .getReg(0); in getVectorFCMP()
896 ? MIB.buildInstr(AArch64::G_FCMLEZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
898 .getReg(0); in getVectorFCMP()
903 ? MIB.buildInstr(AArch64::G_FCMLTZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
905 .getReg(0); in getVectorFCMP()
915 Register Dst = MI.getOperand(0).getReg(); in lowerVectorFCMP()
921 Register LHS = MI.getOperand(2).getReg(); in lowerVectorFCMP()
926 Register RHS = MI.getOperand(3).getReg(); in lowerVectorFCMP()
946 CmpRes = MIB.buildOr(DstTy, Cmp1Dst, Cmp2Dst).getReg(0); in lowerVectorFCMP()
949 CmpRes = MIB.buildNot(DstTy, CmpRes).getReg(0); in lowerVectorFCMP()
958 Register DstReg = MI.getOperand(0).getReg(); in matchFormTruncstore()