Lines Matching refs:getReg
656 return RegSequence.getReg(0); in createTuple()
689 getIConstantVRegValWithLookThrough(Root.getReg(), MRI, true); in getImmedFromMO()
708 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
726 if (!Register::isVirtualRegister(MO.getReg())) { in unsupportedBinOp()
731 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
870 RegOp.setReg(SubRegCopy.getReg(0)); in copySubReg()
874 if (!Register::isPhysicalRegister(I.getOperand(0).getReg())) in copySubReg()
875 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
888 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy()
889 Register SrcReg = I.getOperand(1).getReg(); in getRegClassesForCopy()
913 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
914 Register SrcReg = I.getOperand(1).getReg(); in selectCopy()
950 copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg); in selectCopy()
1368 !MRI.hasOneNonDBGUse(MI->getOperand(0).getReg())) in getTestBitReg()
1380 Register NextReg = MI->getOperand(1).getReg(); in getTestBitReg()
1398 TestReg = MI->getOperand(1).getReg(); in getTestBitReg()
1399 Register ConstantReg = MI->getOperand(2).getReg(); in getTestBitReg()
1419 TestReg = MI->getOperand(1).getReg(); in getTestBitReg()
1421 getIConstantVRegValWithLookThrough(MI->getOperand(2).getReg(), MRI); in getTestBitReg()
1550 AndInst.getOperand(2).getReg(), *MIB.getMRI()); in tryOptAndIntoCompareBranch()
1558 Register TestReg = AndInst.getOperand(1).getReg(); in tryOptAndIntoCompareBranch()
1593 emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, in selectCompareBranchFedByFCmp()
1621 Register LHS = ICmp.getOperand(2).getReg(); in tryOptCompareBranchFedByICmp()
1622 Register RHS = ICmp.getOperand(3).getReg(); in tryOptCompareBranchFedByICmp()
1711 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch()
1788 Register DstReg = I.getOperand(0).getReg(); in selectVectorSHL()
1790 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorSHL()
1791 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorSHL()
1834 Register DstReg = I.getOperand(0).getReg(); in selectVectorAshrLshr()
1836 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorAshrLshr()
1837 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorAshrLshr()
1897 Register ListReg = I.getOperand(0).getReg(); in selectVaStartDarwin()
1952 Register DstReg = BuildMovK(MovZ.getReg(0), in materializeLargeCMVal()
1955 BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg()); in materializeLargeCMVal()
1967 if (MRI.getType(SrcOp.getReg()).isPointer()) { in preISelLower()
1972 Register NewSrc = Copy.getReg(0); in preISelLower()
1986 Register DstReg = I.getOperand(0).getReg(); in preISelLower()
1995 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in preISelLower()
1998 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); in preISelLower()
1999 MRI.setType(I.getOperand(0).getReg(), in preISelLower()
2001 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower()
2002 I.getOperand(1).setReg(NewSrc.getReg(0)); in preISelLower()
2011 Register SrcReg = I.getOperand(1).getReg(); in preISelLower()
2013 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in preISelLower()
2042 Register DstReg = I.getOperand(0).getReg(); in convertPtrAddToAdd()
2043 Register AddOp1Reg = I.getOperand(1).getReg(); in convertPtrAddToAdd()
2053 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID)); in convertPtrAddToAdd()
2055 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in convertPtrAddToAdd()
2061 I.getOperand(1).setReg(PtrToInt.getReg(0)); in convertPtrAddToAdd()
2070 if (!mi_match(I.getOperand(2).getReg(), MRI, m_Neg(m_Reg(NegatedReg)))) in convertPtrAddToAdd()
2084 auto VRegAndVal = getIConstantVRegVal(MO.getReg(), MRI); in earlySelectSHL()
2088 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in earlySelectSHL()
2100 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()}); in earlySelectSHL()
2128 Register DefDstReg = getSrcRegIgnoringCopies(I.getOperand(0).getReg(), MRI); in contractCrossBankCopyIntoStore()
2132 Register StoreSrcReg = I.getOperand(0).getReg(); in contractCrossBankCopyIntoStore()
2165 Register Src = I.getOperand(1).getReg(); in earlySelect()
2170 Register Dst = I.getOperand(0).getReg(); in earlySelect()
2200 Register DefReg = I.getOperand(0).getReg(); in earlySelect()
2224 Register AddDst = I.getOperand(0).getReg(); in earlySelect()
2225 Register AddLHS = I.getOperand(1).getReg(); in earlySelect()
2226 Register AddRHS = I.getOperand(2).getReg(); in earlySelect()
2251 MRI.getType(Cmp->getOperand(2).getReg()).getSizeInBits() != 64) in earlySelect()
2280 Register Dst = I.getOperand(0).getReg(); in earlySelect()
2351 const Register DefReg = I.getOperand(0).getReg(); in select()
2409 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{}; in select()
2421 getIConstantVRegValWithLookThrough(I.getOperand(2).getReg(), MRI); in select()
2424 getIConstantVRegValWithLookThrough(I.getOperand(3).getReg(), MRI); in select()
2451 MachineInstr *BaseMI = MRI.getVRegDef(I.getOperand(1).getReg()); in select()
2472 Register DstReg = I.getOperand(0).getReg(); in select()
2518 const Register DefReg = I.getOperand(0).getReg(); in select()
2582 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()}); in select()
2622 Register DstReg = I.getOperand(0).getReg(); in select()
2623 Register SrcReg = I.getOperand(1).getReg(); in select()
2676 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) in select()
2678 RBI.constrainGenericRegister(I.getOperand(0).getReg(), in select()
2686 LLT SrcTy = MRI.getType(I.getOperand(2).getReg()); in select()
2687 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in select()
2696 unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); in select()
2711 .addUse(I.getOperand(2).getReg()) in select()
2713 RBI.constrainGenericRegister(I.getOperand(2).getReg(), in select()
2800 Register ValReg = LdSt.getReg(0); in select()
2805 .addReg(I.getOperand(0).getReg(), 0, AArch64::sub_32); in select()
2824 const Register ValReg = LdSt.getReg(0); in select()
2840 .getReg(0); in select()
2852 Register OldDst = LdSt.getReg(0); in select()
2889 Register CurValReg = I.getOperand(0).getReg(); in select()
2905 LoadStore->getOperand(0).getReg(), MRI); in select()
2923 if (MRI.getType(LoadStore->getOperand(0).getReg()).getSizeInBits() != 64) in select()
2928 Register DstReg = LoadStore->getOperand(0).getReg(); in select()
2949 const Register DefReg = I.getOperand(0).getReg(); in select()
2973 if (MRI.getType(I.getOperand(0).getReg()).isVector()) in select()
2978 MRI.getType(I.getOperand(0).getReg()).isVector()) in select()
2986 Register SrcReg = I.getOperand(1).getReg(); in select()
2987 Register ShiftReg = I.getOperand(2).getReg(); in select()
2996 MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in select()
2997 I.getOperand(2).setReg(Trunc.getReg(0)); in select()
3008 const Register DefReg = I.getOperand(0).getReg(); in select()
3024 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2), MIB); in select()
3033 auto OpAndCC = emitOverflowOp(Opcode, I.getOperand(0).getReg(), in select()
3041 emitCSINC(/*Dst=*/I.getOperand(1).getReg(), /*Src1=*/ZReg, /*Src2=*/ZReg, in select()
3048 Register MaskReg = I.getOperand(2).getReg(); in select()
3063 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in select()
3064 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); in select()
3066 const Register DstReg = I.getOperand(0).getReg(); in select()
3067 const Register SrcReg = I.getOperand(1).getReg(); in select()
3142 const Register DstReg = I.getOperand(0).getReg(); in select()
3143 const Register SrcReg = I.getOperand(1).getReg(); in select()
3193 const Register DefReg = I.getOperand(0).getReg(); in select()
3194 Register SrcReg = I.getOperand(1).getReg(); in select()
3288 .getReg(0); in select()
3313 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()), in select()
3314 SrcTy = MRI.getType(I.getOperand(1).getReg()); in select()
3357 if (!emitSelect(Sel.getReg(0), TReg, FReg, AArch64CC::NE, MIB)) in select()
3376 emitCSINC(/*Dst=*/I.getOperand(0).getReg(), /*Src1=*/AArch64::WZR, in select()
3385 if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(), MIB, in select()
3387 !emitCSetForFCmp(I.getOperand(0).getReg(), Pred, MIB)) in select()
3401 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in select()
3402 const Register DstReg = I.getOperand(0).getReg(); in select()
3416 I.getOperand(0).getReg()) in select()
3432 if (RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() != in select()
3435 LLT VecTy = MRI.getType(I.getOperand(0).getReg()); in select()
3484 Register VecReg = I.getOperand(1).getReg(); in selectReduction()
3490 Register DstReg = I.getOperand(0).getReg(); in selectReduction()
3494 .addReg(AddP.getReg(0), 0, AArch64::ssub) in selectReduction()
3495 .getReg(0); in selectReduction()
3556 const Register DstPtrCopy = MRI.cloneVirtualRegister(DstPtr.getReg()); in selectMOPS()
3557 const Register SrcValCopy = MRI.cloneVirtualRegister(SrcOrVal.getReg()); in selectMOPS()
3558 const Register SizeCopy = MRI.cloneVirtualRegister(Size.getReg()); in selectMOPS()
3595 Register JTAddr = I.getOperand(0).getReg(); in selectBrJT()
3597 Register Index = I.getOperand(2).getReg(); in selectBrJT()
3617 Register DstReg = I.getOperand(0).getReg(); in selectJumpTable()
3645 {LoadGOT.getReg(0)}) in selectTLSGlobalValue()
3648 MIB.buildCopy(Register(AArch64::X0), LoadGOT.getReg(0)); in selectTLSGlobalValue()
3657 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0)); in selectTLSGlobalValue()
3658 RBI.constrainGenericRegister(I.getOperand(0).getReg(), AArch64::GPR64RegClass, in selectTLSGlobalValue()
3666 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicTrunc()
3721 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicRound()
3776 Register DstReg = I.getOperand(0).getReg(); in selectVectorICmp()
3778 Register SrcReg = I.getOperand(2).getReg(); in selectVectorICmp()
3779 Register Src2Reg = I.getOperand(3).getReg(); in selectVectorICmp()
3938 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
3975 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in selectMergeValues()
3976 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); in selectMergeValues()
3978 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI); in selectMergeValues()
3987 Register DstReg = I.getOperand(0).getReg(); in selectMergeValues()
3988 Register Src1Reg = I.getOperand(1).getReg(); in selectMergeValues()
3989 Register Src2Reg = I.getOperand(2).getReg(); in selectMergeValues()
3992 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB); in selectMergeValues()
3995 MachineInstr *Ins2MI = emitLaneInsert(DstReg, InsMI->getOperand(0).getReg(), in selectMergeValues()
4017 .addUse(I.getOperand(1).getReg()) in selectMergeValues()
4025 .addUse(I.getOperand(2).getReg()) in selectMergeValues()
4029 .addDef(I.getOperand(0).getReg()) in selectMergeValues()
4118 InsertReg = ScalarToVector->getOperand(0).getReg(); in emitExtractVectorElt()
4134 Register DstReg = I.getOperand(0).getReg(); in selectExtractElt()
4136 const Register SrcReg = I.getOperand(1).getReg(); in selectExtractElt()
4153 auto VRegAndVal = getIConstantVRegValWithLookThrough(LaneIdxOp.getReg(), MRI); in selectExtractElt()
4172 Register SrcReg = I.getOperand(NumElts).getReg(); in selectSplitVectorUnmerge()
4173 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg()); in selectSplitVectorUnmerge()
4185 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI); in selectSplitVectorUnmerge()
4187 Register Dst = I.getOperand(OpIdx).getReg(); in selectSplitVectorUnmerge()
4203 if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() != in selectUnmergeValues()
4205 RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() != in selectUnmergeValues()
4215 Register SrcReg = I.getOperand(NumElts).getReg(); in selectUnmergeValues()
4216 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg()); in selectUnmergeValues()
4285 Register CopyTo = I.getOperand(0).getReg(); in selectUnmergeValues()
4293 Register CopyTo = I.getOperand(LaneIdx).getReg(); in selectUnmergeValues()
4306 MRI.getRegClassOrNull(I.getOperand(1).getReg()); in selectUnmergeValues()
4321 Register Dst = I.getOperand(0).getReg(); in selectConcatVectors()
4322 Register Op1 = I.getOperand(1).getReg(); in selectConcatVectors()
4323 Register Op2 = I.getOperand(2).getReg(); in selectConcatVectors()
4454 auto Ty = MRI.getType(LHS.getReg()); in emitAddSub()
4526 bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32); in emitCMN()
4536 LLT Ty = MRI.getType(LHS.getReg()); in emitTST()
4544 if (auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS.getReg(), MRI)) { in emitTST()
4566 LLT CmpTy = MRI.getType(LHS.getReg()); in emitIntegerCompare()
4574 auto Dst = MRI.cloneVirtualRegister(LHS.getReg()); in emitIntegerCompare()
4699 .buildInstr(InsertOpc, {*Dst}, {WidenedOp1->getOperand(0).getReg()}) in emitVectorConcat()
4701 .addUse(WidenedOp2->getOperand(0).getReg()) in emitVectorConcat()
4779 Register O0 = ValDef->getOperand(1).getReg(); in canEmitConjunction()
4780 Register O1 = ValDef->getOperand(2).getReg(); in canEmitConjunction()
4877 CCOp = ExtraCmp->getOperand(0).getReg(); in emitConjunctionRec()
4887 return emitFPCompare(Cmp->getOperand(2).getReg(), in emitConjunctionRec()
4888 Cmp->getOperand(3).getReg(), MIB); in emitConjunctionRec()
4897 Register LHS = ValDef->getOperand(1).getReg(); in emitConjunctionRec()
4904 Register RHS = ValDef->getOperand(2).getReg(); in emitConjunctionRec()
4957 LHS, OutCC, NegateL, CmpR->getOperand(0).getReg(), RHSCC, MIB); in emitConjunctionRec()
4980 emitSelect(SelI.getReg(0), SelI.getTrueReg(), SelI.getFalseReg(), AArch64CC, MIB); in tryOptSelectConjunction()
5005 MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg()); in tryOptSelect()
5008 Register CondDefReg = CondDef->getOperand(0).getReg(); in tryOptSelect()
5048 if (!emitFPCompare(CondDef->getOperand(2).getReg(), in tryOptSelect()
5049 CondDef->getOperand(3).getReg(), MIB)) { in tryOptSelect()
5056 emitSelect(I.getOperand(0).getReg(), I.getOperand(2).getReg(), in tryOptSelect()
5057 I.getOperand(3).getReg(), CondCode, MIB); in tryOptSelect()
5078 MachineInstr *LHSDef = getDefIgnoringCopies(LHS.getReg(), MRI); in tryFoldIntegerCompare()
5079 MachineInstr *RHSDef = getDefIgnoringCopies(RHS.getReg(), MRI); in tryFoldIntegerCompare()
5116 auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS.getReg(), MRI); in tryFoldIntegerCompare()
5129 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in selectShuffleVector()
5130 Register Src1Reg = I.getOperand(1).getReg(); in selectShuffleVector()
5132 Register Src2Reg = I.getOperand(2).getReg(); in selectShuffleVector()
5180 IndexLoad->getOperand(0).getReg(), MIB); in selectShuffleVector()
5184 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()}); in selectShuffleVector()
5188 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) in selectShuffleVector()
5189 .addReg(TBL1.getReg(0), 0, AArch64::dsub); in selectShuffleVector()
5190 RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI); in selectShuffleVector()
5225 .addUse(InsSub->getOperand(0).getReg()) in emitLaneInsert()
5244 const Register DefReg = MI.getOperand(0).getReg(); in selectUSMovFromExtend()
5252 MI.getOperand(1).getReg(), MRI); in selectUSMovFromExtend()
5254 if (!Extract || !mi_match(Extract->getOperand(2).getReg(), MRI, m_ICst(Lane))) in selectUSMovFromExtend()
5256 Register Src0 = Extract->getOperand(1).getReg(); in selectUSMovFromExtend()
5264 Src0 = ScalarToVector->getOperand(0).getReg(); in selectUSMovFromExtend()
5307 Register DstReg = I.getOperand(0).getReg(); in selectInsertElt()
5312 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt()
5320 Register IdxReg = I.getOperand(3).getReg(); in selectInsertElt()
5327 Register SrcReg = I.getOperand(1).getReg(); in selectInsertElt()
5337 SrcReg = ScalarToVec->getOperand(0).getReg(); in selectInsertElt()
5349 Register DemoteVec = InsMI->getOperand(0).getReg(); in selectInsertElt()
5397 .addReg(Mov.getReg(0), 0, AArch64::dsub); in emitConstantVector()
5411 Dst, *MRI.getRegClass(CPLoad->getOperand(0).getReg()), MRI); in emitConstantVector()
5428 getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI); in tryOptConstantBuildVec()
5433 I.getOperand(Idx).getReg(), MRI))) in tryOptConstantBuildVec()
5440 if (!emitConstantVector(I.getOperand(0).getReg(), CV, MIB, MRI)) in tryOptConstantBuildVec()
5452 Register Dst = I.getOperand(0).getReg(); in tryOptBuildVecToSubregToReg()
5453 Register EltReg = I.getOperand(1).getReg(); in tryOptBuildVecToSubregToReg()
5463 return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(), in tryOptBuildVecToSubregToReg()
5491 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in selectBuildVector()
5492 const LLT EltTy = MRI.getType(I.getOperand(1).getReg()); in selectBuildVector()
5502 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI); in selectBuildVector()
5507 I.getOperand(1).getReg(), MIB); in selectBuildVector()
5511 Register DstVec = ScalarToVec->getOperand(0).getReg(); in selectBuildVector()
5520 PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB, in selectBuildVector()
5522 DstVec = PrevMI->getOperand(0).getReg(); in selectBuildVector()
5548 Register DstReg = I.getOperand(0).getReg(); in selectBuildVector()
5558 PrevMI->getOperand(0).setReg(I.getOperand(0).getReg()); in selectBuildVector()
5573 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in selectVectorLoadIntrinsic()
5578 auto Ptr = I.getOperand(I.getNumOperands() - 1).getReg(); in selectVectorLoadIntrinsic()
5583 Register SelectedLoadDst = Load->getOperand(0).getReg(); in selectVectorLoadIntrinsic()
5613 {I.getOperand(0).getReg(), I.getOperand(1).getReg()}, in selectIntrinsicWithSideEffects()
5630 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicWithSideEffects()
5654 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicWithSideEffects()
5678 Register Src1 = I.getOperand(1).getReg(); in selectIntrinsicWithSideEffects()
5679 Register Src2 = I.getOperand(2).getReg(); in selectIntrinsicWithSideEffects()
5680 Register Ptr = I.getOperand(3).getReg(); in selectIntrinsicWithSideEffects()
5722 Register DstDef = I.getOperand(0).getReg(); in selectIntrinsicWithSideEffects()
5724 Register DstUse = I.getOperand(2).getReg(); in selectIntrinsicWithSideEffects()
5725 Register ValUse = I.getOperand(3).getReg(); in selectIntrinsicWithSideEffects()
5726 Register SizeUse = I.getOperand(4).getReg(); in selectIntrinsicWithSideEffects()
5753 Register DstReg = I.getOperand(0).getReg(); in selectIntrinsic()
5754 Register SrcReg = I.getOperand(2).getReg(); in selectIntrinsic()
5768 RBI.constrainGenericRegister(I.getOperand(2).getReg(), in selectIntrinsic()
5780 if (DstReg != I.getOperand(0).getReg()) { in selectIntrinsic()
5784 RBI.constrainGenericRegister(I.getOperand(0).getReg(), in selectIntrinsic()
5792 Register DstReg = I.getOperand(0).getReg(); in selectIntrinsic()
5793 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic()
5795 Register DiscReg = I.getOperand(4).getReg(); in selectIntrinsic()
5824 Register DstReg = I.getOperand(0).getReg(); in selectIntrinsic()
5879 auto Sub = MIB.buildInstr(AArch64::SUBXri, {I.getOperand(0).getReg()}, in selectIntrinsic()
5991 if (MRI.getType(Root.getReg()).getSizeInBits() == 32) in selectNegArithImmed()
6009 Register DefReg = MI.getOperand(0).getReg(); in isWorthFoldingIntoExtendedReg()
6045 MachineInstr *OffsetInst = MRI.getVRegDef(Offset.getReg()); in selectExtendedSHL()
6054 OffsetInst = MRI.getVRegDef(OffsetInst->getOperand(1).getReg()); in selectExtendedSHL()
6071 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL()
6072 Register ConstantReg = OffsetInst->getOperand(2).getReg(); in selectExtendedSHL()
6123 OffsetReg = ExtInst->getOperand(1).getReg(); in selectExtendedSHL()
6127 MachineIRBuilder MIB(*MRI.getVRegDef(Root.getReg())); in selectExtendedSHL()
6133 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(Base.getReg()); }, in selectExtendedSHL()
6171 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeShiftedExtendXReg()
6178 getDefIgnoringCopies(PtrAdd->getOperand(2).getReg(), MRI); in selectAddrModeShiftedExtendXReg()
6198 MachineInstr *Gep = MRI.getVRegDef(Root.getReg()); in selectAddrModeRegisterOffset()
6205 if (!MRI.hasOneNonDBGUse(Gep->getOperand(0).getReg())) in selectAddrModeRegisterOffset()
6210 MIB.addUse(Gep->getOperand(1).getReg()); in selectAddrModeRegisterOffset()
6213 MIB.addUse(Gep->getOperand(2).getReg()); in selectAddrModeRegisterOffset()
6232 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeXRO()
6250 getIConstantVRegValWithLookThrough(PtrAdd->getOperand(2).getReg(), MRI); in selectAddrModeXRO()
6305 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeWRO()
6311 MachineInstr *OffsetInst = getDefIgnoringCopies(RHS.getReg(), MRI); in selectAddrModeWRO()
6348 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(), in selectAddrModeWRO()
6353 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(LHS.getReg()); }, in selectAddrModeWRO()
6378 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeUnscaled()
6383 MachineInstr *RHS = MRI.getVRegDef(OffImm.getReg()); in selectAddrModeUnscaled()
6411 MachineInstr &Adrp = *MRI.getVRegDef(RootDef.getOperand(1).getReg()); in tryFoldAddLowIntoImm()
6430 Register AdrpReg = Adrp.getOperand(0).getReg(); in tryFoldAddLowIntoImm()
6451 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeIndexed()
6470 MachineInstr *LHSDef = MRI.getVRegDef(LHS.getReg()); in selectAddrModeIndexed()
6471 MachineInstr *RHSDef = MRI.getVRegDef(RHS.getReg()); in selectAddrModeIndexed()
6529 MachineInstr *ShiftInst = MRI.getVRegDef(Root.getReg()); in selectShiftedRegister()
6547 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister()
6565 Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in getExtendTypeForInst()
6582 unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in getExtendTypeForInst()
6629 return Copy.getReg(0); in moveScalarRegClass()
6645 MachineInstr *RootDef = getDefIgnoringCopies(Root.getReg(), MRI); in selectArithExtendedRegister()
6664 MachineInstr *ExtDef = getDefIgnoringCopies(LHS.getReg(), MRI); in selectArithExtendedRegister()
6670 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6676 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6707 getIConstantVRegSExtVal(MI.getOperand(0).getReg(), MRI); in renderTruncImm()
6779 if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() != 32) in isDef32()
6803 Register DstReg = MI.getOperand(0).getReg(); in fixupPHIOpBanks()
6812 Register OpReg = MO.getReg(); in fixupPHIOpBanks()
6827 MRI.setRegBank(Copy.getReg(0), *DstRB); in fixupPHIOpBanks()
6828 MO.setReg(Copy.getReg(0)); in fixupPHIOpBanks()
6870 const LLT &Ty = MRI.getType(MO.getReg()); in processPHIs()
6875 const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg()); in processPHIs()