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/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp1510 .addReg(DstLoReg); in expandLSLW4Rd()
1548 .addReg(DstLoReg); in expandLSLW8Rd()
1575 .addReg(DstLoReg); in expandLSLW12Rd()
1746 .addReg(DstHiReg); in expandLSRW8Rd()
1773 .addReg(DstHiReg); in expandLSRW12Rd()
1909 .addReg(DstHiReg); in expandASRW7Rd()
1945 .addReg(DstHiReg); in expandASRW8Rd()
2004 .addReg(DstLoReg); in expandASRW14Rd()
2054 .addReg(DstHiReg); in expandASRW15Rd()
2193 .addReg(DstReg) in expandASRB6Rd()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
204 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicRMW128()
266 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
286 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
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H A DPPCFrameLowering.cpp872 .addReg(SPReg); in emitPrologue()
885 .addReg(SPReg) in emitPrologue()
886 .addReg(SPReg); in emitPrologue()
969 .addReg(SPReg); in emitPrologue()
1145 .addReg(SPReg) in emitPrologue()
1146 .addReg(SPReg); in emitPrologue()
1768 .addReg(SPReg); in emitEpilogue()
1782 .addReg(RBReg); in emitEpilogue()
1790 .addReg(RBReg); in emitEpilogue()
1809 .addReg(RBReg); in emitEpilogue()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB); in expandAtomicCmpSwapSubword()
165 .addReg(Ptr) in expandAtomicCmpSwapSubword()
169 .addReg(ZERO) in expandAtomicCmpSwapSubword()
280 .addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB); in expandAtomicCmpSwap()
288 .addReg(Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwap()
534 .addReg(OldVal).addReg(Mask2); in expandAtomicBinOpSubword()
536 .addReg(StoreVal).addReg(BinOpRes); in expandAtomicBinOpSubword()
538 .addReg(StoreVal).addReg(Ptr).addImm(0); in expandAtomicBinOpSubword()
540 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB); in expandAtomicBinOpSubword()
550 .addReg(OldVal).addReg(Mask); in expandAtomicBinOpSubword()
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H A DMipsFastISel.cpp328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
649 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
667 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
673 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
1060 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp234 .addReg(AddrReg); in doAtomicBinOpExpansion()
248 .addReg(AddrReg) in doAtomicBinOpExpansion()
272 .addReg(MaskReg); in insertMaskedMerge()
300 .addReg(AddrReg); in doMaskedAtomicBinOpExpansion()
333 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
383 .addReg(ValReg) in insertSext()
386 .addReg(ValReg) in insertSext()
440 .addReg(AddrReg); in expandAtomicMinMaxOp()
442 .addReg(DestReg) in expandAtomicMinMaxOp()
445 .addReg(DestReg) in expandAtomicMinMaxOp()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp159 .addReg(SystemZ::R7D) in emitInstruction()
161 .addReg(0); in emitInstruction()
175 .addReg(SystemZ::R7D) in emitInstruction()
177 .addReg(0); in emitInstruction()
185 .addReg(SystemZ::R14D) in emitInstruction()
194 .addReg(SystemZ::R14D) in emitInstruction()
203 .addReg(SystemZ::R14D) in emitInstruction()
212 .addReg(SystemZ::R14D) in emitInstruction()
221 .addReg(SystemZ::R14D) in emitInstruction()
230 .addReg(SystemZ::R14D) in emitInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp188 .addReg(0)); in runOnMachineFunction()
1411 .addReg(0) in emitInstruction()
1413 .addReg(0)); in emitInstruction()
1457 .addReg(0) in emitInstruction()
1466 .addReg(0) in emitInstruction()
1477 .addReg(0) in emitInstruction()
1901 .addReg(0) in emitInstruction()
2024 .addReg(0) in emitInstruction()
2041 .addReg(0) in emitInstruction()
2051 .addReg(0) in emitInstruction()
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H A DARMExpandPseudoInsts.cpp874 MIB.addReg(D0); in ExpandVTBL()
1041 .addReg(DstReg); in ExpandMOV32BitImm()
1351 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1591 .addReg(Reg) in CMSERestoreFPRegsV8()
1597 .addReg(Reg) in CMSERestoreFPRegsV8()
1658 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1769 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1792 .addReg(NewReg) in ExpandCMP_SWAP()
1793 .addReg(AddrReg); in ExpandCMP_SWAP()
1963 PushMIB.addReg( in CMSEPushCalleeSaves()
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/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/X86/
H A DX86TestBase.cpp21 .addReg(X86::XMM2) in getSimpleInsts()
22 .addReg(X86::XMM1) in getSimpleInsts()
23 .addReg(X86::XMM0)); in getSimpleInsts()
26 .addReg(X86::XMM3) in getSimpleInsts()
27 .addReg(X86::XMM2) in getSimpleInsts()
28 .addReg(X86::XMM2)); in getSimpleInsts()
31 .addReg(X86::XMM4) in getSimpleInsts()
32 .addReg(X86::XMM3) in getSimpleInsts()
33 .addReg(X86::XMM3)); in getSimpleInsts()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
177 MIB.addReg(AM.Base.Reg); in addFullAddress()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
189 return MIB.addReg(0); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
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/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp153 .addReg(VE::SX11) in emitPrologueInsns()
156 .addReg(VE::SX9); in emitPrologueInsns()
158 .addReg(VE::SX11) in emitPrologueInsns()
165 .addReg(VE::SX11) in emitPrologueInsns()
170 .addReg(VE::SX11) in emitPrologueInsns()
177 .addReg(VE::SX11) in emitPrologueInsns()
201 .addReg(VE::SX11) in emitEpilogueInsns()
206 .addReg(VE::SX11) in emitEpilogueInsns()
210 .addReg(VE::SX11) in emitEpilogueInsns()
216 .addReg(VE::SX11) in emitEpilogueInsns()
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H A DVERegisterInfo.cpp223 .addReg(clobber) in prepareReplaceFI()
224 .addReg(FrameReg) in prepareReplaceFI()
255 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg); in processSTQ()
311 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM()
364 .addReg(DestReg); in processLDVM()
369 .addReg(DestReg); in processLDVM()
393 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM512()
404 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM512()
441 .addReg(DestLoReg); in processLDVM512()
451 .addReg(DestHiReg); in processLDVM512()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp566 .addReg(StReg[0]) in optimizeLdStInterleave()
567 .addReg(StReg[1]); in optimizeLdStInterleave()
573 .addReg(ZipDest[0]) in optimizeLdStInterleave()
574 .addReg(ZipDest[1]) in optimizeLdStInterleave()
575 .addReg(AddrReg) in optimizeLdStInterleave()
588 .addReg(StReg[0]) in optimizeLdStInterleave()
589 .addReg(StReg[2]); in optimizeLdStInterleave()
594 .addReg(StReg[1]) in optimizeLdStInterleave()
595 .addReg(StReg[3]); in optimizeLdStInterleave()
615 .addReg(AddrReg) in optimizeLdStInterleave()
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H A DAArch64AsmPrinter.cpp399 .addReg(AArch64::W16) in emitHwasanMemaccessSymbols()
401 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
407 .addReg(AArch64::XZR) in emitHwasanMemaccessSymbols()
408 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
409 .addReg(Reg) in emitHwasanMemaccessSymbols()
461 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
462 .addReg(Reg) in emitHwasanMemaccessSymbols()
486 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
487 .addReg(Reg) in emitHwasanMemaccessSymbols()
499 .addReg(Reg) in emitHwasanMemaccessSymbols()
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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp62 .addReg(Reg) in loadImmediate()
104 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
110 MCInstBuilder(PPC::MTVRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
114 .addReg(Reg) in setRegTo()
115 .addReg(ScratchImmReg) in setRegTo()
116 .addReg(ScratchImmReg)}; in setRegTo()
119 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp71 .addReg(FrameReg) in InsertFPImmInst()
78 .addReg(FrameReg) in InsertFPImmInst()
84 .addReg(FrameReg) in InsertFPImmInst()
107 .addReg(FrameReg) in InsertFPConstInst()
108 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
114 .addReg(FrameReg) in InsertFPConstInst()
115 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
120 .addReg(FrameReg) in InsertFPConstInst()
184 .addReg(ScratchBase, RegState::Kill) in InsertSPConstInst()
191 .addReg(ScratchBase, RegState::Kill) in InsertSPConstInst()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp392 .addReg(DstLo) in selectG_ADD_SUB()
394 .addReg(DstHi) in selectG_ADD_SUB()
835 .addReg(M0Val); in selectInterpP1F16()
2305 .addReg(HiReg) in selectG_FNEG()
2308 .addReg(LoReg) in selectG_FNEG()
2310 .addReg(OpReg) in selectG_FNEG()
2346 .addReg(HiReg) in selectG_FABS()
2349 .addReg(LoReg) in selectG_FABS()
2351 .addReg(OpReg) in selectG_FABS()
3136 .addReg(Data) in selectGlobalAtomicFadd()
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H A DSIFrameLowering.cpp40 LiveRegs.addReg(CSRegs[i]); in findScratchNonCalleeSaveRegister()
138 LiveRegs.addReg(SpillReg); in buildPrologSpill()
187 .addReg(GitPtrLo); in buildGitPtr()
254 .addReg(FlatScrInit) in emitEntryFunctionFlatScratchInit()
303 .addReg(FlatScrInitLo) in emitEntryFunctionFlatScratchInit()
307 .addReg(FlatScrInitHi) in emitEntryFunctionFlatScratchInit()
564 .addReg(Rsrc01) in emitEntryFunctionScratchRsrcRegSetup()
581 .addReg(Rsrc03); in emitEntryFunctionScratchRsrcRegSetup()
821 .addReg(Reg); in emitPrologue()
836 .addReg(Reg) in emitPrologue()
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/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/ARM/
H A DAssemblerTest.cpp37 .addReg(ARM::R0) in TEST_F()
38 .addReg(ARM::R0) in TEST_F()
39 .addReg(ARM::R0) in TEST_F()
41 .addReg(0) in TEST_F()
42 .addReg(0), in TEST_F()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp90 .addReg(Reg) in loadImmediate()
91 .addReg(ZeroReg) in loadImmediate()
103 .addReg(Reg) in loadImmediate()
104 .addReg(ZeroReg) in loadImmediate()
108 .addReg(Reg) in loadImmediate()
109 .addReg(Reg) in loadImmediate()
114 .addReg(Reg) in loadImmediate()
122 .addReg(Reg) in loadImmediate()
123 .addReg(ZeroReg) in loadImmediate()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp250 .addReg(DstReg) in movImm()
266 .addReg(DstReg) in movImm()
271 .addReg(DstReg) in movImm()
279 .addReg(DstReg) in movImm()
284 .addReg(DstReg) in movImm()
288 .addReg(DstReg) in movImm()
301 .addReg(DstReg) in movImm()
310 .addReg(DstReg) in movImm()
319 .addReg(DstReg) in movImm()
513 .addReg(DestReg) in copyPhysReg()
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/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DAssemblerTest.cpp46 MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX), in TEST_F()
54 Check({}, MCInstBuilder(MOV64ri32).addReg(RAX).addImm(42), 0x48, 0xc7, 0xc0, in TEST_F()
59 Check({}, MCInstBuilder(MOV32ri).addReg(EAX).addImm(42), 0xb8, 0x2a, 0x00, in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp659 .addReg(P.first); in splitMemRef()
663 .addReg(P.second); in splitMemRef()
675 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
809 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
849 .addReg(TmpR) in splitShift()
859 .addReg(TmpR) in splitShift()
945 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
960 .addReg(TmpR1); in splitAslOr()
962 .addReg(TmpR2) in splitAslOr()
1114 .addReg(Pr.first) in collapseRegPairs()
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