Lines Matching refs:addReg
217 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
222 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
365 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
368 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
377 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
400 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
418 .addReg(MFI->getGlobalBaseReg(*MF)) in materializeGV()
424 .addReg(DestReg) in materializeGV()
435 .addReg(MFI->getGlobalBaseReg(*MF)) in materializeExternalCallSym()
649 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
650 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
656 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
660 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
663 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
667 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
668 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
673 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
674 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
681 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
686 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
692 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
738 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
739 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
740 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) in emitCmp()
741 .addReg(RightReg); in emitCmp()
743 .addReg(RegWithOne) in emitCmp()
744 .addReg(Mips::FCC0) in emitCmp()
745 .addReg(RegWithZero); in emitCmp()
847 .addReg(SrcReg) in emitStore()
971 .addReg(ZExtCondReg) in selectBranch()
1004 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
1058 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
1060 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1084 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
1123 emitInst(Opc, TempReg).addReg(SrcReg); in selectFPToInt()
1124 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1225 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1296 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1466 .addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
1551 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1554 Mips::RA).addReg(Mips::T9); in fastLowerCall()
1558 MIB.addReg(Reg, RegState::Implicit); in fastLowerCall()
1599 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1609 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1610 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1611 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1612 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); in fastLowerIntrinsicCall()
1619 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1620 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1631 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1632 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1633 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1634 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1636 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1637 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1639 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1640 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1641 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1760 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg); in selectRet()
1767 MIB.addReg(RetRegs[i], RegState::Implicit); in selectRet()
1837 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1838 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1848 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1851 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1884 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); in emitIntZExt()
1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
1938 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
2000 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
2023 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
2110 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()
2131 .addReg(Op0) in fastEmitInst_rr()
2132 .addReg(Op1) in fastEmitInst_rr()
2133 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2134 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()