Lines Matching refs:addReg
171 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
172 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
173 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
177 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
178 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
179 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
205 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
206 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
207 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
214 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
215 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLogic()
216 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandLogic()
254 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogicImm()
255 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expandLogicImm()
265 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogicImm()
266 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expandLogicImm()
304 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
305 .addReg(DstLoReg, getKillRegState(SrcIsKill)); in expand()
309 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
310 .addReg(DstHiReg, getKillRegState(SrcIsKill)); in expand()
363 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
364 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expand()
372 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
373 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expand()
425 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
426 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
433 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
434 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
456 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
457 .addReg(DstHiReg, RegState::Kill); in expand()
463 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
464 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
469 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
470 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
471 .addReg(ZERO_REGISTER); in expand()
497 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
498 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
501 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
502 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
529 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
530 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
536 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
537 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
561 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
565 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
612 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
616 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
667 .addReg(CurDstLoReg, RegState::Define) in expand()
668 .addReg(SrcReg); in expand()
672 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
676 .addReg(CurDstHiReg, RegState::Define) in expand()
677 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
682 buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg); in expand()
711 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
712 .addReg(SrcReg, RegState::Define) in expand()
713 .addReg(SrcReg, RegState::Kill); in expand()
717 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
718 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead)) in expand()
719 .addReg(SrcReg, RegState::Kill); in expand()
744 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
745 .addReg(SrcReg, RegState::Define) in expand()
746 .addReg(SrcReg, RegState::Kill); in expand()
750 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
751 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead)) in expand()
752 .addReg(SrcReg, RegState::Kill); in expand()
787 .addReg(CurDstLoReg, RegState::Define) in expand()
788 .addReg(SrcReg) in expand()
793 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
797 .addReg(CurDstHiReg, RegState::Define) in expand()
798 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
803 buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg); in expand()
832 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank); in expandLPMWELPMW()
844 .addReg(CurDstLoReg, RegState::Define) in expandLPMWELPMW()
845 .addReg(SrcReg); in expandLPMWELPMW()
849 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expandLPMWELPMW()
853 .addReg(CurDstHiReg, RegState::Define) in expandLPMWELPMW()
854 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expandLPMWELPMW()
858 buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg); in expandLPMWELPMW()
891 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(BankReg); in expand()
895 .addReg(DstReg, RegState::Define) in expand()
896 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expand()
926 .addReg(SCRATCH_REGISTER, RegState::Define) in expandAtomic()
937 .addReg(SCRATCH_REGISTER); in expandAtomic()
1049 MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1050 MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
1073 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1074 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1077 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1079 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
1104 .addReg(DstReg, RegState::Define) in expand()
1105 .addReg(DstReg, RegState::Kill) in expand()
1106 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1111 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1112 .addReg(DstReg, RegState::Kill) in expand()
1113 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1139 .addReg(DstReg, RegState::Define) in expand()
1140 .addReg(DstReg, RegState::Kill) in expand()
1141 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1146 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1147 .addReg(DstReg, RegState::Kill) in expand()
1148 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1172 buildMI(MBB, MBBI, AVR::PUSHWRr).addReg(DstReg); in expand()
1176 .addReg(DstReg, RegState::Define) in expand()
1177 .addReg(DstReg, RegState::Kill) in expand()
1181 .addReg(DstReg, RegState::Kill) in expand()
1182 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expand()
1194 .addReg(DstReg) in expand()
1196 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1199 .addReg(DstReg, getKillRegState(DstIsKill)) in expand()
1201 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
1266 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1271 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1299 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
1303 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1325 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1330 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1375 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1376 .addReg(DstReg, RegState::Kill) in expand()
1377 .addReg(DstReg, RegState::Kill); in expand()
1381 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1382 .addReg(DstReg, getKillRegState(DstIsKill)) in expand()
1383 .addReg(ZERO_REGISTER); in expand()
1408 buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0); in expand()
1411 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg); in expand()
1414 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7); in expand()
1434 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1435 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
1436 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1440 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1441 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
1442 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1467 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1468 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
1469 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1490 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1491 .addReg(DstHiReg, RegState::Kill); in expandLSLW4Rd()
1493 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1494 .addReg(DstLoReg, RegState::Kill); in expandLSLW4Rd()
1499 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1500 .addReg(DstHiReg, RegState::Kill) in expandLSLW4Rd()
1508 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1509 .addReg(DstHiReg, RegState::Kill) in expandLSLW4Rd()
1510 .addReg(DstLoReg); in expandLSLW4Rd()
1517 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1518 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW4Rd()
1526 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1527 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSLW4Rd()
1528 .addReg(DstLoReg); in expandLSLW4Rd()
1547 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW8Rd()
1548 .addReg(DstLoReg); in expandLSLW8Rd()
1553 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW8Rd()
1554 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW8Rd()
1555 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandLSLW8Rd()
1574 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1575 .addReg(DstLoReg); in expandLSLW12Rd()
1579 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1580 .addReg(DstHiReg, RegState::Kill); in expandLSLW12Rd()
1585 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1586 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSLW12Rd()
1594 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1595 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW12Rd()
1596 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandLSLW12Rd()
1635 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1636 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1640 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1641 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1666 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1667 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1688 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1689 .addReg(DstHiReg, RegState::Kill); in expandLSRW4Rd()
1691 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1692 .addReg(DstLoReg, RegState::Kill); in expandLSRW4Rd()
1697 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1698 .addReg(DstLoReg, RegState::Kill) in expandLSRW4Rd()
1706 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1707 .addReg(DstLoReg, RegState::Kill) in expandLSRW4Rd()
1708 .addReg(DstHiReg); in expandLSRW4Rd()
1715 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1716 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSRW4Rd()
1724 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1725 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSRW4Rd()
1726 .addReg(DstHiReg); in expandLSRW4Rd()
1745 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW8Rd()
1746 .addReg(DstHiReg); in expandLSRW8Rd()
1751 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW8Rd()
1752 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSRW8Rd()
1753 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandLSRW8Rd()
1772 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1773 .addReg(DstHiReg); in expandLSRW12Rd()
1777 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1778 .addReg(DstLoReg, RegState::Kill); in expandLSRW12Rd()
1783 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1784 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSRW12Rd()
1792 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1793 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSRW12Rd()
1794 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandLSRW12Rd()
1845 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1846 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1850 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1851 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1876 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1877 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1902 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
1903 .addReg(DstLoReg, RegState::Kill) in expandASRW7Rd()
1904 .addReg(DstLoReg, RegState::Kill); in expandASRW7Rd()
1908 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
1909 .addReg(DstHiReg); in expandASRW7Rd()
1913 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
1914 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandASRW7Rd()
1915 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandASRW7Rd()
1920 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
1921 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandASRW7Rd()
1922 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandASRW7Rd()
1944 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
1945 .addReg(DstHiReg); in expandASRW8Rd()
1949 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
1950 .addReg(DstHiReg, RegState::Kill) in expandASRW8Rd()
1951 .addReg(DstHiReg, RegState::Kill); in expandASRW8Rd()
1956 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
1957 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandASRW8Rd()
1958 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandASRW8Rd()
1985 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
1986 .addReg(DstHiReg, RegState::Kill) in expandASRW14Rd()
1987 .addReg(DstHiReg, RegState::Kill); in expandASRW14Rd()
1991 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
1992 .addReg(DstLoReg, RegState::Kill) in expandASRW14Rd()
1993 .addReg(DstLoReg, RegState::Kill); in expandASRW14Rd()
1997 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
1998 .addReg(DstHiReg, RegState::Kill) in expandASRW14Rd()
1999 .addReg(DstHiReg, RegState::Kill); in expandASRW14Rd()
2003 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2004 .addReg(DstLoReg); in expandASRW14Rd()
2009 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2010 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandASRW14Rd()
2011 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandASRW14Rd()
2036 .addReg(DstHiReg, RegState::Define) in expandASRW15Rd()
2037 .addReg(DstHiReg, RegState::Kill) in expandASRW15Rd()
2038 .addReg(DstHiReg, RegState::Kill); in expandASRW15Rd()
2043 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW15Rd()
2044 .addReg(DstHiReg, RegState::Kill) in expandASRW15Rd()
2045 .addReg(DstHiReg, RegState::Kill); in expandASRW15Rd()
2053 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW15Rd()
2054 .addReg(DstHiReg); in expandASRW15Rd()
2091 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2092 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2097 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2098 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2099 .addReg(DstReg, RegState::Kill); in expandLSLB7Rd()
2103 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2104 .addReg(DstReg, getKillRegState(DstIsKill)); in expandLSLB7Rd()
2141 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2142 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2143 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2148 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2149 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2150 .addReg(DstReg, RegState::Kill); in expandLSRB7Rd()
2154 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2155 .addReg(DstReg, getKillRegState(DstIsKill)) in expandLSRB7Rd()
2156 .addReg(DstReg, getKillRegState(DstIsKill)); in expandLSRB7Rd()
2193 .addReg(DstReg) in expandASRB6Rd()
2199 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2200 .addReg(DstReg, RegState::Kill) in expandASRB6Rd()
2201 .addReg(DstReg, RegState::Kill); in expandASRB6Rd()
2204 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2205 .addReg(DstReg, RegState::Kill) in expandASRB6Rd()
2206 .addReg(DstReg, RegState::Kill); in expandASRB6Rd()
2209 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2210 .addReg(DstReg, getKillRegState(DstIsKill)) in expandASRB6Rd()
2230 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2231 .addReg(DstReg, RegState::Kill) in expandASRB7Rd()
2232 .addReg(DstReg, RegState::Kill); in expandASRB7Rd()
2236 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2237 .addReg(DstReg, getKillRegState(DstIsKill)) in expandASRB7Rd()
2238 .addReg(DstReg, getKillRegState(DstIsKill)); in expandASRB7Rd()
2290 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2291 .addReg(SrcReg); in expand()
2295 .addReg(DstHiReg, RegState::Define) in expand()
2296 .addReg(SrcReg); in expand()
2302 .addReg(DstHiReg, RegState::Define) in expand()
2303 .addReg(DstHiReg, RegState::Kill) in expand()
2304 .addReg(DstHiReg, RegState::Kill); in expand()
2308 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2309 .addReg(DstHiReg, RegState::Kill) in expand()
2310 .addReg(DstHiReg, RegState::Kill); in expand()
2342 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2343 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expand()
2348 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2349 .addReg(DstHiReg, RegState::Kill | RegState::Undef) in expand()
2350 .addReg(DstHiReg, RegState::Kill | RegState::Undef); in expand()
2372 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2378 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2397 .addReg(AVR::R0, RegState::Define) in expand()
2405 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
2410 .addReg(AVR::R0, RegState::Kill) in expand()
2415 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()