Lines Matching refs:addReg
605 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
609 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
611 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
613 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
615 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
677 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
738 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
740 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
742 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
744 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
753 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
797 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
799 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
801 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
803 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
824 MIB.addReg(D0, SrcFlags); in ExpandLaneOp()
826 MIB.addReg(D1, SrcFlags); in ExpandLaneOp()
828 MIB.addReg(D2, SrcFlags); in ExpandLaneOp()
830 MIB.addReg(D3, SrcFlags); in ExpandLaneOp()
845 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
874 MIB.addReg(D0); in ExpandVTBL()
885 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); in ExpandVTBL()
908 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags); in ExpandMQQPRLoadStore()
909 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags); in ExpandMQQPRLoadStore()
910 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags); in ExpandMQQPRLoadStore()
911 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags); in ExpandMQQPRLoadStore()
914 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags); in ExpandMQQPRLoadStore()
915 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags); in ExpandMQQPRLoadStore()
916 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags); in ExpandMQQPRLoadStore()
917 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags); in ExpandMQQPRLoadStore()
921 MIB.addReg(SrcReg, RegState::Implicit); in ExpandMQQPRLoadStore()
997 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
998 .addReg(DstReg); in ExpandMOV32BitImm()
1004 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1005 .addReg(DstReg); in ExpandMOV32BitImm()
1018 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1019 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1040 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1041 .addReg(DstReg); in ExpandMOV32BitImm()
1073 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
1074 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
1116 CLRM.addReg(R, RegState::Define); in CMSEClearGPRegs()
1117 CLRM.addReg(ARM::APSR, RegState::Define); in CMSEClearGPRegs()
1118 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1126 .addReg(ClobberReg) in CMSEClearGPRegs()
1132 .addReg(ClobberReg) in CMSEClearGPRegs()
1235 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1242 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1251 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1252 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1259 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1266 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1277 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1282 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1287 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1313 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1314 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1324 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1325 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1351 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1372 .addReg(SaveReg1, RegState::Define) in CMSESaveClearFPRegsV8()
1373 .addReg(SaveReg2, RegState::Define) in CMSESaveClearFPRegsV8()
1374 .addReg(Reg) in CMSESaveClearFPRegsV8()
1386 .addReg(Reg) in CMSESaveClearFPRegsV8()
1403 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1407 VLSTM.addReg(R, RegState::Implicit | in CMSESaveClearFPRegsV8()
1416 .addReg(SaveReg1) in CMSESaveClearFPRegsV8()
1417 .addReg(SaveReg2) in CMSESaveClearFPRegsV8()
1421 .addReg(SaveReg1) in CMSESaveClearFPRegsV8()
1429 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1437 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1441 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1447 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1456 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1460 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1465 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1470 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1491 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1497 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1501 VLSTM.addReg(R, RegState::Implicit | in CMSESaveClearFPRegsV81()
1507 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1510 VPUSH.addReg(Reg); in CMSESaveClearFPRegsV81()
1517 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1559 .addReg(SaveReg1, RegState::Define) in CMSERestoreFPRegsV8()
1560 .addReg(SaveReg2, RegState::Define) in CMSERestoreFPRegsV8()
1561 .addReg(Reg) in CMSERestoreFPRegsV8()
1573 .addReg(Reg) in CMSERestoreFPRegsV8()
1591 .addReg(Reg) in CMSERestoreFPRegsV8()
1592 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1597 .addReg(Reg) in CMSERestoreFPRegsV8()
1598 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1606 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1613 .addReg(ScratchReg, RegState::Define) in CMSERestoreFPRegsV8()
1618 .addReg(ScratchReg) in CMSERestoreFPRegsV8()
1631 .addReg(ARM::S0, RegState::Define) in CMSERestoreFPRegsV8()
1632 .addReg(ARM::S0, RegState::Undef) in CMSERestoreFPRegsV8()
1647 .addReg(SaveReg1) in CMSERestoreFPRegsV8()
1648 .addReg(SaveReg2) in CMSERestoreFPRegsV8()
1652 .addReg(SaveReg1) in CMSERestoreFPRegsV8()
1658 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1683 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
1688 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1693 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1700 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1707 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1710 VPOP.addReg(Reg, RegState::Define); in CMSERestoreFPRegsV81()
1756 .addReg(DesiredReg, RegState::Kill); in ExpandCMP_SWAP()
1769 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1776 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) in ExpandCMP_SWAP()
1777 .addReg(DesiredReg) in ExpandCMP_SWAP()
1783 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1792 .addReg(NewReg) in ExpandCMP_SWAP()
1793 .addReg(AddrReg); in ExpandCMP_SWAP()
1801 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP()
1807 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1842 MIB.addReg(RegLo, Flags); in addExclusiveRegPair()
1843 MIB.addReg(RegHi, Flags); in addExclusiveRegPair()
1845 MIB.addReg(Reg.getReg(), Flags); in addExclusiveRegPair()
1889 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1893 .addReg(DestLo, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
1894 .addReg(DesiredLo) in ExpandCMP_SWAP_64()
1898 .addReg(DestHi, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
1899 .addReg(DesiredHi) in ExpandCMP_SWAP_64()
1900 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1906 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1918 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1922 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP_64()
1928 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1963 PushMIB.addReg( in CMSEPushCalleeSaves()
1978 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
1987 PushMIB2.addReg(Reg, RegState::Kill); in CMSEPushCalleeSaves()
1996 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2000 .addReg(LoReg, RegState::Kill); in CMSEPushCalleeSaves()
2005 .addReg(ARM::SP) in CMSEPushCalleeSaves()
2008 PushMIB.addReg( in CMSEPushCalleeSaves()
2023 PopMIB.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2025 .addReg(ARM::R4 + R, RegState::Kill) in CMSEPopCalleeSaves()
2031 PopMIB2.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2035 .addReg(ARM::SP) in CMSEPopCalleeSaves()
2038 PopMIB.addReg(Reg, RegState::Define); in CMSEPopCalleeSaves()
2089 .addReg(DstReg, in ExpandMI()
2098 .addReg(DstReg, in ExpandMI()
2162 .addReg(JumpTarget.getReg(), RegState::Kill); in ExpandMI()
2190 .addReg(ARM::SP) in ExpandMI()
2211 .addReg(ARM::LR) in ExpandMI()
2250 .addReg(JumpReg) in ExpandMI()
2263 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2264 .addReg(JumpReg) in ExpandMI()
2265 .addReg(ScratchReg) in ExpandMI()
2276 .addReg(JumpReg, RegState::Kill); in ExpandMI()
2446 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
2465 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2508 MIB.addReg(Reg, RegState::Kill); in ExpandMI()
2538 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2539 .addReg(DstReg) in ExpandMI()
2597 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2598 .addReg(DstReg) in ExpandMI()
2632 .addReg(DstReg) in ExpandMI()
2638 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2639 .addReg(DstReg).addImm(LabelId); in ExpandMI()
2660 .addReg(ARM::LR) in ExpandMI()
2664 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
2689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2690 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
2693 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
2721 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) in ExpandMI()
2722 .addReg(D1, SrcIsKill ? RegState::Kill : 0); in ExpandMI()
3079 .addReg(Reg); in ExpandMI()
3086 .addReg(ARM::SP, RegState::Define) in ExpandMI()
3087 .addReg(ARM::SP) in ExpandMI()
3089 .addReg(Reg); in ExpandMI()
3123 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
3125 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()