648              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
651               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
657              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
659              .addReg(P.first);  in splitMemRef()
661               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
663               .addReg(P.second);  in splitMemRef()
675       .addReg(AdrOp.getReg(), RSA)  in splitMemRef()
741       .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());  in splitCombine()
749       .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());  in splitCombine()
767     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
769     .addReg(Op1.getReg(), RS, Op1.getSubReg())  in splitExt()
807       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
809       .addReg(Op1.getReg(), RS, HiSR);  in splitShift()
832         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
835         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
838         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
844         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
849         .addReg(TmpR)  in splitShift()
850         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
855         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
859         .addReg(TmpR)  in splitShift()
860         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
866       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
872         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
878         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
881         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
884         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
889         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
942       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
943       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);  in splitAslOr()
945       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
946       .addReg(Op2.getReg(), RS2, HiSR);  in splitAslOr()
949       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
950       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
954       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
959       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
960       .addReg(TmpR1);  in splitAslOr()
962       .addReg(TmpR2)  in splitAslOr()
963       .addReg(Op2.getReg(), RS2, HiSR)  in splitAslOr()
971       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
973       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
974       .addReg(Op2.getReg(), RS2, LoSR);  in splitAslOr()
982       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
984       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
985       .addReg(Op2.getReg(), RS2, LoSR)  in splitAslOr()
1114       .addReg(Pr.first)  in collapseRegPairs()
1116       .addReg(Pr.second)  in collapseRegPairs()