Lines Matching refs:addReg
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
455 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
456 .addReg(DupDest, Src2IsKill); in optimizeVectElement()
462 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
467 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
566 .addReg(StReg[0]) in optimizeLdStInterleave()
567 .addReg(StReg[1]); in optimizeLdStInterleave()
569 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
570 .addReg(StReg[1], StRegKill[1]); in optimizeLdStInterleave()
573 .addReg(ZipDest[0]) in optimizeLdStInterleave()
574 .addReg(ZipDest[1]) in optimizeLdStInterleave()
575 .addReg(AddrReg) in optimizeLdStInterleave()
588 .addReg(StReg[0]) in optimizeLdStInterleave()
589 .addReg(StReg[2]); in optimizeLdStInterleave()
591 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
592 .addReg(StReg[2], StRegKill[2]); in optimizeLdStInterleave()
594 .addReg(StReg[1]) in optimizeLdStInterleave()
595 .addReg(StReg[3]); in optimizeLdStInterleave()
597 .addReg(StReg[1], StRegKill[1]) in optimizeLdStInterleave()
598 .addReg(StReg[3], StRegKill[3]); in optimizeLdStInterleave()
600 .addReg(ZipDest[0]) in optimizeLdStInterleave()
601 .addReg(ZipDest[2]); in optimizeLdStInterleave()
603 .addReg(ZipDest[0]) in optimizeLdStInterleave()
604 .addReg(ZipDest[2]); in optimizeLdStInterleave()
606 .addReg(ZipDest[1]) in optimizeLdStInterleave()
607 .addReg(ZipDest[3]); in optimizeLdStInterleave()
609 .addReg(ZipDest[1]) in optimizeLdStInterleave()
610 .addReg(ZipDest[3]); in optimizeLdStInterleave()
613 .addReg(ZipDest[4]) in optimizeLdStInterleave()
614 .addReg(ZipDest[5]) in optimizeLdStInterleave()
615 .addReg(AddrReg) in optimizeLdStInterleave()
618 .addReg(ZipDest[6]) in optimizeLdStInterleave()
619 .addReg(ZipDest[7]) in optimizeLdStInterleave()
620 .addReg(AddrReg) in optimizeLdStInterleave()