Lines Matching refs:addReg
164 .addReg(SrcReg); in selectCOPY()
167 .addReg(MaskedReg); in selectCOPY()
248 .addReg(Reg, 0, ComposedSubIdx); in getSubOperand64()
384 .addReg(CarryReg, RegState::Kill) in selectG_ADD_SUB()
392 .addReg(DstLo) in selectG_ADD_SUB()
394 .addReg(DstHi) in selectG_ADD_SUB()
432 .addReg(I.getOperand(4).getReg()); in selectG_UADDO_USUBO_UADDE_USUBE()
442 .addReg(AMDGPU::SCC); in selectG_UADDO_USUBO_UADDE_USUBE()
519 .addReg(SrcReg, 0, SubReg); in selectG_EXTRACT()
548 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
592 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
693 .addReg(ShiftSrc0) in selectG_BUILD_VECTOR_TRUNC()
779 .addReg(Src0Reg) in selectG_INSERT()
780 .addReg(Src1Reg) in selectG_INSERT()
804 .addReg(SrcReg) in selectG_SBFX_UBFX()
805 .addReg(OffsetReg) in selectG_SBFX_UBFX()
806 .addReg(WidthReg); in selectG_SBFX_UBFX()
835 .addReg(M0Val); in selectInterpP1F16()
843 .addReg(Src0) // $src0 in selectInterpP1F16()
847 .addReg(InterpMov) // $src2 - 2 f16 values selected by high in selectInterpP1F16()
880 MIB.addReg(Val); in selectWritelane()
892 MIB.addReg(LaneSelect); in selectWritelane()
894 MIB.addReg(Val); in selectWritelane()
902 .addReg(LaneSelect); in selectWritelane()
903 MIB.addReg(AMDGPU::M0); in selectWritelane()
907 MIB.addReg(VDstIn); in selectWritelane()
1115 .addReg(AMDGPU::SCC); in selectG_ICMP()
1197 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(SrcReg); in selectBallot()
1202 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(SrcReg); in selectBallot()
1293 .addReg(LiveIn); in selectReturnAddress()
1359 .addReg(M0Val); in selectDSOrderedIntrinsic()
1365 .addReg(ValReg) in selectDSOrderedIntrinsic()
1459 .addReg(BaseOffset) in selectDSGWSIntrinsic()
1463 .addReg(M0Base); in selectDSGWSIntrinsic()
1473 MIB.addReg(VSrc); in selectDSGWSIntrinsic()
1508 .addReg(PtrBase); in selectDSAppendConsume()
1720 .addReg(TmpReg, RegState::Kill, SubReg); in selectImageIntrinsic()
1729 MIB.addReg(VDataIn); // vdata input in selectImageIntrinsic()
1735 MIB.addReg(SrcOp.getReg()); in selectImageIntrinsic()
1739 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
1741 MIB.addReg(MI.getOperand(ArgOffset + Intr->SampIndex).getReg()); in selectImageIntrinsic()
1784 RegSeq.addReg(Zero).addImm(Sub); in selectImageIntrinsic()
1793 RegSeq.addReg(Undef).addImm(Sub); in selectImageIntrinsic()
1794 RegSeq.addReg(Zero).addImm(Parts.back()); in selectImageIntrinsic()
1796 MIB.addReg(Tied, RegState::Implicit); in selectImageIntrinsic()
1864 .addReg(CCReg); in selectG_SELECT()
1964 .addReg(SrcReg, 0, AMDGPU::sub0); in selectG_TRUNC()
1966 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_TRUNC()
1974 .addReg(HiReg) // $src0 in selectG_TRUNC()
1979 .addReg(LoReg, RegState::Implicit); in selectG_TRUNC()
1988 .addReg(HiReg); in selectG_TRUNC()
1991 .addReg(HiReg) in selectG_TRUNC()
2002 .addReg(LoReg) in selectG_TRUNC()
2003 .addReg(ImmReg); in selectG_TRUNC()
2005 .addReg(TmpReg0) in selectG_TRUNC()
2006 .addReg(TmpReg1); in selectG_TRUNC()
2094 .addReg(SrcReg) in selectG_SZA_EXT()
2096 .addReg(UndefReg) in selectG_SZA_EXT()
2113 .addReg(SrcReg); in selectG_SZA_EXT()
2121 .addReg(SrcReg) in selectG_SZA_EXT()
2138 .addReg(SrcReg); in selectG_SZA_EXT()
2155 .addReg(SrcReg, 0, SubReg) in selectG_SZA_EXT()
2157 .addReg(UndefReg) in selectG_SZA_EXT()
2161 .addReg(ExtReg) in selectG_SZA_EXT()
2171 .addReg(SrcReg) in selectG_SZA_EXT()
2175 .addReg(SrcReg) in selectG_SZA_EXT()
2245 .addReg(LoReg) in selectG_CONSTANT()
2247 .addReg(HiReg) in selectG_CONSTANT()
2296 .addReg(Src, 0, AMDGPU::sub0); in selectG_FNEG()
2298 .addReg(Src, 0, AMDGPU::sub1); in selectG_FNEG()
2305 .addReg(HiReg) in selectG_FNEG()
2306 .addReg(ConstReg); in selectG_FNEG()
2308 .addReg(LoReg) in selectG_FNEG()
2310 .addReg(OpReg) in selectG_FNEG()
2337 .addReg(Src, 0, AMDGPU::sub0); in selectG_FABS()
2339 .addReg(Src, 0, AMDGPU::sub1); in selectG_FABS()
2346 .addReg(HiReg) in selectG_FABS()
2347 .addReg(ConstReg); in selectG_FABS()
2349 .addReg(LoReg) in selectG_FABS()
2351 .addReg(OpReg) in selectG_FABS()
2511 .addReg(CondReg) in selectG_BRCOND()
2512 .addReg(Exec); in selectG_BRCOND()
2525 .addReg(CondReg); in selectG_BRCOND()
2574 .addReg(SrcReg) in selectG_PTRMASK()
2575 .addReg(MaskReg); in selectG_PTRMASK()
2599 .addReg(SrcReg) in selectG_PTRMASK()
2600 .addReg(MaskReg); in selectG_PTRMASK()
2610 .addReg(SrcReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2612 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
2625 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2627 .addReg(LoReg) in selectG_PTRMASK()
2628 .addReg(MaskLo); in selectG_PTRMASK()
2639 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
2641 .addReg(HiReg) in selectG_PTRMASK()
2642 .addReg(MaskHi); in selectG_PTRMASK()
2646 .addReg(MaskedLo) in selectG_PTRMASK()
2648 .addReg(MaskedHi) in selectG_PTRMASK()
2724 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
2728 .addReg(SrcReg, 0, SubReg) in selectG_EXTRACT_VECTOR_ELT()
2729 .addReg(SrcReg, RegState::Implicit); in selectG_EXTRACT_VECTOR_ELT()
2739 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
2741 .addReg(SrcReg, 0, SubReg) in selectG_EXTRACT_VECTOR_ELT()
2742 .addReg(SrcReg, RegState::Implicit); in selectG_EXTRACT_VECTOR_ELT()
2750 .addReg(SrcReg) in selectG_EXTRACT_VECTOR_ELT()
2751 .addReg(IdxReg) in selectG_EXTRACT_VECTOR_ELT()
2808 .addReg(IdxReg); in selectG_INSERT_VECTOR_ELT()
2813 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
2814 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
2823 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
2824 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
2825 .addReg(IdxReg) in selectG_INSERT_VECTOR_ELT()
2906 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2916 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2919 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2926 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2929 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2939 .addReg(SrcVec) // $src0 in selectG_SHUFFLE_VECTOR()
2944 .addReg(SrcVec, RegState::Implicit); in selectG_SHUFFLE_VECTOR()
2950 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2952 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()
2954 .addReg(TmpReg); in selectG_SHUFFLE_VECTOR()
2958 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2959 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2968 .addReg(SrcVec) // $src0 in selectG_SHUFFLE_VECTOR()
2973 .addReg(SrcVec, RegState::Implicit); in selectG_SHUFFLE_VECTOR()
2979 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2981 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()
2983 .addReg(TmpReg); in selectG_SHUFFLE_VECTOR()
2987 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2988 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2993 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2994 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2999 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
3000 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
3004 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
3007 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()
3008 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
3082 .addReg(VIndex.getReg()) in selectAMDGPU_BUFFER_ATOMIC_FADD()
3084 .addReg(VOffset.getReg()) in selectAMDGPU_BUFFER_ATOMIC_FADD()
3087 I.addReg(IdxReg); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3135 .addReg(Addr.first) in selectGlobalAtomicFadd()
3136 .addReg(Data) in selectGlobalAtomicFadd()
3196 .addReg(VIndex) in selectBufferLoadLds()
3198 .addReg(VOffset) in selectBufferLoadLds()
3201 MIB.addReg(IdxReg); in selectBufferLoadLds()
3203 MIB.addReg(VIndex); in selectBufferLoadLds()
3205 MIB.addReg(VOffset); in selectBufferLoadLds()
3311 .addReg(Addr); in selectGlobalLoadLds()
3314 MIB.addReg(VOffset); in selectGlobalLoadLds()
3416 .addReg(SrcReg); in selectWaveAddress()
3419 .addReg(SrcReg) in selectWaveAddress()
3611 .addReg(Src); in selectVOP3ModsImpl()
3635 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods0()
3649 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3BMods0()
3672 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods()
3684 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3BMods()
3697 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3735 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3750 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PModsDOT()
3793 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods_nnan()
3802 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }, in selectVOP3OpSelMods()
3817 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVINTERPMods()
3832 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVINTERPModsHi()
3911 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdImm()
3931 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
3942 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgpr()
3943 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectSmrdSgpr()
3953 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgprImm()
3954 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSmrdSgprImm()
3987 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectFlatOffset()
3997 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectGlobalOffset()
4007 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectScratchOffset()
4053 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr in selectGlobalSAddr()
4055 MIB.addReg(HighBits); in selectGlobalSAddr()
4090 MIB.addReg(SAddr); in selectGlobalSAddr()
4093 MIB.addReg(VOffset); in selectGlobalSAddr()
4118 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()
4119 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
4169 .addReg(RHSDef->Reg); in selectScratchSAddr()
4177 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr in selectScratchSAddr()
4234 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4244 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4245 [=](MachineInstrBuilder &MIB) { MIB.addReg(LHS); }, // saddr in selectScratchSVAddr()
4269 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4272 MIB.addReg(HighBits); in selectMUBUFScratchOffen()
4311 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4317 MIB.addReg(VAddr); in selectMUBUFScratchOffen()
4391 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4394 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4414 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4417 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4429 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4474 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDS1Addr1Offset()
4496 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDSReadWrite2()
4579 .addReg(RSrc2) in buildRSRC()
4581 .addReg(RSrc3) in buildRSRC()
4594 .addReg(RSrcLo) in buildRSRC()
4596 .addReg(RSrcHi) in buildRSRC()
4768 MIB.addReg(RSrcReg); in selectMUBUFAddr64()
4771 MIB.addReg(VAddr); in selectMUBUFAddr64()
4775 MIB.addReg(SOffset); in selectMUBUFAddr64()
4799 MIB.addReg(RSrcReg); in selectMUBUFOffset()
4803 MIB.addReg(SOffset); in selectMUBUFOffset()
4828 MIB.addReg(RSrcReg); in selectMUBUFAddr64Atomic()
4831 MIB.addReg(VAddr); in selectMUBUFAddr64Atomic()
4835 MIB.addReg(SOffset); in selectMUBUFAddr64Atomic()
4859 MIB.addReg(RSrcReg); in selectMUBUFOffsetAtomic()
4863 MIB.addReg(SOffset); in selectMUBUFOffsetAtomic()