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Searched refs:MaskedValueIsZero (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.cpp25 DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { in EmitTargetCodeForMemcpy()
H A DXCoreISelLowering.cpp656 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && in TryExpandADDWithMul()
657 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { in TryExpandADDWithMul()
1757 DAG.MaskedValueIsZero(Mul0, HighMask) && in PerformDAGCombine()
1758 DAG.MaskedValueIsZero(Mul1, HighMask) && in PerformDAGCombine()
1759 DAG.MaskedValueIsZero(Addend0, HighMask) && in PerformDAGCombine()
1760 DAG.MaskedValueIsZero(Addend1, HighMask)) { in PerformDAGCombine()
/llvm-project-15.0.7/llvm/include/llvm/Transforms/InstCombine/
H A DInstCombiner.h473 bool MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth = 0,
475 return llvm::MaskedValueIsZero(V, Mask, DL, Depth, &AC, CxtI, &DT);
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp509 if (IC.MaskedValueIsZero(InnerShift->getOperand(0), Mask, 0, CxtI)) in canEvaluateShiftedShift()
859 MaskedValueIsZero(X, APInt::getHighBitsSet(SrcWidth, ShAmtC), 0, &I)) in visitShl()
1012 MaskedValueIsZero(Op0, APInt::getHighBitsSet(BitWidth, ShAmtC), 0, in visitShl()
1281 MaskedValueIsZero(Op0, APInt::getLowBitsSet(BitWidth, ShAmtC), 0, &I)) { in visitLShr()
1446 MaskedValueIsZero(Op0, APInt::getLowBitsSet(BitWidth, ShAmt), 0, &I)) { in visitAShr()
1472 if (MaskedValueIsZero(Op0, APInt::getSignMask(BitWidth), 0, &I)) in visitAShr()
H A DInstCombineCasts.cpp410 if (IC.MaskedValueIsZero(I->getOperand(0), Mask, 0, CxtI) && in canEvaluateTruncated()
411 IC.MaskedValueIsZero(I->getOperand(1), Mask, 0, CxtI)) { in canEvaluateTruncated()
440 IC.MaskedValueIsZero(I->getOperand(0), ShiftedBits, 0, CxtI)) { in canEvaluateTruncated()
584 if (ShVal0 == ShVal1 || MaskedValueIsZero(L, HiBitMask)) in narrowFunnelShift()
622 if (!MaskedValueIsZero(ShVal1, HiBitMask, 0, &Trunc)) in narrowFunnelShift()
1166 if (IC.MaskedValueIsZero(I->getOperand(1), in canEvaluateZExtd()
1276 if (MaskedValueIsZero(Res, in visitZExt()
H A DInstCombineMulDivRem.cpp1190 if (MaskedValueIsZero(Op0, Mask, 0, &I)) { in visitSDiv()
1191 if (MaskedValueIsZero(Op1, Mask, 0, &I)) { in visitSDiv()
1577 if (MaskedValueIsZero(Op1, Mask, 0, &I) && in visitSRem()
1578 MaskedValueIsZero(Op0, Mask, 0, &I)) { in visitSRem()
H A DInstCombineInternal.h486 bool MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth = 0,
488 return llvm::MaskedValueIsZero(V, Mask, DL, Depth, &AC, CxtI, &DT);
H A DInstCombineAndOrXor.cpp1914 if (MaskedValueIsZero(X, NotAndMask, 0, &I)) { in visitAnd()
1920 if (!isa<Constant>(Y) && MaskedValueIsZero(Y, NotAndMask, 0, &I)) { in visitAnd()
2764 !CV->isAllOnes() && MaskedValueIsZero(Y, *CV, 0, &I)) { in visitOr()
2809 MaskedValueIsZero(X, ~*C0, 0, &I)) { in visitOr()
2816 MaskedValueIsZero(X, ~*C1, 0, &I)) { in visitOr()
3718 MaskedValueIsZero(X, *C, 0, &I)) in visitXor()
H A DInstCombineAddSub.cpp943 if (ShAmt && MaskedValueIsZero(X, APInt::getHighBitsSet(BitWidth, ShAmt), in foldAddWithConstant()
H A DInstCombineVectorOps.cpp1945 if (match(BO1, m_APInt(C)) && MaskedValueIsZero(BO0, *C, DL)) in getAlternateBinop()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp174 if (CurDAG->MaskedValueIsZero(N, Mask)) { in selectZExti32()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp222 if (DAG.MaskedValueIsZero(Base->getOperand(0), C->getAPIntValue())) { in matchLSNode()
H A DDAGCombiner.cpp3342 if (!DAG.MaskedValueIsZero(LHS, UpperBits)) in getTruncatedUSUBSAT()
3475 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) { in visitSUB()
5581 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { in visitANDLike()
6236 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { in visitAND()
6461 if (DAG.MaskedValueIsZero(N1, ExtBits) && in visitAND()
6619 if (!DAG.MaskedValueIsZero(N10, in MatchBSwapHWordLow()
6881 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && in visitORLike()
7054 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) in visitOR()
8797 if (DAG.MaskedValueIsZero(N1, ModuloMask)) in visitRotate()
9709 if (DAG.MaskedValueIsZero( in visitFunnelShift()
[all …]
H A DTargetLowering.cpp3691 if (DAG.MaskedValueIsZero(N0, UpperBits)) in foldSetCCWithAnd()
4464 if (DAG.MaskedValueIsZero(N0, in SimplifySetCC()
4673 DAG.MaskedValueIsZero(LHS, HiBits)) { in SimplifySetCC()
4681 DAG.MaskedValueIsZero(RHS, HiBits)) { in SimplifySetCC()
6989 if (DAG.MaskedValueIsZero(LHS, HighMask) && in expandMUL_LOHI()
6990 DAG.MaskedValueIsZero(RHS, HighMask)) { in expandMUL_LOHI()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp228 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { in MatchAddress()
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DValueTracking.h185 bool MaskedValueIsZero(const Value *V, const APInt &Mask,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td641 return CurDAG->MaskedValueIsZero(N->getOperand(0),
649 return CurDAG->MaskedValueIsZero(N->getOperand(1),
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrMemory.td32 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1874 bool MaskedValueIsZero(SDValue Op, const APInt &Mask,
1880 bool MaskedValueIsZero(SDValue Op, const APInt &Mask,
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp386 if (!MaskedValueIsZero(BOp->getOperand(0), RHSC->getValue(), DL, 0, AC, in GetLinearExpression()
H A DValueTracking.cpp388 static bool MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth,
391 bool llvm::MaskedValueIsZero(const Value *V, const APInt &Mask, in MaskedValueIsZero() function in llvm
395 return ::MaskedValueIsZero( in MaskedValueIsZero()
2963 bool MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth, in MaskedValueIsZero() function
H A DInstructionSimplify.cpp2444 if (MaskedValueIsZero(N, *C2, Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in simplifyOrInst()
2450 if (MaskedValueIsZero(N, *C1, Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in simplifyOrInst()
5661 if (MaskedValueIsZero(Op0, APInt::getHighBitsSet(BitWidth, BitWidth - 1), in simplifyUnaryIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2498 if (!CurDAG->MaskedValueIsZero(Shl.getOperand(0), HighZeros)) in matchAddressRecursively()
4164 if (CurDAG->MaskedValueIsZero(N->getOperand(0), NeededMask)) in tryShrinkShlLogicImm()
4455 if (!CurDAG->MaskedValueIsZero(And0, HighZeros)) in shrinkAndImmediate()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6917 bool LHSIsU = DAG.MaskedValueIsZero(LHS, HighMask); in ReplaceNodeResults()
6918 bool RHSIsU = DAG.MaskedValueIsZero(RHS, HighMask); in ReplaceNodeResults()
8205 if (DAG.MaskedValueIsZero(N0.getOperand(0), SignMask)) in performSETCCCombine()
8374 if (!DAG.MaskedValueIsZero(Op0, Mask)) in combineVWADD_W_VL_VWSUB_W_VL()
8456 if (DAG.MaskedValueIsZero(Op1, Mask)) in combineMUL_VLToVWMUL_VL()
8809 if (isOneConstant(RHS) && DAG.MaskedValueIsZero(LHS, Mask)) { in combine_CC()
H A DRISCVISelDAGToDAG.cpp2017 if (CurDAG->MaskedValueIsZero(N, Mask)) { in selectZExti32()

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